LFE5UM5G

Part: Lattice ECP5 and ECP5-5G Family

Type: FPGA

Key Specs:

• Not specified in this snippet

Features:

• PFU Blocks (Slice, Modes of Operation)
• Routing
• Clocking Structure (sysCLOCK PLL, Clock Distribution Network, Clock Dividers, DDRDLL)
• sysMEM Memory (Block, Bus Size Matching, RAM Initialization and ROM Operation, Memory Cascading, Single, Dual and Pseudo-Dual Port Modes, Memory Core Reset)
• sysDSP™ Slice (Architecture Features)
• Programmable I/O Cells (PIO, Input Register Block, Output Register Block, Tristate Register Block)
• DDR Memory Support (DQS Grouping)
• sysI/O Buffer (Banks, Supported sysI/O Standards, On-Chip Programmable Termination, Hot Socketing)
• SERDES and Physical Coding Sublayer (SERDES Block, Flexible Dual SERDES Architecture)
• IEEE 1149.1-Compliant Boundary Scan Testability
• Device Configuration (Enhanced Configuration Options, Single Event Upset (SEU) Support, On-Chip Oscillator)
• Density Shifting
• PCI Express (2.5 Gb/s, 5 Gb/s) support
• CPRI LV2 E.48 support
• XAUI/CPRI LV E.30 support
• Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12 support
• SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) support

Applications:

• Not specified in this snippet

Package:

• Not specified in this snippet

• Higher Logic Density for Increased System Integration
  • 12K to 84K LUTs
  • 197 to 365 user programmable I/O
• Embedded SERDES
  • 270 Mb/s, up to 3.2 Gb/s, SERDES interface (ECP5)
  • 270 Mb/s, up to 5.0 Gb/s, SERDES interface (ECP5-5G)
  • Supports eDP in RDR (1.62 Gb/s) and HDR
  • (2.7 Gb/s)
  • Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI
• sysDSP™
  • Fully cascadable slice architecture
  • 12 to 160 slices for high performance multiply and accumulate
  • Powerful 54-bit ALU operations
  • Time Division Multiplexing MAC Sharing
  • Rounding and truncation
  • Each slice supports
    • Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers
    • Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations
• Flexible Memory Resources
  • Up to 3.744 Mb sysMEM™ Embedded Block
  • RAM (EBR)
  • 194K to 669K bits distributed RAM

• sysCLOCK Analog PLLs and DLLs

  • Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12

• Pre-Engineered Source Synchronous I/O

  • DDR registers in I/O cells
  • Dedicated read/write levelling functionality
  • Dedicated gearing logic
  • Source synchronous standards support
  • ADC/DAC, 7:1 LVDS, XGMII
  • High Speed ADC/DAC devices
  • Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate

• Programmable sysI/O™ Buffer Supports Wide Range of Interfaces

  • On-chip termination
  • LVTTL and LVCMOS 33/25/18/15/12
  • SSTL 18/15 I, II
  • HSUL12
  • LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
  • subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces

• Flexible Device Configuration

  • Shared bank for configuration I/O
  • SPI boot flash interface
  • Dual-boot images supported
  • Slave SPI
  • TransFR™ I/O for simple field updates

• Single Event Upset (SEU) Mitigation Support

  • Soft Error Detect Embedded hard macro
  • Soft Error Correction Without stopping user operation
  • Soft Error Injection Emulate SEU event to debug system error handling

• System Level Support

  • IEEE 1149.1 and IEEE 1532 compliant
  • Reveal Logic Analyzer
  • On-chip oscillator for initialization and general use
  • V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G

Table 1.1. ECP5 and ECP5-5G Family Selection Guide

Over Recommended Operating Conditions

Table 3.7. DC Electrical Characteristics

Notes:

• 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled.
• 1. TA25 °C, f = 1.0 MHz.
• 1. Applicable to general purpose I/O in top and bottom banks.
• 1. When used as VREF, maximum leakage= 25 μA.

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Table 3.1. Absolute Maximum Ratings

Notes:

• 1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
• 1. Compliance with the Lattice Thermal Management document is required.
• 3. All voltages referenced to GND.

Table 3.2. Recommended Operating Conditions

Notes:

• 1. For correct operation, all supplies except VREF must be held in their valid operation range. This is true independent of feature usage.
• 1. All supplies with same voltage, except SERDES Power Supplies, should be connected together.
• 1. See recommended voltages by I/O standard in Table 3.4.
• 1. VCCAUX ramp rate must not exceed 30 mV/μs during power-up when transitioning between 0 V and 3 V.
• 1. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206) for information on board considerations for SERDES power supplies.
• 1. VCCHRX is used for Rx termination. It can be biased to Vcm if external AC coupling is used. This voltage needs to meet all the HDin input voltage level requirements specified in the Rx section of this Data Sheet.

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 FPGA-DS-02012-2.2