LFE5U

Part: ECP5 and ECP5-5G Family — Lattice Semiconductor

Type: FPGA

Description: Lattice ECP5 and ECP5-5G family of low power, small form factor, and low cost FPGAs featuring high-performance SERDES up to 5 Gbps, flexible I/O, high-performance DSP blocks, and embedded block RAM.

Operating Conditions:

• Supply voltage: 1.14–3.465 V
• Operating temperature: -40 to +125 °C (Junction)
• SERDES data rate: Up to 5.0 Gbps

Absolute Maximum Ratings:

• Max supply voltage (VCC): 1.32 V
• Max supply voltage (VCCAUX): 3.6 V
• Max supply voltage (VCCIO): 3.9 V
• Max junction temperature: +150 °C
• Max storage temperature: +150 °C

Key Specs:

• Core Supply Voltage (VCC): 1.2 V (nominal)
• Auxiliary Supply Voltage (VCCAUX): 2.5 V or 3.3 V (nominal)
• I/O Supply Voltage (VCCIO): 1.2 V to 3.3 V (nominal)
• SERDES Data Rate: Up to 5.0 Gbps (ECP5-5G)
• Max I/O Buffer Speed (LVCMOS33): 200 MHz
• Max I/O Buffer Speed (LVDS25): 1.25 Gbps
• sysMEM Embedded Block RAM: Up to 40 Kbits per block
• Static VCC Current (LFE5-45F, Tj=25°C): 10 mA (typical)

Features:

• Low power, small form factor, low cost FPGAs
• High-performance SERDES: Up to 5 Gbps per channel
• Flexible I/O: Dedicated DDR memory support, on-chip termination, hot socketing
• High-performance DSP blocks: Dedicated multiply, accumulate, and sum blocks
• Enhanced sysCLOCK PLLs: Flexible clocking
• sysMEM Embedded Block RAM
• Enhanced configuration options: TransFR™ reconfigurability, single event upset (SEU) support
• On-chip oscillator
• IEEE 1149.1-compliant Boundary Scan Testability

• Higher Logic Density for Increased System Integration

• 12K to 84K LUTs

• 197 to 365 user programmable I/O

• Embedded SERDES

• 270 Mb/s, up to 3.2 Gb/s, SERDES interface (ECP5)

• 270 Mb/s, up to 5.0 Gb/s, SERDES interface (ECP5-5G)

• Supports eDP in RDR (1.62 Gb/s) and HDR

• (2.7 Gb/s)

• Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI

• sysDSP™

• Fully cascadable slice architecture

• 12 to 160 slices for high performance multiply and accumulate

• Powerful 54-bit ALU operations

• Time Division Multiplexing MAC Sharing

• Rounding and truncation

• Each slice supports

• Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers

• Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations

• Flexible Memory Resources

• Up to 3.744 Mb sysMEM™ Embedded Block

• RAM (EBR)

• 194K to 669K bits distributed RAM

• sysCLOCK Analog PLLs and DLLs

• Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12

• Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated read/write levelling functionality

• Dedicated gearing logic

• Source synchronous standards support

• ADC/DAC, 7:1 LVDS, XGMII

• High Speed ADC/DAC devices

• Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate

• Programmable sysI/O™ Buffer Supports Wide Range of Interfaces

• On-chip termination

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 18/15 I, II

• HSUL12

• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

• subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces

Over Recommended Operating Conditions

Table 3.7. DC Electrical Characteristics

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled.
2. TA 25 o C, f = 1.0 MHz.
3. Applicable to general purpose I/O in top and bottom banks.
4. When used as VREF, maximum leakage= 25 μA.

1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.

Table 3.2. Recommended Operating Conditions

1. For correct operation, all supplies except V REF must be held in their valid operation range. This is true independent of feature usage.
2. All supplies with same voltage, except SERDES Power Supplies, should be connected together.
3. See recommended voltages by I/O standard in Table 3.4.
4. VCCAUX ramp rate must not exceed 30 mV/μs during power-up when transitioning between 0 V and 3 V.
5. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206) for information on board considerations for SERDES power supplies.
6. VCCHRX is used for Rx termination. It can be biased to Vcm if external AC coupling is used. This voltage needs to meet all the HDin input voltage level requirements specified in the Rx section of this Data Sheet.