LAN9252TI/PT

Part: LAN9252 Microchip

Type: 2/3-Port EtherCAT Slave Controller with Integrated Ethernet PHYs

Key Specs:

• 2/3-port EtherCAT slave controller
• 3 Fieldbus Memory Management Units (FMMUs)
• 4 SyncManagers
• 1.8V to 3.3V variable voltage I/O
• Integrated 1.2V regulator
• Integrated high-performance 100Mbps Ethernet transceivers
• 4K bytes of DPRAM
• 8/16-Bit Host Bus Interface
• 25MHz crystal support

Features:

• Integrated Ethernet PHYs with HP Auto-MDIX
• Wake on LAN (WoL) support
• Low power mode
• Cable diagnostic support
• Compliant with IEEE 802.3/802.3u (Fast Ethernet)
• 100BASE-FX support via external fiber transceiver
• Loop-back modes
• Automatic polarity detection and correction
• Distributed clock support
• Indexed register or multiplexed bus host interface
• SPI / Quad SPI support
• Digital I/O Mode
• 3rd port for flexible network configurations
• Comprehensive power management features (3 power-down levels, Wake on link status change, Magic packet wakeup, wake on broadcast, wake on perfect DA, Wakeup indicator event signal)
• Integrated power-on reset circuit
• Latch-up performance exceeds 150mA per EIA/JESD78, Class II
• JEDEC Class 3A ESD performance
• Single 3.3V power supply
• Multifunction GPIOs

Applications:

• Motor Motion Control
• Process/Factory Automation
• Communication Modules, Interface Cards
• Sensors
• Hydraulic & Pneumatic Valve Systems
• Operator Interfaces

Package:

• 64-pin QFN
• 64-pin TQFP-EP

Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address.

• Motor Motion Control
• Process/Factory Automation
• Communication Modules, Interface Cards
• Sensors
• Hydraulic & Pneumatic Valve Systems
• Operator Interfaces

Note: When a "#" is used at the end of the signal name, it indicates that the signal is active low. For example, RST# indicates that the reset signal is active low.

The buffer type for each signal is indicated in the "Buffer Type" column of the pin description tables in Section 3.3, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".

Table 3-1 details the 64-QFN package pin assignments in table format. As shown, select pin functions may change based on the device's mode of operation. For modes where a specific pin has no function, the table cell will be marked with "-".

• Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO) (Note 1) 0 V to +3.6 V

• Ethernet Magnetics Supply Voltage -0.5 V to +3.6 V

• Positive voltage on input signal pins, with respect to ground (Note 2) VDDIO + 2.0 V

• Negative voltage on input signal pins, with respect to ground (Note 3) -0.5 V

• Positive voltage on OSCI, with respect to ground.+3.6 V

• Storage Temperature-55°C to +150°C

• Junction Temperature+150°C

• Lead Temperature Range Refer to JEDEC Spec. J-STD-020

• HBM ESD Performance JEDEC Class 3A

• Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit.

• Note 2: This rating does not apply to the following pins: OSCI, RBIAS

• Note 3: This rating does not apply to the following pins: RBIAS

*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 18.2, "Operating Conditions\\", Section 18.5, "DC Specifications", or any other applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant.