LAN9252/ML

Part: LAN9252 — Microchip Type: 2/3-Port EtherCAT Slave Controller with Integrated Ethernet PHYs Description: A 2/3-port EtherCAT slave controller with dual integrated 100Mbps Ethernet PHYs, supporting 3 FMMUs, 4 SyncManagers, 4K bytes of DPRAM, and an 8/16-bit host bus interface.

Operating Conditions:

• Supply voltage: 3.3V (single supply)
• Operating temperature: Commercial, Industrial, and Extended Industrial ranges
• Host I/O voltage: 1.8V to 3.3V variable

Absolute Maximum Ratings:

Key Specs:

• Ethernet speed: 100Mbps (100BASE-TX)
• EtherCAT FMMUs: 3
• EtherCAT SyncManagers: 4
• DPRAM size: 4K bytes
• Host bus interface: 8/16-bit (Indexed register or multiplexed bus)
• SPI/Quad SPI clock rate: Up to 80 MHz
• Integrated regulator output: 1.2V
• Crystal frequency: 25MHz

Features:

• Integrated high-performance 100Mbps Ethernet transceivers
• Compliant with IEEE 802.3/802.3u (Fast Ethernet)
• HP Auto-MDIX
• Distributed clock support
• SPI / Quad SPI support
• Digital I/O Mode for 16 digital signals
• Comprehensive power management features (3 power-down levels, Wake on LAN)
• Integrated power-on reset circuit
• Multifunction GPIOs
• 1.8V to 3.3V variable voltage I/O

Applications:

• Motor Motion Control
• Process/Factory Automation
• Communication Modules, Interface Cards
• Sensors
• Hydraulic & Pneumatic Valve Systems
• Operator Interfaces

Package:

• 64-pin QFN
• 64-pin TQFPEP

Offset:

0008h-0009h

Size:

16 bits

Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address.

• Motor Motion Control
• Process/Factory Automation
• Communication Modules, Interface Cards
• Sensors
• Hydraulic & Pneumatic Valve Systems
• Operator Interfaces

Note: When a ' # ' is used at the end of the signal name, it indicates that the signal is active low. For example, RST# indicates that the reset signal is active low.

The buffer type for each signal is indicated in the 'Buffer Type' column of the pin description tables in Section 3.3, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".

Table 3-1 details the 64-QFN package pin assignments in table format. As shown, select pin functions may change based on the device's mode of operation. For modes where a specific pin has no function, the table cell will be marked with '-'.

TABLE 3-1: 64-QFN PACKAGE PIN ASSIGNMENTS

TABLE 3-1: 64-QFN PACKAGE PIN ASSIGNMENTS (CONTINUED)

Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit.

Note 2: This rating does not apply to the following pins: OSCI, RBIAS

Note 3: This rating does not apply to the following pins: RBIAS

Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 18.2, "Operating Conditions*", Section 18.5, "DC Specifications", or any other applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant.

TABLE 18-1: 64-PIN QFN PACKAGE THERMAL PARAMETERS

TABLE 18-2: 64-PIN TQFP-EP PACKAGE THERMAL PARAMETERS

Note: Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESD51.

TABLE 18-3: MAXIMUM POWER DISSIPATION

• Mode Maximum Power (mW)
• Internal Regulator Disabled, 2.5 V Ethernet Magnetics 568
• Internal Regulator Disabled, 3.3 V Ethernet Magnetics 640
• Internal Regulator Enabled, 2.5 V Ethernet Magnetics 749
• Internal Regulator Enabled, 3.3 V Ethernet Magnetics 821