ISO154X
Low-Power Bidirectional I<sup>2</sup>C Isolators
Manufacturer
Texas Instruments
Category
Digital Isolators
Overview
Part: ISO1540, ISO1541 from Texas Instruments
Type: Low-Power Bidirectional I²C Isolator
Key Specs:
- Operation Speed: Up to 1 MHz
- Supply Voltage Range: 3 V to 5.5 V
- Operating Temperature Range: -40°C to 125°C
- Transient Immunity: ±50 kV/μs (Typical)
- Isolation Voltage (Peak): 4000 Vpk
- Isolation Voltage (RMS): 2500 Vrms
- Side 1 Sink Current: 3.5 mA
- Side 2 Sink Current: 35 mA
- HBM ESD Protection (Bus Pins): 8 kV
- HBM ESD Protection (All Pins): 4 kV
Features:
- Isolated Bidirectional, I²C Compatible, Communications
- Supports up to 1 MHz Operation
- 3-V to 5.5-V Supply Range
- Open Drain Outputs with 3.5-mA Side 1 and 35-mA Side 2 Sink Current Capability
- -40°C to 125°C Operating Temperature
- ±50 kV/μs Transient Immunity (Typical)
- HBM ESD Protection of 4 kV on All Pins: 8 kV on Bus Pins
Applications:
- Isolated I²C Bus
- SMBus and PMBus Interfaces
- Open-drain Networks
- Motor Control Systems
- Battery Management
- I²C Level Shifting
Package:
- D-8: 8 pins
Features
- Isolated Bidirectional, I2C Compatible, Communications
- Supports up to 1 MHz Operation
- 3-V to 5.5-V Supply Range
- Open Drain Outputs with 3.5-mA Side 1 and 35-mA Side 2 Sink Current Capability
- -40°C to 125°C Operating Temperature
- ±50 kV/μs Transient Immunity (Typical)
- HBM ESD Protection of 4 kV on All Pins: 8 kV on Bus Pins
APPLICATIONS
- Isolated I2C Bus
- SMBus and PMBus Interfaces
- Open-drain Networks
- Motor Control Systems
- Battery Management
- I2C Level Shifting
Applications
- Isolated I2C Bus
- SMBus and PMBus Interfaces
- Open-drain Networks
- Motor Control Systems
- Battery Management
- I2C Level Shifting
Pin Configuration
| ISO1540 and ISO1541 | 1/0 | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | PIN | ISO1540 | ISO1541 | ISO1540 |
| VCC1 | 1 | - | - | Supply Voltage, Side 1 |
| SDA1 | 2 | 1/0 | 1/0 | Serial Data, Side 1 Input/Output |
| SCL1 | 3 | 1/0 | 1 | Serial Clock Input/Output, Side 1 |
| GND1 | 4 | - | - | Ground, Side 1 |
| GND2 | 5 | - | - | Ground, Side 2 |
| SCL2 | 6 | 1/0 | 0 | Serial Clock Input/Output, Side 2 |
| SDA2 | 7 | 1/0 | 1/0 | Serial Data Input/Output, Side 2 |
| VCC2 | 8 | - | - | Supply Voltage, Side 2 |
Electrical Characteristics
Over recommended operating conditions, unless otherwise noted
| PARAMETER | TEST | CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|---|
| SUPPLY CI | JRRENT (3V ≤ VCC1, VCC | 2 < 3.6V) | 1 | - | ||||
| 0011 21 00 | MREIT (37 2 7001, 700) | ISO1540 | 2.4 | 3.6 | ||||
| I CC1 | Supply Current, Side 1 | ISO1541 | VSDA1 , VSCL1 = GND1 ; | 2.1 | 3.3 | |||
| ISO1540 and | VSDA2 , | |||||||
| I CC2 | Supply Current, Side 2 | ISO1540 and | VSCL2 = GND2 | See Figure 1; | 1.7 | 2.7 | ||
| 0 10 1011 | ISO1540 | V SDA1 , | R1,R2 = Open, C1,C2 = Open | 2.5 | 3.8 | mA | ||
| I CC1 | Supply Current, Side 1 | ISO1541 | VSCL1 = VCC1; | 17.2 | 2.3 | 3.6 | ||
| I CC2 | Supply Current, Side 2 | ISO1540 and ISO1541 | VSDA2 , VSCL2 = VCC2 | 1.9 | 3.1 | |||
| SUPPLY CL | JRRENT (4.5 V ≤ VCC1, VC | CC2 ≤ 5.5 V) | ||||||
| • | ISO1540 | V | 3.1 | 4.7 | ||||
| I CC1 | Supply Current, Side 1 | ISO1541 | VSDA1 , VSCL1 = GND1 ; | 2.8 | 4.4 | |||
| I CC2 | Supply Current, Side 2 | ISO1540 and ISO1541 | VSDA2 , VSCL2 = GND2 | See Figure 1; | 2.3 | 3.7 | ||
| ISO1540 | R1,R2 = Open, C1,C2 = Open | 3.1 | 4.7 | mA | ||||
| I CC1 | Supply Current, Side 1 | ISO1541 | VSDA1 , VSCL1 = VCC1 ; | 0 1 ,0 2 = Open | 2.9 | 4.5 | ||
| I CC2 | Supply Current, Side 2 | ISO1540 and ISO1541 | VSDA2 , VSCL2 = VCC2 | 2.5 | 4 | |||
| PARAM | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
| SIDE 1 (Onl | ||||||||
| V ILT1 | Voltage Input Threshold Side 1 (SDA1, SCL1) | "Low", | 500 | 550 | 660 | |||
| V IHT1 | Voltage Input Threshold Side 1 (SDA1, SCL1) | "High", | 540 | 610 | 700 | |||
| V HYST1 | Voltage Input Hysteresis Side 1 V IHT1 - V ILT1 | 5, | 40 | 60 | mV | |||
| V OL1 (1) | Low-Level Output Voltag Side 1 (SDA1,SCL1) | ge, | 0.5. 4.4 | 650 | 800 | |||
| ΔV OIT1 (1)(2) | Low-Level Output Voltaç Threshold Difference, Side 1 (SDA1, SCL1) | ge to High-Level I | nput Voltage | 0.5 mA ≤ ( ISDA1 and ISCL1 ) ≤ 3.5 mA | 50 | |||
| SIDE 2 (Onl | y) | • | • | |||||
| V ILT2 | Voltage Input Threshold Side 2 (SDA2, SCL2) | "Low", | 0.3 x VCC2 | 0.4 x VCC2 | ||||
| V IHT2 | Voltage Input Threshold Side 2 (SDA2, SCL2) | "High", | 0.4 x VCC2 | 0.5 x VCC2 | ., | |||
| V HYST2 | Voltage Input Hysteresis Side 2 V IHT2 - V ILT2 | 5, | 0.05 x VCC2 | mV | ||||
| V OL2 | Low-Level Output Voltag Side 2 (SDA2, SCL2) | ge, | 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 35 mA | 400 | ||||
| BOTH SIDE | ||||||||
| 1 1 | Input Leakage Currents (SDA1, SCL1, SDA2, SC | CL2) | VSDA1 , VSCL1 = VCC1 ; VSDA2 , VSCL2 = VCC2 | 0.01 | 10 | μΑ | ||
| C I | Input Capacitance to Loc (SDA1, SCL1, SDA2, SC | cal Ground CL2) | V1 = 0.4 × sin(2E6π t) + 2.5 V | 7 | pF | |||
| CMTI | Common-Mode Transier | See Figure 3 | 25 | 50 | kV/μs | |||
| V CCUV (3) | V CC Undervoltage Locko (Side 1 and Side 2) | out Threshold | 2.1 | 2.5 | 2.8 | V |
Submit Documentation Feedback
(1) This parameter does not apply to the ISO1541 SCL1 line as it is uni-directional. (2) ΔVOIT1 = VOL1 - VIHT1. This represents the minimum difference between a Low-Level Output Voltage and a High-Level Input Voltage Threshold to prevent a permanent latch condition that would otherwise exist with bi-directional communication.
Any VCC voltages, on either side, less than the minimum will ensure device lockout. Both VCC voltages above the maximum will prevent device lockout.
Absolute Maximum Ratings
| VALUES | UNIT | |||||
|---|---|---|---|---|---|---|
| MIN | MAX | |||||
| VCC1, VCC2 | –0.5 | 6 | V | |||
| Supply voltage | SDA1, SCL1 | –0.5 | VCC1 + 0.5 | V | ||
| SDA2, SCL2 | –0.5 | VCC2 + 0.5 | V | |||
| Output current | SDA1, SCL1 | ±20 | mA | |||
| SDA2, SCL2 | ±100 | mA | ||||
| Bus Pins | ±8 | kV | ||||
| Human Body Model | ESDA, JEDEC JS-001-2012 All Pins | ±4 | ||||
| Electrostatic Discharge | Field-Induced-Charged Device Model | JEDEC JESD22-C101E All Pins | ±1.5 | kV | ||
| Machine Model JEDEC JESD22-A115-A | ±200 | V | ||||
| TJ(MAX) | Maximum junction temperature | 150 | °C | |||
| TSTG | Storage temperature range | –65 | 150 | °C |
(1) Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability.
Recommended Operating Conditions
| MIN | NOM MAX | UNIT | ||
|---|---|---|---|---|
| VCC1, VCC2 | Supply Voltage | 3 | 5.5 | |
| VSDA1, VSCL1 | Input/Output Signal Voltages, Side 1 | 0 | VCC1 | |
| VSDA2, VSCL2 | Input/Output Signal Voltages, Side 2 | 0 | VCC2 | |
| VIL1 | Low-Level Input Voltage, Side 1 | 0 | 0.5 | V |
| VIH1 | High-Level Input Voltage, Side 1 | 0.7 x VCC1 | VCC1 | |
| VIL2 | Low-Level Input Voltage, Side 2 | 0 | 0.3 x VCC2 | |
| VIH2 | High-Level Input Voltage, Side 2 | 0.7 x VCC2 | VCC2 | |
| IOL1 | Output Current, Side 1 | 0.5 | 3.5 | |
| IOL2 | Output Current, Side 2 | 0.5 | 35 | mA |
| Cb1 | Maximum Capacitive Load, Side 1 | 40 | ||
| Cb2 | Maximum Capacitive Load, Side 2 | 400 | pF | |
| fMAX | Maximum Operating Frequency (1) | 1 | MHz | |
| TA | Ambient Temperature | –40 | 125 | °C |
| TJ | Junction Temperature | –40 | 136 | °C |
| TSD | Thermal Shutdown | 139 | 171 | °C |
(1) This represents the maximum frequency with the maximum bus load (Cb) and the maximum current sink (IO). If the system has less bus capacitance, then higher frequencies can be achieved.
Product Folder Links: ISO1540 ISO1541
(2) All voltage values here within are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
ELECTRICAL CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted
| PARAMETER | TEST | CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|---|
| SUPPLY CI | JRRENT (3V ≤ VCC1, VCC | 2 < 3.6V) | 1 | - | ||||
| 0011 21 00 | MREIT (37 2 7001, 700) | ISO1540 | 2.4 | 3.6 | ||||
| I CC1 | Supply Current, Side 1 | ISO1541 | VSDA1 , VSCL1 = GND1 ; | 2.1 | 3.3 | |||
| ISO1540 and | VSDA2 , | |||||||
| I CC2 | Supply Current, Side 2 | ISO1540 and | VSCL2 = GND2 | See Figure 1; | 1.7 | 2.7 | ||
| 0 10 1011 | ISO1540 | V SDA1 , | R1,R2 = Open, C1,C2 = Open | 2.5 | 3.8 | mA | ||
| I CC1 | Supply Current, Side 1 | ISO1541 | VSCL1 = VCC1; | 17.2 | 2.3 | 3.6 | ||
| I CC2 | Supply Current, Side 2 | ISO1540 and ISO1541 | VSDA2 , VSCL2 = VCC2 | 1.9 | 3.1 | |||
| SUPPLY CL | JRRENT (4.5 V ≤ VCC1, VC | CC2 ≤ 5.5 V) | ||||||
| • | ISO1540 | V | 3.1 | 4.7 | ||||
| I CC1 | Supply Current, Side 1 | ISO1541 | VSDA1 , VSCL1 = GND1 ; | 2.8 | 4.4 | |||
| I CC2 | Supply Current, Side 2 | ISO1540 and ISO1541 | VSDA2 , VSCL2 = GND2 | See Figure 1; | 2.3 | 3.7 | ||
| ISO1540 | R1,R2 = Open, C1,C2 = Open | 3.1 | 4.7 | mA | ||||
| I CC1 | Supply Current, Side 1 | ISO1541 | VSDA1 , VSCL1 = VCC1 ; | 0 1 ,0 2 = Open | 2.9 | 4.5 | ||
| I CC2 | Supply Current, Side 2 | ISO1540 and ISO1541 | VSDA2 , VSCL2 = VCC2 | 2.5 | 4 | |||
| PARAM | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
| SIDE 1 (Onl | ||||||||
| V ILT1 | Voltage Input Threshold Side 1 (SDA1, SCL1) | "Low", | 500 | 550 | 660 | |||
| V IHT1 | Voltage Input Threshold Side 1 (SDA1, SCL1) | "High", | 540 | 610 | 700 | |||
| V HYST1 | Voltage Input Hysteresis Side 1 V IHT1 - V ILT1 | 5, | 40 | 60 | mV | |||
| V OL1 (1) | Low-Level Output Voltag Side 1 (SDA1,SCL1) | ge, | 0.5. 4.4 | 650 | 800 | |||
| ΔV OIT1 (1)(2) | Low-Level Output Voltaç Threshold Difference, Side 1 (SDA1, SCL1) | ge to High-Level I | nput Voltage | 0.5 mA ≤ ( ISDA1 and ISCL1 ) ≤ 3.5 mA | 50 | |||
| SIDE 2 (Onl | y) | • | • | |||||
| V ILT2 | Voltage Input Threshold Side 2 (SDA2, SCL2) | "Low", | 0.3 x VCC2 | 0.4 x VCC2 | ||||
| V IHT2 | Voltage Input Threshold Side 2 (SDA2, SCL2) | "High", | 0.4 x VCC2 | 0.5 x VCC2 | ., | |||
| V HYST2 | Voltage Input Hysteresis Side 2 V IHT2 - V ILT2 | 5, | 0.05 x VCC2 | mV | ||||
| V OL2 | Low-Level Output Voltag Side 2 (SDA2, SCL2) | ge, | 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 35 mA | 400 | ||||
| BOTH SIDE | ||||||||
| 1 1 | Input Leakage Currents (SDA1, SCL1, SDA2, SC | CL2) | VSDA1 , VSCL1 = VCC1 ; VSDA2 , VSCL2 = VCC2 | 0.01 | 10 | μΑ | ||
| C I | Input Capacitance to Loc (SDA1, SCL1, SDA2, SC | cal Ground CL2) | V1 = 0.4 × sin(2E6π t) + 2.5 V | 7 | pF | |||
| CMTI | Common-Mode Transier | See Figure 3 | 25 | 50 | kV/μs | |||
| V CCUV (3) | V CC Undervoltage Locko (Side 1 and Side 2) | out Threshold | 2.1 | 2.5 | 2.8 | V |
Submit Documentation Feedback
(1) This parameter does not apply to the ISO1541 SCL1 line as it is uni-directional. (2) ΔVOIT1 = VOL1 - VIHT1. This represents the minimum difference between a Low-Level Output Voltage and a High-Level Input Voltage Threshold to prevent a permanent latch condition that would otherwise exist with bi-directional communication.
Any VCC voltages, on either side, less than the minimum will ensure device lockout. Both VCC voltages above the maximum will prevent device lockout.
Thermal Information
| THERMAL METRIC(1) | ISO1540 ISO1541 | UNITS | |
|---|---|---|---|
| D (8 PINS) | |||
| θJA | Junction-to-ambient thermal resistance | 114.6 | |
| θJCtop | Junction-to-case (top) thermal resistance | 69.6 | |
| θJB | Junction-to-board thermal resistance | 55.3 | |
| ψJT | Junction-to-top characterization parameter | 27.2 | °C/W |
| ψJB | Junction-to-board characterization parameter | 54.7 | |
| θJCbot | Junction-to-case (bottom) thermal resistance | n/a |
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