HT32F52352

Part: HT32F52342/HT32F52352 — Holtek

Type: 32-bit Arm Cortex-M0+ Microcontroller

Description: 32-bit Arm Cortex-M0+ MCU at up to 48 MHz with up to 128 KB Flash and 16 KB SRAM, 1 Msps ADC, USB 2.0 FS, and a single 2.0–3.6 V supply.

Operating Conditions:

• Supply voltage: 2.0–3.6 V (single VDD supply)
• Operating temperature: -40 to +85 °C (ambient)
• Max CPU clock: 48 MHz
• Integrated 1.5 V LDO for core; VBAT supply for RTC and backup registers

Absolute Maximum Ratings:

• Max supply voltage (VDD): VSS + 3.6 V
• Max analog supply voltage (VDDA): VSSA + 3.6 V
• Max battery supply voltage (VBAT): VSS + 3.6 V
• Max input voltage on I/O: VDD + 0.3 V
• Max junction temperature: 125 °C
• Storage temperature: -60 to +150 °C
• Total power dissipation: 500 mW
• ESD (HBM): ±4000 V

Key Specs:

• Core: Arm Cortex-M0+, up to 48 MHz, single-cycle multiplication
• Memory: up to 128 KB Flash, 16 KB SRAM
• ADC: 1 Msps
• Internal 8 MHz RC oscillator trimmed to ±2 % at 3.3 V and 25 °C
• External crystal oscillators: 4–16 MHz (HSE) and 32,768 Hz (LSE)
• Internal 32 kHz RC oscillator and system clock PLL
• Power modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
• Up to 16 EXTI lines

Features:

• Flash accelerator with ISP and IAP, and Flash protection
• Supply supervisor: POR/PDR, Brown-out Detector, programmable LVD
• Three power domains: VDD, VCORE, Backup
• Peripherals: ADC, comparator, USART, UART, SPI, I2C, I2S, MCTM, GPTM, SCTM, BFTM, SCI, CRC-16/32, RTC, WDT, PDMA, EBI, USB 2.0 FS
• SW-DP serial wire debug
• Independent clock divider and gating for peripherals

Applications:

• White goods application control
• Power monitors
• Alarm systems
• Consumer products
• Handheld equipment
• Data logging
• Motor control

Package:

• 33-pin QFN (4 mm × 4 mm, SAW type)
• 48-pin LQFP (7 mm × 7 mm)
• 64-pin LQFP (7 mm × 7 mm)

Table 18. ADC Characteristics

TA = 25 °C, unless otherwise specified.

Note: 1. Data based on characterization results only, not tested in production.

1. Due to the A/D Converter input channel and GPIO pin-shared function design limitation, the VDDA supply power of the A/D Converter has to be equal to the VDD supply power of the MCU in the application circuit.

2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input stage where C I is the storage capacitor, RI is the resistance of the sampling switch and RS is the output impedance of the signal source VS. Normally the sampling phase duration is approximately, 3.5/fADC. The capacitance, CI, must be charged within this time frame and it must be ensured that the voltage at its terminals becomes sufficiently close to V S for accuracy. To guarantee this, RS is not allowed to have an arbitrarily large value.

Figure 7. ADC Sampling Network Model

The worst case occurs when the extremities of the input range (0 V and VREF) are sampled consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following equation:

$$R_S < \frac{3.5}{f_{ADC} C_I \ln(2^{N+2})} - R_I$$

Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model.

If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, RS may be larger than the value indicated by the equation above.

The following table shows the absolute maximum ratings of the device. These are stress ratings only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

6

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