Part: HT32F52342/HT32F52352 — Holtek Type: 32-Bit Arm Cortex-M0+ Microcontroller Description: High performance, low power consumption 32-bit microcontrollers based around an Arm Cortex-M0+ processor core, operating at up to 48 MHz with up to 128 KB Flash, 16 KB SRAM, and a 1 Msps ADC.

Operating Conditions:

• Supply voltage: 2.0 V to 3.6 V
• Operating temperature: -40 to +85 °C (suffix-dependent — see Table 6 for grade-specific ranges)
• Max operating frequency: 48 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max junction/storage temperature: 150 °C

Key Specs:

• Core: 32-bit Arm Cortex-M0+
• Max CPU frequency: 48 MHz
• Flash memory: Up to 128 KB
• SRAM: 16 KB
• ADC resolution: 12-bit
• ADC sampling rate: 1 Msps
• Internal HSI accuracy: ±2 % (at 3.3V, 25 °C)
• I/O sink/source current: ±8 mA (per pin)

Features:

• Single-cycle multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC)
• 24-bit SysTick timer
• Multiple boot modes
• Flash accelerator with In System Programming (ISP) and In Application Programming (IAP)
• Supply supervisor: POR/PDR, BOD, LVD
• Integrated 1.5 V LDO regulator
• V BAT battery power supply for RTC and backup registers
• Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
• Up to 16 EXTI lines with configurable trigger source and type
• All GPIO pins can be selected as EXTI trigger source

Applications:

• White goods application control
• Power monitors
• Alarm systems
• Consumer products
• Handheld equipment
• Data logging applications
• Motor control

Package:

• 33-pin QFN (4mm × 4mm)
• 48-pin LQFP (7mm × 7mm)
• 64-pin LQFP (7mm × 7mm)

HT32F52352 QFN-33 Pinout

Notes

• Pin numbering source: The source table does not have a consistent Pin Number column. Pin numbers were extracted from the leftmost column where present, but several GPIO pins (PA6, PA7, PA10, PA11, PB5, PB6, PC0-C5, PC8-C15, PD0-D2) appear in the table without explicit pin numbers. The numbering above represents the best interpretation of the table structure, but verification against a pin diagram image is strongly recommended.
• VDD/VSS pins: Multiple power and ground pins are distributed throughout the package (VDD_1, VDD_2, VDD_3, VDD_4; VSS_1, VSS_2, VSS_3, VSS_4).
• Dual-function pins: Many pins serve as both GPIO and crystal/boot/debug pins (e.g., X32KIN/PB10, XTALIN/PB13, PA8/PA9_BOOT, SWCLK/PA12, SWDIO/PA13).
• Incomplete table: The source table is malformed in places (e.g., row 27 appears truncated). Pin PB5 and PB6 are referenced but lack clear pin number assignments in the source.

Table 18. ADC Characteristics

TA = 25 °C, unless otherwise specified.

Note: 1. Data based on characterization results only, not tested in production.

1. Due to the A/D Converter input channel and GPIO pin-shared function design limitation, the VDDA supply power of the A/D Converter has to be equal to the VDD supply power of the MCU in the application circuit.

1. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input stage where C I is the storage capacitor, RI is the resistance of the sampling switch and RS is the output impedance of the signal source VS. Normally the sampling phase duration is approximately, 3.5/fADC. The capacitance, CI, must be charged within this time frame and it must be ensured that the voltage at its terminals becomes sufficiently close to V S for accuracy. To guarantee this, RS is not allowed to have an arbitrarily large value.

Figure 7. ADC Sampling Network Model

The worst case occurs when the extremities of the input range (0 V and VREF) are sampled consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following equation:

Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model.

If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, RS may be larger than the value indicated by the equation above.

The following table shows the absolute maximum ratings of the device. These are stress ratings only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

6

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