Part: GD32F303xx — GigaDevice Semiconductor Inc.

Type: Arm Cortex-M4 32-bit MCU

Description: 32-bit Arm Cortex-M4 MCU operating at up to 120 MHz, with up to 3 MB Flash memory and 96 KB SRAM.

Operating Conditions:

• Supply voltage: 2.6 to 3.6 V
• Operating temperature: -40 to +105 °C
• Max core frequency: 120 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max junction/storage temperature: 125 °C

Key Specs:

• Core frequency: Up to 120 MHz (fHCLK)
• Flash memory: Up to 3072 KB
• SRAM: Up to 96 KB
• ADC resolution: 12-bit
• ADC conversion rate: Up to 2.6 MSPS (fADC=40MHz)
• DAC resolution: 12-bit
• Run mode current: 40 mA (Typ. at 120 MHz, VDD=3.3V, Tj=25°C, all peripherals enabled)
• I/O voltage: 2.6 to 3.6 V

Features:

• Arm Cortex-M4 core
• Up to 120 MHz operation
• Up to 3 MB Flash, 96 KB SRAM
• Multiple communication interfaces (I2C, SPI, USART, CAN, USB, SDIO)
• 12-bit ADC and DAC
• Timers and PWM generation
• Power saving modes

Package:

• LQFP144
• LQFP100
• LQFP64
• LQFP48

GD32F303CCT6 – LQFP48 Pinout

Pin Number	Pin Name	Type	Description
1	VBAT	P	Battery Power Supply
2	PC13-TAMPER-RTC	I/O	Port C Pin 13 / Tamper / RTC
3	PC14-OSC32IN	I/O	Port C Pin 14 / 32 kHz Oscillator Input
4	PC15-OSC32OUT	I/O	Port C Pin 15 / 32 kHz Oscillator Output
5	PD0-OSCIN	I/O	Port D Pin 0 / Main Oscillator Input
6	PD1-OSCOUT	I/O	Port D Pin 1 / Main Oscillator Output
7	NRST	I	Reset Pin
8	VSSA	P	Ground (Analog)
9	VDDA	P	Analog Power Supply
10	PA0-WKUP	I/O	Port A Pin 0 / Wakeup Pin
11	PA1	I/O	Port A Pin 1
12	PA2	I/O	Port A Pin 2
13	PA3	I/O	Port A Pin 3
14	PA4	I/O	Port A Pin 4
15	PA5	I/O	Port A Pin 5
16	PA6	I/O	Port A Pin 6
17	PA7	I/O	Port A Pin 7
18	PB0	I/O	Port B Pin 0
19	PB1	I/O	Port B Pin 1
20	PB2	I/O	Port B Pin 2
21	PB10	I/O	Port B Pin 10
22	PB11	I/O	Port B Pin 11
23	VSS_1	P	Ground
24	VDD_1	P	Digital Power Supply
25	PB12	I/O	Port B Pin 12
26	PB13	I/O	Port B Pin 13
27	PB14	I/O	Port B Pin 14
28	PB15	I/O	Port B Pin 15
29	PA8	I/O	Port A Pin 8
30	PA9	I/O	Port A Pin 9
31	PA10	I/O	Port A Pin 10
32	PA11	I/O	Port A Pin 11
33	PA12	I/O	Port A Pin 12
34	PA13	I/O	Port A Pin 13
35	VSS_2	P	Ground
36	VDD_2	P	Digital Power Supply
37	PA14	I/O	Port A Pin 14
38	PA15	I/O	Port A Pin 15
39	PB3	I/O	Port B Pin 3
40	PB4	I/O	Port B Pin 4
41	PB5	I/O	Port B Pin 5
42	PB6	I/O	Port B Pin 6
43	PB7	I/O	Port B Pin 7
44	BOOT0	I	Boot Configuration Pin
45	PB8	I/O	Port B Pin 8
46	PB9	I/O	Port B Pin 9
47	VSS_3	P	Ground
48	VDD_3	P	Digital Power Supply

Notes

• GD32F303CCT6 is the LQFP48 package variant (48 pins).
• Pin numbers extracted from the GD32F303Cx LQFP48 pinout diagram (Figure 2-5).
• VBAT (pin 1) is the battery backup supply for RTC and tamper detection.
• VDDA/VSSA (pins 9/8) are dedicated analog power and ground.
• Multiple VDD/VSS pairs (pins 23–24, 35–36, 47–48) provide distributed power and ground connections.
• PC13–PC15 and PD0–PD1 have special oscillator and RTC functions.
• PA0 includes wakeup capability (PA0-WKUP).
• BOOT0 (pin 44) controls boot mode selection.

Table 4-26. ADC characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V DDA (1)	Operating voltage	-	2.6	3.3	3.6	V
V IN (1)	ADC input voltage range	-	0	-	V REF+	V
V REF+ (2)	Positive Reference Voltage	-	2.6	-	V DDA	V
V REF- (2)	Negative Reference Voltage	-	-	V SSA	-	V
f ADC (1)	ADC clock	-	0.1	-	40	MHz
f S (1)	Sampling rate	12-bit	0.007	-	2.86	MSP
f S (1)	Sampling rate	10-bit	0.008	-	3.33	MSP
f S (1)	Sampling rate	8-bit	0.01	-	4	S
f S (1)	Sampling rate	6-bit	0.012	-	5	S
V AIN (1)	Analog input voltage	16 external; 2 internal	0	-	V DDA	V
R AIN (2)	External input impedance	See Equation 1	-	-	32.9	kΩ
R ADC (2)	Input sampling switch resistance	-	-	-	0.55	kΩ
C ADC (2)	Input sampling capacitance	No pin/pad capacitance included	-	-	5.5	pF

Table 4-26. ADC characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
t CAL (2)	Calibration time	f ADC = 40 MHz	-	3.275	-	μs
t s (2)	Sampling time	f ADC = 40 MHz	0.0375	-	5.99	μs
t CONV (2)	Total conversion time(including sampling time)	12-bit	-	14	-	1/ f ADC
t CONV (2)	Total conversion time(including sampling time)	10-bit	-	12	-	1/ f ADC
t CONV (2)	Total conversion time(including sampling time)	8-bit	-	10	-	1/ f ADC
t CONV (2)	Total conversion time(including sampling time)	6-bit	-	8	-	1/ f ADC
t SU (2)	Startup time	-	-	-	1	μ s

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 4-27. ADC RAIN max for fADC = 40 MHz

• T s (cycles) t s (μs) (1) R AIN max (kΩ)
• 1.5 0.0375 0.15
• 7.5 0.1875 2.96
• 13.5 0.3375 5.77
• 28.5 0.7125 12.8
• 41.5 1.0375 18.9
• 55.5 1.3875 25.4
• 71.5 1.7875 32.9
• 239.5 5.9875 N/A

Table 4-28. ADC dynamic accuracy at fADC = 14 MHz (1)

Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
ENOB	Effective number of bits	f ADC = 14 MHz	-	10.8	-	bits
SNDR	Signal-to-noise and distortion ratio	V DDA = V REF+ = 3.3 V	-	66.7	-
SNR	Signal-to-noise ratio	Input Frequency = 20	-	67.4	-	dB
THD	Total harmonic distortion	kHz Temperature = 25 °C	-	-76.3	-

Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
ENOB	Effective number of bits	f ADC = 40 MHz	-	10	-	bits
SNDR	Signal-to-noise and distortion ratio	V DDA = V REF+ = 3.3 V	-	62	-
SNR	Signal-to-noise ratio	Input Frequency = 20 kHz	-	62.2	-	dB
THD	Total harmonic distortion	Temperature = 25 °C	-	-68.6	-

Table 4-30. ADC static accuracy at fADC = 14 MHz (1)

Symbol	Parameter	Test conditions	Typ	Max	Unit
Offset	Offset error	f ADC = 14 MHz V DDA = V REF+ = 3.3 V	±1	-	LSB
DNL	Differential linearity error	f ADC = 14 MHz V DDA = V REF+ = 3.3 V	±0.9	-	LSB
INL	Integral linearity error	f ADC = 14 MHz V DDA = V REF+ = 3.3 V	±1	-	LSB

The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Table 4-1. Absolute maximum ratings (1) (4)

Symbol	Parameter	Min	Max	Unit
V DD	External voltagerange (2)	V SS - 0.3	V SS + 3.6	V
V DDA	External analog supply voltage	V SSA - 0.3	V SSA + 3.6	V
V BAT	External battery supply voltage	V SS - 0.3	V SS + 3.6	V
V IN	Input voltageon 5V tolerant pin (3)	V SS - 0.3	V DD + 3.6	V
V IN	Input voltageon other I/O	V SS - 0.3	3.6	V
\	ΔV DDX \		Variations between differentV DD power pins	-
\	V SSX -V SS \		Variations between differentground pins	-
I IO	Maximum current for GPIO pins	-	±25	mA
T A	Operating temperaturerange for grade6 device	-40	+85	° C
T A	Operating temperaturerange for grade7 device	-40	+105	° C
P D	Power dissipationatT A = 85° C ofLQFP144 (5)	-	820	mW
P D	Power dissipationatT A = 85° C ofLQFP100 (5)	-	848	mW
P D	Power dissipationatT A = 85° C ofLQFP64 (5)	-	647	mW
P D	Power dissipationatT A = 85° C ofLQFP48 (5)	-	621	mW
P D	Power dissipationatT A = 105° C of LQFP100 (5)	-	424	mW
P D	Power dissipationatT A = 105° C of LQFP48 (5)	-	311	mW
T STG	Storage temperature range	-65	+150	° C
T J	Maximum junction temperature	-	125	° C

Thermal resistance is used to characterize the thermal performance of the package device, which is represented by the Greek letter 'θ'. For semiconductor devices, thermal resistance represents the steady-state temperature rise of the chip junction due to the heat dissipated on the chip surface.

θJA: Thermal resistance, junction-to-ambient.

θJB: Thermal resistance, junction-to-board.

θJC: Thermal resistance, junction-to-case.

ᴪJB: Thermal characterization parameter, junction-to-board.

ᴪJT: Thermal characterization parameter, junction-to-top center.

Where, TJ = Junction temperature.

TA = Ambient temperature

TB = Board temperature

TC = Case temperature which is monitoring on package surface

PD = Total power dissipation

θJA represents the resistance of the heat flows from the heating junction to ambient air. It is an indicator of package heat dissipation capability. Lower θJA can be considerate as better overall thermal performance. θJA is generally used to estimate junction temperature.

θJB is used to measure the heat flow resistance between the chip surface and the PCB board.

θJC represents the thermal resistance between the chip surface and the package top case. θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat dissipation methods outside the device package).

Table 5-5. Package thermal characteristics (1)

Symbol	Condition	Package	Value	Unit
θ JA	Natural convection,2S2P PCB	LQFP144	48.76	° C/W
θ JA	Natural convection,2S2P PCB	LQFP100	47.19	° C/W
θ JA	Natural convection,2S2P PCB	LQFP64	61.8	° C/W
θ JA	Natural convection,2S2P PCB	LQFP48	64.4	° C/W
θ JB	Cold plate,2S2P PCB	LQFP144	35	° C/W
θ JB	Cold plate,2S2P PCB	LQFP100	27.43	° C/W

Table 5-5. Package thermal characteristics (1)

Symbol	Condition	Package	Value	Unit
		LQFP64 LQFP48	42.83 42.32
θ JC		LQFP144	12.03	° C/W
θ JC		LQFP100	8.57	° C/W
θ JC		LQFP64	21.98	° C/W
θ JC		LQFP48	22.47	° C/W
ᴪ JB	convection,2S2P PCB	LQFP144	35.32	° C/W
ᴪ JB	convection,2S2P PCB	LQFP100	31.42	° C/W
ᴪ JB	convection,2S2P PCB	LQFP64	43.05	° C/W
ᴪ JB	convection,2S2P PCB	LQFP48	42.42	° C/W
ᴪ JT	convection,2S2P PCB	LQFP144	1.86	° C/W
ᴪ JT	convection,2S2P PCB	LQFP100	1	° C/W
ᴪ JT	convection,2S2P PCB	LQFP64	1.58	° C/W
ᴪ JT	convection,2S2P PCB	LQFP48	1.74	° C/W

Figure 5-1. LQFP144 package outline

Table 5-1. LQFP144 package dimensions

Symbol	Min	Typ	Max
A	-	-	1.60
A1	0.05	-	0.15
A2	1.35	1.40	1.45
A3	0.59	0.64	0.69
b	0.18	-	0.26
b1	0.17	0.20	0.23
c	0.13	-	0.17
c1	0.12	0.13	0.14
D	21.80	22.00	22.20
D1	19.90	20.00	20.10
E	21.80	22.00	22.20
E1	19.90	20.00	20.10
e	-	0.50	-
L	0.45	-	0.75
L1	-	1.00	-
θ	0°	-	7°

(Original dimensions are in millimeters)

Table 5-1. LQFP144 package dimensions

Figure 5-2. LQFP144 recommended footprint

(Original dimensions are in millimeters)