GD32E103T8

Part: GD32E103xx — GigaDevice Semiconductor Inc.

Type: ARM Cortex-M4 32-bit MCU

Description: A 32-bit general-purpose microcontroller based on the ARM Cortex-M4 RISC core, offering enhanced processing capacity, reduced power consumption, and a rich peripheral set.

Operating Conditions:

• Supply voltage: 2.6–3.6 V
• Operating temperature: -40 to +105 °C
• Max CPU frequency: 108 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max junction/storage temperature: -65 to +150 °C

Key Specs:

• CPU Core: ARM Cortex-M4 with FPU
• Max CPU Frequency: 108 MHz
• Flash Memory: Up to 512 KB
• SRAM: Up to 96 KB
• ADC Resolution: 12-bit
• DAC Resolution: 12-bit
• Run Mode Current (VDD, 108MHz, 25°C): 28.5 mA (Typ)
• Standby Mode Current (VDD, 25°C): 2.0 μA (Typ)

Features:

• ARM Cortex-M4 RISC core with FPU
• Up to 512 KB Flash memory
• Up to 96 KB SRAM
• Up to 3x 12-bit ADCs
• 2x 12-bit DACs
• USBFS interface
• CAN interface
• Multiple timers, I2C, SPI, USART, I2S interfaces

Package:

• LQFP100
• LQFP64
• LQFP48
• QFN36

Figure 2-2. GD32E103Vx LQFP100 pinouts

Figure 2-3. GD32E103Rx LQFP64 pinouts

Figure 2-4. GD32E103Cx LQFP48 pinouts

Figure 2-5. GD32E103Tx QFN36 pinouts

Table 4-26. ADC characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V DDA (1)	Operating voltage	-	2.4	3.3	3.6	V
V IN (1)	ADC input voltage range	-	0	-	V REF+	V
f ADC (1)	ADC clock	-	0.1	-	42	MHz
f S (1)	Sampling rate	12-bit	0.007	-	3	MSPS
f S (1)	Sampling rate	10-bit	0.008	-	3.5	MSPS
f S (1)	Sampling rate	8-bit	0.01	-	4.2	MSPS
f S (1)	Sampling rate	6-bit	0.011	-	5.25	MSPS
V AIN (1)	Analog input voltage	16 external; 2 internal	0	-	V DDA	V
V REF+ (2)	Positive Reference Voltage	-	1.8	-	V DDA	V
V REF- (2)	Negative Reference Voltage	-	-	V SSA	-	V
R AIN (2)	External input impedance	See Equation 1	-	-	24	kΩ
R ADC (2)	Input sampling switch resistance	-	-	-	0.2	kΩ
C ADC (2)	Input sampling capacitance	No pin/pad capacitance included	-	-	5.5	pF
t CAL (2)	Calibration time	f ADC = 42 MHz	-	3.12	-	μs
t s (2)	Sampling time	f ADC = 42 MHz	0.036	-	5.7	μs
t CONV (2)	Total conversion time(including sampling time)	12-bit	-	14	-	1/ f ADC
t CONV (2)	Total conversion time(including sampling time)	10-bit	-	12	-	1/ f ADC
t CONV (2)	Total conversion time(including sampling time)	8-bit	-	10	-	1/ f ADC
t CONV (2)	Total conversion time(including sampling time)	6-bit	-	8	-	1/ f ADC
t SU (2)	Startup time	-	-	-	1	μs

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 4-27. ADC RAIN max for fADC = 42 MHz

• T s (cycles) t s (us) R AINmax (kΩ)
• 1.5 0.04 0.47
• 7.5 0.18 3.15
• 13.5 0.32 5.82
• 28.5 0.68 12.55
• 41.5 0.99 18.35
• 55.5 1.32 24.55
• 71.5 1.7 NA

Table 4-27. ADC RAIN max for fADC = 42 MHz

T s (cycles)	t s (us)	R AINmax (kΩ)
239.5	5.7	NA

Table 4-28. ADC dynamic accuracy at fADC = 14 MHz (1)

Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
ENOB	Effective number of bits	f ADC = 14 MHz	-	10.3	-	bits
SNDR	Signal-to-noise and distortion ratio	V DDA = V REF+ = 3.3 V	-	63.8	-
SNR	Signal-to-noise ratio	Input Frequency = 20	-	64.5	-	dB
THD	Total harmonic distortion	kHz Temperature = 25 °C	-	-67.5	-

Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
ENOB	Effective number of bits	f ADC = 42 MHz	-	10.3	-	bits
SNDR	Signal-to-noise and distortion ratio	V DDA = V REF+ = 3.3 V	-	63.8	-
SNR	Signal-to-noise ratio	Input Frequency = 20 kHz	-	64.5	-	dB
THD	Total harmonic distortion	Temperature = 25 °C	-	-67.5	-

Symbol	Parameter	Test conditions	Typ	Max	Unit
Offset	Offset error	f ADC = 42 MHz V DDA = V REF+ = 3.3 V	±1	-	LSB
DNL	Differential linearity error	f ADC = 42 MHz V DDA = V REF+ = 3.3 V	±1	-	LSB
INL	Integral linearity error	f ADC = 42 MHz V DDA = V REF+ = 3.3 V	±3	-	LSB

The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Table 4-1. Absolute maximum ratings (1)(4)

Symbol	Parameter	Min	Max	Unit
V DD	External voltage range (2)	V SS - 0.3	V SS + 3.6	V
V DDA	External analog supply voltage	V SSA - 0.3	V SSA + 3.6	V
V BAT	External battery supply voltage	V SS - 0.3	V SS + 3.6	V
V IN	Input voltage on 5V tolerant pin (3)	V SS - 0.3	V DD + 3.6	V
V IN	Input voltage on other I/O	V SS - 0.3	3.6	V
\	ΔV DDX \		Variations between different V DD power pins	-
\	V SSX -V SS \		Variations between different ground pins	-
I IO	Maximum current for GPIO pins	-	±25	mA
T A	Operating temperature range	-40	+85	° C
P D	Power dissipation at T A = 85° C of LQFP100	-	813	mW
P D	Power dissipation at T A = 85° C of LQFP64	-	733	mW
P D	Power dissipation at T A = 85° C of LQFP48	-	574	mW
P D	Power dissipation at T A = 85° C of QFN36	-	1086	mW
T STG	Storage temperature range	-55	+150	° C
T J	Maximum junction temperature	-	125	° C

Thermal resistance is used to characterize the thermal performance of the package device, which is represented by the Greek letter ' Θ '. For semiconductor devices, thermal resistance represents the steady-state temperature rise of the chip junction due to the heat dissipated on the chip surface.

Θ JA: Thermal resistance, junction-to-ambient.

Θ JB: Thermal resistance, junction-to-board.

Θ JC: Thermal resistance, junction-to-case.

Ψ JB: Thermal characterization parameter, junction-to-board.

Ψ JT: Thermal characterization parameter, junction-to-top center.

Where, TJ = Junction temperature.

TA = Ambient temperature

TB = Board temperature

TC = Case temperature which is monitoring on package surface

PD = Total power dissipation

Θ JA represents the resistance of the heat flows from the heating junction to ambient air. It is

an indicator of package heat dissipation capability. Lower Θ JA can be considerate as better overall thermal performance. Θ JA is generally used to estimate junction temperature.

• Θ JB is used to measure the heat flow resistance between the chip surface and the PCB board.
• Θ JC represents the thermal resistance between the chip surface and the package top case.
• Θ JC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat dissipation methods outside the device package).

Table 5-5. Package thermal characteristics (1)

Symbol	Condition	Package	Value	Unit
Θ JA	T A = 85° C, Natural convection, 2S2P PCB	LQFP100	49.18	° C/W
Θ JA	T A = 85° C, Natural convection, 2S2P PCB	LQFP64	54.57	° C/W
Θ JA	T A = 85° C, Natural convection, 2S2P PCB	LQFP48	69.64	° C/W
Θ JA	T A = 85° C, Natural convection, 2S2P PCB	QFN36	36.82	° C/W
Θ JB	T A = 25° C, Cold plate, 2S2P PCB	LQFP100	22.7	° C/W
Θ JB	T A = 25° C, Cold plate, 2S2P PCB	LQFP64	35.08	° C/W
Θ JB	T A = 25° C, Cold plate, 2S2P PCB	LQFP48	43.16	° C/W
Θ JB	T A = 25° C, Cold plate, 2S2P PCB	QFN36	9.79	° C/W
Θ JC	T A = 25° C, Cold plate, 2S2P PCB	LQFP100	12.52	° C/W
Θ JC	T A = 25° C, Cold plate, 2S2P PCB	LQFP64	18.11	° C/W
Θ JC	T A = 25° C, Cold plate, 2S2P PCB	LQFP48	25.36	° C/W
Θ JC	T A = 25° C, Cold plate, 2S2P PCB	QFN36	13.31	° C/W
Ψ JB	T A = 85° C, Natural convection, 2S2P PCB	LQFP100	32.85	° C/W
Ψ JB	T A = 85° C, Natural convection, 2S2P PCB	LQFP64	35.41	° C/W
Ψ JB	T A = 85° C, Natural convection, 2S2P PCB	LQFP48	47.75	° C/W
Ψ JB	T A = 85° C, Natural convection, 2S2P PCB	QFN36	9.87	° C/W
Ψ JT	T A = 85° C, Natural convection, 2S2P PCB	LQFP100	0.53	° C/W
Ψ JT	T A = 85° C, Natural convection, 2S2P PCB	LQFP64	1.1	° C/W
Ψ JT	T A = 85° C, Natural convection, 2S2P PCB	LQFP48	2.45	° C/W
Ψ JT	T A = 85° C, Natural convection, 2S2P PCB	QFN36	0.43	° C/W

Figure 5-1. LQFP100 package outline

Table 5-1. LQFP100 package dimensions

Symbol	Min	Typ	Max
A	-	-	1.60
A1	0.05	-	0.15
A2	1.35	1.40	1.45
A3	0.59	0.64	0.69
D	15.80	16.0	16.20
D1	13.90	14.0	14.10
E	15.80	16.0	16.20
E1	13.90	14.0	14.10
θ	0°	3.5°	7°
c	0.13	-	0.17
c1	0.12	0.13	0.14
L	0.45	0.6	0.75
L1	-	1.0REF	-

Table 5-1. LQFP100 package dimensions

Symbol	Min	Typ	Max
b	0.18	0.20	0.26
b1	0.17	0.20	0.23
eB	15.05	-	15.35
e	-	0.50BSC	-

(Original dimensions are in millimeters)