ESP32-C6

Part: ESP32-C6 Series

Type: Ultra-low-power SoC with RISC-V single-core microprocessor

Key Specs:

• HP RISC-V Processor Clock Speed: up to 160 MHz
• LP RISC-V Processor Clock Speed: up to 20 MHz
• Wi-Fi: 2.4 GHz Wi-Fi 6 (802.11ax)
• Bluetooth: Bluetooth 5.3 LE
• Deep-sleep Power Consumption: 7 µA
• GPIOs: 30 (QFN40), 22 (QFN32)
• ROM: 320 KB
• HP SRAM: 512 KB
• LP SRAM: 16 KB

Features:

• 2.4 GHz Wi-Fi 6 (802.11ax) with 1T1R, OFDMA, MU-MIMO, TWT
• Bluetooth 5.3 LE with Bluetooth mesh, high power mode (20 dBm)
• IEEE 802.15.4 (Zigbee 3.0, Thread 1.3)
• Dual RISC-V processors (HP and LP)
• Optional 4 MB flash in the chip's package
• Rich set of peripherals including UART, SPI, I2C, I2S, ADC, PWM, CAN, USB
• Advanced power management with Active, Modem-sleep, Light-sleep, Deep-sleep modes
• Comprehensive security features: Secure boot, Flash encryption, OTP, Cryptographic hardware acceleration
• RF module with integrated antenna switches, RF balun, power amplifier, low-noise receive amplifier

Applications:

• Smart Home
• Industrial Automation
• Health Care
• Consumer Electronics
• Smart Agriculture
• POS Machines
• Service Robot
• Audio Devices
• Generic Low-power IoT Sensor Hubs
• Generic Low-power IoT Data Loggers

Package:

• QFN40: 5×5 mm
• QFN32: 5×5 mm

Wi-Fi

• • 1T1R in 2.4 GHz band
• • Operating frequency: 2412 ~ 2484 MHz
• • IEEE 802.11ax-compliant
  • 20 MHz-only non-AP mode
  • MCS0 ~MCS9
  • Uplink and downlink OFDMA, especially suitable for simultaneous connections in high-density environments
  • Downlink MU-MIMO (multi-user, multiple input, multiple output) to increase network capacity
  • Beamformee that improves signal quality
  • Channel quality indication (CQI)
  • DCM (dual carrier modulation) to improve link robustness
  • Spatial reuse to maximize parallel transmissions
  • Target wake time (TWT) that optimizes power saving mechanisms
• • Fully compatible with IEEE 802.11b/g/n protocol
  • 20 MHz and 40 MHz bandwidth
  • Data rate up to 150 Mbps
  • Wi-Fi Multimedia (WMM)
  • TX/RX A-MPDU, TX/RX A-MSDU
  • Immediate Block ACK
  • Fragmentation and defragmentation
  • Transmit opportunity (TXOP)
  • Automatic Beacon monitoring (hardware TSF)
  • Four virtual Wi-Fi interfaces
  • Simultaneous support for Infrastructure BSS in Station mode, SoftAP mode, Station
    • • SoftAP mode, and promiscuous mode

Note that when ESP32-C6 scans in Station mode, the SoftAP channel will change along with the Station channel

• Antenna diversity
• 802.11mc FTM

Bluetooth®

• • Bluetooth LE: Bluetooth 5.3 certified
• • Bluetooth mesh
• • High power mode (20 dBm)
• • Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps
• • Advertising extensions
• • Multiple advertisement sets
• • Channel selection algorithm #2
• • LE power control
• • Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna

IEEE 802.15.4

• • Compliant with IEEE 802.15.4-2015 protocol
• • OQPSK PHY in 2.4 GHz band
• • Data rate: 250 Kbps
• • Thread 1.3
• • Zigbee 3.0

CPU and Memory

• • HP RISC-V processor:
  • Clock speed: up to 160 MHz
  • Four stage pipeline
  • CoreMark® score: 464.36 CoreMark;2.90 CoreMark/MHz (160 MHz)
• • LP RISC-V processor:
  • Clock speed: up to 20 MHz
  • Two stage pipeline

• L1 cache: 32 KB

• ROM: 320 KB

• HP SRAM: 512 KB

• LP SRAM: 16 KB

• • Supported SPI protocols: SPI, Dual SPI, Quad SPI, QPI interfaces that allow connection to flash and other SPI devices off the chip's package
• • Flash controller with cache is supported
• • Flash in-Circuit Programming (ICP) is supported

Advanced Peripheral Interfaces

• • 30 GPIOs (QFN40), or 22 GPIOs (QFN32)

  • 5 strapping GPIOs
  • 6 GPIOs needed for in-package flash

• • Analog interfaces:

  • 12-bit SAR ADC, up to 7 channels
  • Temperature sensor

• • Digital interfaces:

  • Two UARTs
  • Low-power (LP) UART
  • Two SPI ports for communication with flash
  • General purpose SPI port
  • I2C
  • Low-power (LP) I2C
  • I2S
  • Pulse count controller
  • USB Serial/JTAG controller
  • Two TWAI® controllers, compatible with ISO 11898-1 (CAN Specification 2.0)
  • SDIO 2.0 slave controller
  • LED PWM controller, up to 6 channels
  • Motor Control PWM (MCPWM)
  • Remote control peripheral (TX/RX)
  • Parallel IO interface (PARLIO)

• General DMA controller, with 3 transmit channels and 3 receive channels

• Event task matrix (ETM)

• • Timers:

  • 52-bit system timer
  • Two 54-bit general-purpose timers
  • Three digital watchdog timers
  • Analog watchdog timer

Power Management

• • Fine-resolution power control through a selection of clock frequency, duty cycle, Wi-Fi operating modes, and individual power control of internal components
• • Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep
• • Power consumption in Deep-sleep mode is 7 µA
• • Low-power (LP) memory remains powered on in Deep-sleep mode

Security

• • Secure boot permission control on accessing internal and external memory

• • Flash encryption memory encryption and decryption

• • 4096-bit OTP, up to 1792 bits for users

• • Trusted execution environment (TEE) controller and access permission management (APM)

• • Cryptographic hardware acceleration:

  • AES-128/256 (FIPS PUB 197)
  • ECC
  • HMAC
  • RSA
  • SHA (FIPS PUB 180-4)
  • Digital signature

• • External Memory Encryption and Decryption (XTS_AES)

• • Random Number Generator (RNG)

RF Module

• Antenna switches, RF balun, power amplifier, low-noise receive amplifier

• • Up to +21 dBm of power for an 802.11b transmission
• • Up to +19.5 dBm of power for an 802.11ax transmission
• • Up to -106 dBm of sensitivity for Bluetooth LE receiver (125 Kbps)

With low power consumption, ESP32-C6 is an ideal choice for IoT devices in the following areas:

• • Smart Home

• • Industrial Automation

• • Health Care

• • Consumer Electronics

• • Smart Agriculture

• • POS Machines

• • Service Robot

• • Audio Devices

• • Generic Low-power IoT Sensor Hubs

• • Generic Low-power IoT Data Loggers

Note:

Check the link or the QR code to make sure that you use the latest version of this document: https://www.espressif.com/documentation/esp32-c6\_datasheet\_en.pdf

The IO MUX allows multiple input/output signals to be connected to a single input/output pin. Each IO pin of ESP32-C6 can be connected to one of the three signals (IO MUX functions, i.e. F0-F2), as listed in Table 2-4 QFN40 IO MUX Pin Functions and Table 2-5 QFN32 IO MUX Pin Functions.

Among the three sets of signals:

• • Some are routed via the GPIO Matrix (GPIO0, GPIO1, etc.), which incorporates internal signal routing circuitry for mapping signals programmatically. It gives the pin access to almost any peripheral signals. However, the flexibility of programmatic mapping comes at a cost as it might affect the latency of routed signals. For details about connecting to peripheral signals via GPIO Matrix, see ESP32-C6 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.
• • Some are directly routed from certain peripherals (U0TXD, MTCK, etc.), including UART0/1, JTAG, SPI0/1, SPI2, and SDIO - see Table 2-3 Peripheral Signals Routed via IO MUX.

Table 2-3. Peripheral Signals Routed via IO MUX

Table 2-4. QFN40 IO MUX Pin Functions

| Pin | IO MUX / | IO MUX Function 1, 2, 3 | |-----|----------------|-------------------------|--------|--------|-------|---------|--------| | No. | GPIO
Name 2 | F0 | Type 3 | F1 | Type | F2 | Type | | 6 | GPIO0 | GPIO0 | I/O/T | GPIO0 | I/O/T | | 7 | GPIO1 | GPIO1 | I/O/T | GPIO1 | I/O/T | | 8 | GPIO2 | GPIO2 | I/O/T | GPIO2 | I/O/T | FSPIQ | I1/O/T | | 9 | GPIO3 | GPIO3 | I/O/T | GPIO3 | I/O/T | | 10 | GPIO4 | MTMS | I1 | GPIO4 | I/O/T | FSPIHD | I1/O/T | | 11 | GPIO5 | MTDI | I1 | GPIO5 | I/O/T | FSPIWP | I1/O/T | | 12 | GPIO6 | MTCK | I1 | GPIO6 | I/O/T | FSPICLK | I1/O/T | | 13 | GPIO7 | MTDO | O/T | GPIO7 | I/O/T | FSPID | I1/O/T | | 14 | GPIO8 | GPIO8 | I/O/T | GPIO8 | I/O/T | | 15 | GPIO9 | GPIO9 | I/O/T | GPIO9 | I/O/T | | 16 | GPIO10 | GPIO10 | I/O/T | GPIO10 | I/O/T | | 17 | GPIO11 | GPIO11 | I/O/T | GPIO11 | I/O/T | | 18 | GPIO12 | GPIO12 | I/O/T | GPIO12 | I/O/T | | 19 | GPIO13 | GPIO13 | I/O/T | GPIO13 | I/O/T | | 20 | GPIO24 | SPICS0 | O/T | GPIO24 | I/O/T | | 21 | GPIO25 | SPIQ | I1/O/T | GPIO25 | I/O/T | | 22 | GPIO26 | SPIWP | I1/O/T | GPIO26 | I/O/T | | 23 | GPIO27 | GPIO27 | I/O/T | GPIO27 | I/O/T | | 24 | GPIO28 | SPIHD | I1/O/T | GPIO28 | I/O/T | | 25 | GPIO29 | SPICLK | O/T | GPIO29 | I/O/T | | 26 | GPIO30 | SPID | I1/O/T | GPIO30 | I/O/T | | 27 | GPIO15 | GPIO15 | I/O/T | GPIO15 | I/O/T | | 29 | GPIO16 | U0TXD | O | GPIO16 | I/O/T | FSPICS0 | I1/O/T | | 30 | GPIO17 | U0RXD | I1 | GPIO17 | I/O/T | FSPICS1 | O/T | | 31 | GPIO18 | SDIO_CMD | I1/O/T | GPIO18 | I/O/T | FSPICS2 | O/T | | 32 | GPIO19 | SDIO_CLK | I1 | GPIO19 | I/O/T | FSPICS3 | O/T | | 33 | GPIO20 | SDIO_DATA0 | I1/O/T | GPIO20 | I/O/T | FSPICS4 | O/T | | 34 | GPIO21 | SDIO_DATA1 | I1/O/T | GPIO21 | I/O/T | FSPICS5 | O/T | | 35 | GPIO22 | SDIO_DATA2 | I1/O/T | GPIO22 | I/O/T | | 36 | GPIO23 | SDIO_DATA3 | I1/O/T | GPIO23 | I/O/T | Bold marks the default pin functions in the default boot mode. See Section 3.1 Chip Boot Mode Control.

• • I1 input; if the pin is assigned a function other than Fn, the input signal of Fn is always 1.
• • I0 input; if the pin is assigned a function other than Fn, the input signal of Fn is always 0.

Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and LP GPIOs.

Each IO MUX function (Fn, n = 0 ~ 2) is associated with a type. The description of type is as follows:

^• I – input. O – output. T – high impedance.

Table 2-5. QFN32 IO MUX Pin Functions

| Pin | IO MUX / | | | IO MUX Function 1, 2, 3 | |-----|----------------|------------|--------|-------------------------|-------|---------|--------| | No. | GPIO
Name 2 | F0 | Type 3 | F1 | Type | F2 | Type | | 6 | GPIO0 | GPIO0 | I/O/T | GPIO0 | I/O/T | | 7 | GPIO1 | GPIO1 | I/O/T | GPIO1 | I/O/T | | 8 | GPIO2 | GPIO2 | I/O/T | GPIO2 | I/O/T | FSPIQ | I1/O/T | | 9 | GPIO3 | GPIO3 | I/O/T | GPIO3 | I/O/T | | 10 | GPIO4 | MTMS | I1 | GPIO4 | I/O/T | FSPIHD | I1/O/T | | 11 | GPIO5 | MTDI | I1 | GPIO5 | I/O/T | FSPIWP | I1/O/T | | 12 | GPIO6 | MTCK | I1 | GPIO6 | I/O/T | FSPICLK | I1/O/T | | 13 | GPIO7 | MTDO | O/T | GPIO7 | I/O/T | FSPID | I1/O/T | | 14 | GPIO8 | GPIO8 | I/O/T | GPIO8 | I/O/T | | 15 | GPIO9 | GPIO9 | I/O/T | GPIO9 | I/O/T | | 16 | GPIO12 | GPIO12 | I/O/T | GPIO12 | I/O/T | | 17 | GPIO13 | GPIO13 | I/O/T | GPIO13 | I/O/T | | 18 | GPIO14 | GPIO14 | I/O/T | GPIO14 | I/O/T | | 19 | GPIO15 | GPIO15 | I/O/T | GPIO15 | I/O/T | | 21 | GPIO16 | U0TXD | O | GPIO16 | I/O/T | FSPICS0 | I1/O/T | | 22 | GPIO17 | U0RXD | I1 | GPIO17 | I/O/T | FSPICS1 | O/T | | 23 | GPIO18 | SDIO_CMD | I1/O/T | GPIO18 | I/O/T | FSPICS2 | O/T | | 24 | GPIO19 | SDIO_CLK | I1 | GPIO19 | I/O/T | FSPICS3 | O/T | | 25 | GPIO20 | SDIO_DATA0 | I1/O/T | GPIO20 | I/O/T | FSPICS4 | O/T | | 26 | GPIO21 | SDIO_DATA1 | I1/O/T | GPIO21 | I/O/T | FSPICS5 | O/T | | 27 | GPIO22 | SDIO_DATA2 | I1/O/T | GPIO22 | I/O/T | | 28 | GPIO23 | SDIO_DATA3 | I1/O/T | GPIO23 | I/O/T | ¹ Bold marks the default pin functions in the default boot mode. See Section 3.1 Chip Boot Mode Control.

• • I input. O output. T high impedance.
• • I1 input; if the pin is assigned a function other than Fn, the input signal of Fn is always 1.
• • I0 input; if the pin is assigned a function other than Fn, the input signal of Fn is always 0.

² Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and LP GPIOs.

³ Each IO MUX function (Fn, n = 0 ~ 2) is associated with a type. The description of type is as follows:

Table 5-4. DC Characteristics (3.3 V, 25 °C)

¹ VDD – voltage from a power pin of a respective power domain.

Stresses above those listed in Table 5-1 Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and normal operation of the device at these or any other conditions beyond those indicated in Section 5.2 Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Table 5-1. Absolute Maximum Ratings

¹ For more information on input power pins, see Section 2.5.1 Power Pins.

Table 5-2. Recommended Power Characteristics

¹ See in conjunction with Section 2.5 Power Supply.

² The product proved to be fully functional after all its IO pins were pulled high while being connected to ground for 24 consecutive hours at ambient temperature of 25 °C.

² If VDDPST2 is used to power VDD_SPI (see Section 2.5.2 Power Scheme), the voltage drop on RSP I should be accounted for. See also Section 5.3 VDD\_SPI Output Characteristics.

³ If writing to eFuses, the voltage on VDDPST2 should not exceed 3.3 V as the circuits responsible for burning eFuses are sensitive to higher voltages.