Part: EFR32BG24A010F1024IM48-B — Silicon Labs Type: Wireless System-on-Chip (SoC) Description: A 32-bit ARM Cortex-M33 core running at up to 78 MHz, with 1024 kB Flash and 128 kB RAM, featuring a high-performance 2.4 GHz radio with up to +10 dBm output power, an AI/ML hardware accelerator, and Secure Vault Mid security.

Operating Conditions:

• Supply voltage: 1.71 V to 3.8 V
• Operating temperature: -40 to +125 °C
• Max operating frequency: 78 MHz

Absolute Maximum Ratings:

• Max supply voltage: 3.8 V
• Max junction/storage temperature: 125 °C

Key Specs:

• CPU: ARM Cortex-M33 with DSP and FPU
• Max CPU frequency: 78 MHz
• Flash memory: Up to 1536 kB (1024 kB for this variant)
• RAM memory: Up to 256 kB (128 kB for this variant)
• RX current (1 Mbps GFSK): 4.4 mA
• TX current @ 0 dBm: 5 mA
• EM2 DeepSleep current (16 kB RAM retention): 1.3 μA
• ADC resolution: 12-bit @ 1 Msps or 16-bit @ 76.9 ksps
• Die temperature sensor accuracy: +/-1.5 °C

Features:

• High performance 2.4 GHz radio with up to +19.5 dBm output power
• AI/ML Hardware Accelerator (Matrix Vector Processor)
• Secure Vault (Mid or High grade)
• Bluetooth Low Energy (BLE 5.3) and Bluetooth Mesh support
• Hardware Cryptographic Acceleration
• True Random Number Generator (TRNG)
• ARM TrustZone
• Wide selection of MCU peripherals including IADC, VDAC, ACMP, Timers, USART, EUSART, I2C
• Up to 32 General Purpose I/O pins

Applications:

• Smart Home - Gateways and hubs, sensors, switches, door locks, smart plugs
• Lighting - LED bulbs, luminaires
• Portable Medical Devices - Blood glucose meters, pulse oximeters
• AI/ML - Predictive maintenance, glass break detection, wake-word detection

Package:

• QFN40 (5 mm × 5 mm × 0.85 mm)
• QFN48 (6 mm × 6 mm × 0.85 mm)

• 32-bit ARM® Cortex®-M33 core with 78 MHz maximum operating frequency
• Up to 1536 kB of flash and 256 kB of RAM
• High performance radio with up to +19.5 dBm output power
• Energy efficient design with low active and sleep currents
• Secure Vault™
• AI/ML Hardware Accelerator

• Smart Home - Gateways and hubs, sensors, switches, door locks, smart plugs
• Lighting - LED bulbs, luminaires
• Portable Medical Devices - Blood glucose meters, pulse oximeters
• AI/ML - Predictive maintenance, glass break detection, wake-word detection

EFR32BG24A010F1024IM48 — QFN48 Pinout

Pin Number	Pin Name	Type	Description
1	PC00	GPIO	GPIO
2	PC01	GPIO	GPIO
3	PC02	GPIO	GPIO
4	PC03	GPIO	GPIO
5	PC04	GPIO	GPIO
6	PC05	GPIO	GPIO
7	PC06	GPIO	GPIO
8	PC07	GPIO	GPIO
9	PC08	GPIO	GPIO
10	PC09	GPIO	GPIO
11	HFXTAL_I	Analog	High Frequency Crystal Input
12	HFXTAL_O	Analog	High Frequency Crystal Output
13	RESETn	Input	Reset Pin (internally pulled up to DVDD)
14	RFVDD	Power	Radio power supply
15	RFVSS	Ground	Radio Ground
16	RF2G4_IO	Analog	2.4 GHz RF input/output
17	PAVDD	Power	Power Amplifier (PA) power supply
18	PB05	GPIO	GPIO
19	PB04	GPIO	GPIO
20	PB03	GPIO	GPIO
21	PB02	GPIO	GPIO
22	PB01	GPIO	GPIO
23	PB00	GPIO	GPIO
24	VREFN	Analog	Dedicated ADC VREF Negative Input
25	VREFP	Analog	Dedicated ADC VREF Positive Input
26	PA00	GPIO	GPIO
27	PA01	GPIO	GPIO
28	PA02	GPIO	GPIO
29	PA03	GPIO	GPIO
30	PA04	GPIO	GPIO
31	PA05	GPIO	GPIO
32	PA06	GPIO	GPIO
33	PA07	GPIO	GPIO
34	PA08	GPIO	GPIO
35	PA09	GPIO	GPIO
36	DECOUPLE	Analog	Decouple output for on-chip voltage regulator (requires external capacitor)
37	VREGSW	Power	DCDC regulator switching node
38	VREGVDD	Power	DCDC regulator input supply
39	VREGVSS	Ground	DCDC ground
40	DVDD	Power	Digital power supply
41	AVDD	Power	Analog power supply
42	IOVDD	Power	I/O power supply
43	PD05	GPIO	GPIO
44	PD04	GPIO	GPIO
45	PD03	GPIO	GPIO
46	PD02	GPIO	GPIO
47	PD01	GPIO	GPIO
48	PD00	GPIO	GPIO

Notes

• Standard Device Pinout: This is the QFN48 Standard Device variant (not the ADC variant). The part number suffix "A010" indicates the standard configuration.
• Pin numbering verified from the attached QFN48 package diagram.
• GPIO pins support alternate functions; refer to section 6.4 (Alternate Function Table), 6.5 (Analog Peripheral Connectivity), and 6.6 (Digital Peripheral Connectivity) in the datasheet for detailed capabilities.
• Power pins (DVDD, AVDD, IOVDD, RFVDD, PAVDD, VREGVDD) must be properly decoupled per datasheet recommendations.
• RESETn is internally pulled up and active-low.

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on T A =25 °C and all supplies at 3.0 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.

Due to on-chip circuitry (e.g., diodes), some EFR32BG24 power supply pins have a dependent relationship with one or more other power supply pins. These internal relationships between the external voltages applied to the various EFR32BG24 supply pins are defined below. Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD and DVDD
• In systems using the DCDC converter, DVDD (the buck converter output) should not be driven externally and VREGVDD (the buck converter input) must be greater than DVDD (VREGVDD ≥ DVDD)
• In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD = DVDD)
• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered with power applied to these supplies.
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD

Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Storage temperature range	T STG		-50	-	+150	°C
Voltage on any supply pin 1	V DDMAX		-0.3	-	3.8	V
Junction temperature	T JMAX	-I grade	-	-	+125	°C
Voltage ramp rate on any supply pin	V DDRAMPMAX		-	-	1.0	V / μs
Voltage on HFXO pins	V HFXOPIN		-0.3	-	1.2	V
DC voltage on any GPIO pin	V DIGPIN		-0.3	-	V IOVDD + 0.3	V
DC voltage on RESETn pin 2	V RESETn		-0.3	-	3.8	V
DC voltage on RF pin RF2G4_IO	V MAX2G4		-0.3	-	1.2	V
Total current into VDD power lines	I VDDMAX	Source	-	-	200	mA
Total current into VSS ground lines	I VSSMAX	Sink	-	-	200	mA
Current per I/O pin	I IOMAX	Sink	-	-	50	mA
Current per I/O pin		Source	-	-	50	mA
Current for all I/O pins	I IOALLMAX	Sink	-	-	200	mA
Current for all I/O pins		Source	-	-	200	mA

1. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifications for more details.

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at DVDD.

Table 4.4. Thermal Characteristics

Package	Board	Parameter	Symbol	Test Condition	Value	Unit
40QFN (5x5mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Ambient	Θ JA	Still Air	29.2	°C/W
40QFN (5x5mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Board	Θ JB		15.2	°C/W
40QFN (5x5mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Top Center	Ѱ JT		0.3	°C/W
40QFN (5x5mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Board	Ѱ JB		11.2	°C/W
40QFN (5x5mm)	No Board	Thermal Resistance, Junction to Case	Θ JC	Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow.	24.6	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Ambient	Θ JA	Still Air	27.7	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Board	Θ JB		14.6	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Top Center	Ѱ JT		0.69	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Board	Ѱ JB		11.85	°C/W
48QFN (6x6mm)	No Board	Thermal Resistance, Junction to Case	Θ JC	Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow.	23	°C/W

1. Based on 4 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm, per JEDEC. PCB Center Land with 9 Via to top internal plane of PCB.

Figure 7.1. QFN40 Package Drawing

Table 7.1. QFN40 Package Dimensions

Dimension	Min	Typ	Max
A	0.80	0.85	0.90
A1	0.00	0.02	0.05
A3	0.20 REF	0.20 REF	0.20 REF
b	0.15	0.20	0.25
D	4.90	5.00	5.10
E	4.90	5.00	5.10
D2	3.55	3.70	3.85
E2	3.55	3.70	3.85
e	0.40 BSC	0.40 BSC	0.40 BSC
L	0.30	0.40	0.50
K	0.20	-	-
R	0.075	-	-
aaa	0.10	0.10	0.10
bbb	0.07	0.07	0.07
ccc	0.10	0.10	0.10
ddd	0.05	0.05	0.05
eee	0.08	0.08	0.08
fff	0.10	0.10	0.10

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

5. Package external pad (epad) may have pin one chamfer.

MPN	Package	Temperature Range	Packing
EFR32BG24B220F1024IM48-B	QFN48	-40 to +125 °C	null
EFR32BG24B210F1024IM48-B	QFN48	-40 to +125 °C	null
EFR32BG24B110F1536IM48-B	QFN48	-40 to +125 °C	null
EFR32BG24A020F1024IM48-B	QFN48	-40 to +125 °C	null
EFR32BG24A020F1024IM40-B	QFN40	-40 to +125 °C	null
EFR32BG24A010F1024IM48-B	QFN48	-40 to +125 °C	null
EFR32BG24A010F1024IM40-B	QFN40	-40 to +125 °C	null