EFM32PG23B310F512IM48-C

Part: EFM32PG23 Gecko Family

Type: Microcontroller

Key Specs:

• Core: 32-bit ARM Cortex-M33
• Maximum Operating Frequency: 80 MHz
• Flash Memory: Up to 512 kB
• RAM Data Memory: Up to 64 kB
• GPIO Pins: Up to 34
• Active Mode Current (EM0): 21 μA/MHz
• DeepSleep Current (EM2): 1.03 μA (16 kB RAM retention, RTC from LFRCO)
• Supply Voltage: 1.71 V to 3.8 V
• Operating Temperature: -40 °C to 125 °C

Features:

• DSP instruction and floating-point unit
• Low energy operation
• Secure Vault with Hardware Cryptographic Acceleration, TRNG, ARM TrustZone, Secure Boot, Secure Debug Unlock, DPA Countermeasures, Secure Key Management with PUF, Anti-Tamper, Secure Attestation
• Wide Operating Range
• Wide selection of MCU peripherals including IADC (12, 16, or 20-bit), ACMP, VDAC, LESENSE, DMA, PRS, Timers, RTC, LETimer, PCNT, Watchdog, EUSART, UART/SPI/SmartCard/IrDA/I2S, I2C, LCD Controller, Keypad scanner, Die temperature sensor

Applications:

• 32-bit ARM® Cortex®-M33 core with 80 MHz maximum operating frequency
• Up to 512 kB of flash and 64 kB of RAM
• Robust peripheral set and up to 34 GPIO
• Low energy operation • 21 uA/MHz (EM0)
  • 1.03 uA sleep (EM2)
• 16-channel ADC with options for 12, 16, or 20-bit resolution
• Best-in-class security with Secure Vault

4.1 Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on TA=25 °C and all supplies at 3.3 V, by production test and/or technology characterization.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.

Power Supply Pin Dependencies

Due to on-chip circuitry (e.g., diodes), some EFM32 power supply pins have a dependent relationship with one or more other power supply pins. These internal relationships between the external voltages applied to the various EFM32 supply pins are defined below. Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD and DVDD
  • In systems using the DCDC converter, DVDD (the buck converter output) should not be driven externally and VREGVDD (the buck converter input) must be greater than DVDD (VREGVDD ≥ DVDD)
  • In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD = DVDD)
• DVDD ≥ DECOUPLE
• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered with power applied to these supplies.

4.2 Absolute Maximum Ratings

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at https://www.silabs.com/about-us/corporate-responsibility/commitment-toquality.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Storage temperature range	TSTG		-50	—	+150	°C
Voltage on any supply pin	VDDMAX		-0.3	—	3.8	V
Junction temperature	TJMAX	-I grade	—	—	+125	°C
Voltage ramp rate on any supply pin	VDDRAMPMAX		—	—	1.0	V / μs
Voltage on HFXO pins	VHFXOPIN		-0.3	—	1.2	V
DC voltage on any GPIO pin1	VDIGPIN		-0.3	—	VIOVDD + 0.3	V
DC voltage on RESETn pin2	VRESETn		-0.3	—	3.8	V
Total current into VDD power lines	IVDDMAX	Source	—	—	200	mA
Total current into VSS ground lines	IVSSMAX	Sink	—	—	200	mA
Current per I/O pin	IIOMAX	Sink	—	—	50	mA
		Source	—	—	50	mA
Current for all I/O pins	IIOALLMAX	Sink	—	—	200	mA
		Source	—	—	200	mA

Table 4.1. Absolute Maximum Ratings

Note:

1. When operating as an LCD driver, the output voltage on a GPIO may safely exceed this specification. The pin output voltage may be up to 3.8 V in this case.

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at DVDD.

4.3 General Operating Conditions

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Operating ambient tempera ture range	TA	-I temperature grade 1	-40	—	+125	° C
DVDD supply voltage	VDVDD	EM0/1	1.71	3.3	3.8	V
		EM2/3/4²	1.71	3.3	3.8	V
AVDD supply voltage	VAVDD		1.71	3.3	3.8	V
IOVDD operating supply volt age	VIOVDD		1.71	3.3	3.8	V
VREGVDD operating supply	VVREGVDD	DCDC in regulation	2.2	3.3	3.8	V
voltage		DCDC in bypass 60 mA load	1.8	3.3	3.8	V
		DCDC not in use. DVDD external ly shorted to VREGVDD	1.71	3.3	3.8	V
DECOUPLE output capaci tor³	CDECOUPLE	1.0 μF ± 10% X8L capacitor used for performance characterization.	0.75	1.0	2.75	μF
HCLK and SYSCLK frequen cy	fHCLK	VSCALE2, MODE = WS1	—	—	80	MHz
		VSCALE2, MODE = WS0	—	—	40	MHz
		VSCALE1, MODE = WS0	—	—	40	MHz
PCLK frequency	fPCLK	VSCALE2 or VSCALE1	—	—	40	MHz
EM01 Group A clock fre	fEM01GRPACLK	VSCALE2	—	—	80	MHz
quency		VSCALE1	—	—	40	MHz
EM01 Group C clock fre	fEM01GRPCCLK	VSCALE2	—	—	80	MHz
quency		VSCALE1	—	—	40	MHz
External Clock Input	fCLKIN	VSCALE2 or VSCALE1	—	—	40	MHz
DPLL Reference Clock	fDPLLREFCLK	VSCALE2 or VSCALE1	—	—	40	MHz

Table 4.2. General Operating Conditions

Note:

1. The device may operate continuously at the maximum allowable ambient TA rating as long as the absolute maximum TJMAX is not exceeded. For an application with significant power dissipation, the allowable TA may be lower than the maximum TA rating. TA = TJMAX - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for TJMAX and THETAJA.

2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.

3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance value stays within the specified bounds across temperature and DC bias.

4.4 DC-DC Converter

Test conditions: LDCDC = 2.2 μH (Samsung CIG22H2R2MNE), CDCDC = 4.7 μF (TDK CGA5L3X8R1C475K160AB), VVREGVDD = 3.3 V, VOUT = 1.8 V, IPKVAL in EM0/1 modes is set to 150 mA, and in EM2/3 modes is set to 90 mA, unless otherwise indicated.

Table 4.3. DC-DC Converter

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Input voltage range at VREGVDD pin	VVREGVDD	DCDC in regulation, ILOAD = 60 mA, EM0/EM1 mode	2.2	—	3.8	V
		DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode	1.8	—	3.8	V
		Bypass Mode, ILOAD ≤ 60 mA	1.8	—	3.8	V
Regulated output voltage	VOUT		—	1.8	—	V
Regulation DC accuracy	ACCDC	VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode	-2.5	—	4.0	%
Regulation total accuracy	ACCTOT	All error sources (including DC er rors, overshoot, undershoot)	-5	—	7	%
Steady-state output ripple	VR	ILOAD = 20 mA in EM0/EM1 mode	—	12	—	mVpp
DC line regulation	VREG	ILOAD = 60 mA in EM0/EM1 mode, VVREGVDD ≥ 2.2 V	—	-2.6	—	mV/V
Efficiency	EFF	Load current between 100 μA and 60 mA in EM0/EM1 mode	—	90	—	%
		Load current between 10 μA and 5 mA in EM2/EM3 mode	—	89	—	%
DC load regulation	IREG	Load current between 100 μA and 60 mA in EM0/EM1 mode	—	-0.08	—	mV/mA
Output load current	ILOAD	EM0/EM1 mode, DCDC in regula tion	—	—	60	mA
		EM2/EM3 mode, DCDC in regula tion	—	—	5	mA
		Bypass mode, 1.8 V ≤ VVREGVDD ≤ 3.8 V	—	—	60	mA
Nominal output capacitor	CDCDC	4.7 μF ± 10% X7R capacitor used for performance characterization¹	—	4.7	10	μF
Nominal inductor	LDCDC	± 20% tolerance	—	2.2	—	μH
Nominal input capacitor	CIN		—	—	—	μF
Resistance in bypass mode	RBYP	Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V	—	0.45	0.8	Ω
		Powertrain PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V	—	0.6	0.9	Ω
Supply monitor threshold programming range	VCMP_RNG	Programmable in 0.1 V steps	2	—	2.3	V
Supply monitor threshold ac curacy	VCMP_ACC	Supply falling edge trip point	-5	—	5	%

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Supply monitor threshold hysteresis	VCMP_HYST	Positive hysteresis on the supply rising edge referred to the falling edge trip point	—	4	—	%
Supply monitor response time	tCMP_DELAY	Supply falling edge at -100 mV / μs	—	0.6	—	μs

1. TDK CGA5L3X8R1C475K160AB used for performance characterization. Actual capacitor values can be significantly de-rated from their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The minimum capacitance counting all error sources should be no less than 3.6 μF.

4.5 Thermal Characteristics

Package	Board	Parameter	Symbol	Test Condition	Value	Unit
40QFN (5x5mm)	JEDEC - High Thermal Cond.	Thermal Resistance, Junction to Ambient	ΘJA	Still Air	29.2	°C/W
	(2s2p)1	Thermal Resistance, Junction to Board	ΘJB		15.2	°C/W
		Thermal Resistance, Junction to Top Center	ѰJT		0.3	°C/W
		Thermal Resistance, Junction to Board	ѰJB		11.2	°C/W
	No Board	Thermal Resistance, Junction to Case	ΘJC	Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow.	24.6	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p)1	Thermal Resistance, Junction to Ambient	ΘJA	Still Air	27.7	°C/W
		Thermal Resistance, Junction to Board	ΘJB		14.6	°C/W
		Thermal Resistance, Junction to Top Center	ѰJT		0.69	°C/W
		Thermal Resistance, Junction to Board	ѰJB		11.85	°C/W
	No Board	Thermal Resistance, Junction to Case	ΘJC	Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow.	23.0	°C/W

Table 4.4. Thermal Characteristics

Note:

1. Based on 4 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm, per JEDEC. PCB Center Land with 9 Via to top internal plane of PCB.

4.6 Current Consumption

4.6.1 MCU current consumption using DC-DC at 3.3 V input

Unless otherwise indicated, typical conditions are: VREGVDD = 3.3 V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V from DC-DC. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.

	Table 4.5. MCU current consumption using DC-DC at 3.3 V input
Parameter	Symbol
-------------------------------------------------------------	---------
Current consumption in EM0 mode with all peripherals dis	IACTIVE
abled
Current consumption in EM1	IEM1
mode with all peripherals dis abled
Current consumption in EM2 mode, VSCALE0	IEM2_VS

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Current consumption in EM0 mode with all peripherals disabled	I_ACTIVE	80 MHz HFRCO, CPU running Prime from flash, VSCALE2	—	23	—	μA/MHz
		80 MHz HFRCO, CPU running while loop from flash, VSCALE2	—	21	—	μA/MHz
		80 MHz HFRCO, CPU running CoreMark loop from flash, VSCALE2	—	31	—	μA/MHz
		39 MHz crystal, CPU running Prime from flash	—	27	—	μA/MHz
		39 MHz crystal, CPU running while loop from flash	—	26	—	μA/MHz
		39 MHz crystal, CPU running CoreMark loop from flash	—	36	—	μA/MHz
		38 MHz HFRCO, CPU running while loop from flash	—	22	—	μA/MHz
		26 MHz HFRCO, CPU running while loop from flash	—	24	—	μA/MHz
		16 MHz HFRCO, CPU running while loop from flash	—	29	—	μA/MHz
		1 MHz HFRCO, CPU running while loop from flash	—	206	—	μA/MHz
Current consumption in EM1 mode with all peripherals disabled	IEM1	80 MHz HFRCO, VSCALE2	—	11	—	μA/MHz
		39 MHz crystal	—	18	—	μA/MHz
		38 MHz HFRCO	—	14	—	μA/MHz
		26 MHz HFRCO	—	16	—	μA/MHz
		16 MHz HFRCO	—	21	—	μA/MHz
		1 MHz HFRCO	—	197	—	μA/MHz
Current consumption in EM2 mode, VSCALE0	IEM2_VS	64 kB RAM retention, RTC running from LFXO	—	1.33	—	μA
		64 kB RAM retention, RTC running from LFRCO	—	1.33	—	μA
		16 kB RAM retention, RTC running from LFRCO	—	1.03	—	μA
		16 kB RAM retention, RTC running from LFXO	—	1.03	—	μA

Note:

1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.9.4 Power Domains for a list of the peripherals in each power domain. Note that if the PD0B, PD0C, or PD0D domains are enabled, PD0E will also automatically be enabled.

4.6.2 MCU current consumption at 3.3 V

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 3.3 V. DC-DC not used. Voltage scaling level = VSCALE1. T^A = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Current consumption in EM0 mode with all peripherals dis abled	IACTIVE	80 MHz HFRCO, CPU running Prime from flash, VSCALE2	—	37	—	μA/MHz
		80 MHz HFRCO, CPU running while loop from flash, VSCALE2	—	33	TBD	μA/MHz
		80 MHz HFRCO, CPU running CoreMark loop from flash, VSCALE2	—	49	—	μA/MHz
		39 MHz crystal, CPU running Prime from flash	—	44	—	μA/MHz
		39 MHz crystal, CPU running while loop from flash	—	42	—	μA/MHz
		39 MHz crystal, CPU running CoreMark loop from flash	—	58	—	μA/MHz
		38 MHz HFRCO, CPU running while loop from flash	—	35	56	μA/MHz
		26 MHz HFRCO, CPU running while loop from flash	—	38	—	μA/MHz
		16 MHz HFRCO, CPU running while loop from flash	—	46	—	μA/MHz
		1 MHz HFRCO, CPU running while loop from flash	—	329	1100	μA/MHz
Current consumption in EM1 mode with all peripherals dis abled	IEM1	80 MHz HFRCO, VSCALE2	—	18	TBD	μA/MHz
		39 MHz crystal	—	29	—	μA/MHz
		38 MHz HFRCO	—	22	42	μA/MHz
		26 MHz HFRCO	—	25	—	μA/MHz
		16 MHz HFRCO	—	33	—	μA/MHz
		1 MHz HFRCO	—	315	1086	μA/MHz

Table 4.6. MCU current consumption at 3.3 V

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Current consumption in EM0 mode with all peripherals disabled	IACTIVE	80 MHz HFRCO, CPU running Prime from flash, VSCALE2	—	37	—	µA/MHz
		80 MHz HFRCO, CPU running while loop from flash, VSCALE2	—	33	TBD	µA/MHz
		80 MHz HFRCO, CPU running CoreMark loop from flash, VSCALE2	—	49	—	µA/MHz
		39 MHz crystal, CPU running Prime from flash	—	44	—	µA/MHz
		39 MHz crystal, CPU running while loop from flash	—	42	—	µA/MHz
		39 MHz crystal, CPU running CoreMark loop from flash	—	58	—	µA/MHz
		38 MHz HFRCO, CPU running while loop from flash	—	35	56	µA/MHz
		26 MHz HFRCO, CPU running while loop from flash	—	38	—	µA/MHz
		16 MHz HFRCO, CPU running while loop from flash	—	46	—	µA/MHz
		1 MHz HFRCO, CPU running while loop from flash	—	329	1100	µA/MHz
Current consumption in EM1 mode with all peripherals disabled	IEM1	80 MHz HFRCO, VSCALE2	—	18	TBD	µA/MHz
		39 MHz crystal	—	29	—	µA/MHz
		38 MHz HFRCO	—	22	42	µA/MHz
		26 MHz HFRCO	—	25	—	µA/MHz
		16 MHz HFRCO	—	33	—	µA/MHz
		1 MHz HFRCO	—	315	1086	µA/MHz

Note:

1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.9.4 Power Domains for a list of the peripherals in each power domain. Note that if the PD0B, PD0C, or PD0D domains are enabled, PD0E will also automatically be enabled.

4.6.3 MCU current consumption at 1.8 V

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 1.8 V. DC-DC not used. Voltage scaling level = VSCALE1. T^A = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Current consumption in EM0 mode with all peripherals dis abled	IACTIVE	80 MHz HFRCO, CPU running Prime from flash, VSCALE2	—	37	—	μA/MHz
		80 MHz HFRCO, CPU running while loop from flash, VSCALE2	—	33	—	μA/MHz
		80 MHz HFRCO, CPU running CoreMark loop from flash, VSCALE2	—	49	—	μA/MHz
		39 MHz crystal, CPU running Prime from flash	—	44	—	μA/MHz
		39 MHz crystal, CPU running while loop from flash	—	42	—	μA/MHz
		39 MHz crystal, CPU running CoreMark loop from flash	—	58	—	μA/MHz
		38 MHz HFRCO, CPU running while loop from flash	—	35	—	μA/MHz
		26 MHz HFRCO, CPU running while loop from flash	—	38	—	μA/MHz
		16 MHz HFRCO, CPU running while loop from flash	—	46	—	μA/MHz
		1 MHz HFRCO, CPU running while loop from flash	—	323	—	μA/MHz
Current consumption in EM1 mode with all peripherals dis abled	IEM1	80 MHz HFRCO, VSCALE2	—	18	—	μA/MHz
		39 MHz crystal	—	29	—	μA/MHz
		38 MHz HFRCO	—	22	—	μA/MHz
		26 MHz HFRCO	—	25	—	μA/MHz
		16 MHz HFRCO	—	32	—	μA/MHz
		1 MHz HFRCO	—	309	—	μA/MHz
Current consumption in EM2 mode, VSCALE0	IEM2_VS	64 kB RAM retention, RTC run ning from LFXO	—	1.92	—	μA
		64 kB RAM retention, RTC run ning from LFRCO	—	1.92	—	μA
		16 kB RAM retention, RTC run ning from LFRCO	—	1.47	—	μA
		16 kB RAM retention, RTC run ning from LFXO	—	1.5	—	μA
Current consumption in EM3 mode, VSCALE0	IEM3_VS	64 kB RAM retention, RTC run ning from ULFRCO	—	1.6	—	μA
		16 kB RAM retention, RTC run ning from ULFRCO	—	1.15	—	μA

Table 4.7. MCU current consumption at 1.8 V

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Current consumption in EM0 mode with all peripherals disabled	IACTIVE	80 MHz HFRCO, CPU running Prime from flash, VSCALE2	—	37	—	µA/MHz
		80 MHz HFRCO, CPU running while loop from flash, VSCALE2	—	33	—	µA/MHz
		80 MHz HFRCO, CPU running CoreMark loop from flash, VSCALE2	—	49	—	µA/MHz
		39 MHz crystal, CPU running Prime from flash	—	44	—	µA/MHz
		39 MHz crystal, CPU running while loop from flash	—	42	—	µA/MHz
		39 MHz crystal, CPU running CoreMark loop from flash	—	58	—	µA/MHz
		38 MHz HFRCO, CPU running while loop from flash	—	35	—	µA/MHz
		26 MHz HFRCO, CPU running while loop from flash	—	38	—	µA/MHz
		16 MHz HFRCO, CPU running while loop from flash	—	46	—	µA/MHz
		1 MHz HFRCO, CPU running while loop from flash	—	323	—	µA/MHz
Current consumption in EM1 mode with all peripherals disabled	IEM1	80 MHz HFRCO, VSCALE2	—	18	—	µA/MHz
		39 MHz crystal	—	29	—	µA/MHz
		38 MHz HFRCO	—	22	—	µA/MHz
		26 MHz HFRCO	—	25	—	µA/MHz
		16 MHz HFRCO	—	32	—	µA/MHz
		1 MHz HFRCO	—	309	—	µA/MHz
Current consumption in EM2 mode, VSCALE0	IEM2_VS	64 kB RAM retention, RTC running from LFXO	—	1.92	—	µA
		64 kB RAM retention, RTC running from LFRCO	—	1.92	—	µA
		16 kB RAM retention, RTC running from LFRCO	—	1.47	—	µA
		16 kB RAM retention, RTC running from LFXO	—	1.5	—	µA
Current consumption in EM3 mode, VSCALE0	IEM3_VS	64 kB RAM retention, RTC running from ULRFCO	—	1.6	—	µA
		16 kB RAM retention, RTC running from ULRFCO	—	1.15	—	µA

Note:

1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.9.4 Power Domains for a list of the peripherals in each power domain. Note that if the PD0B, PD0C, or PD0D domains are enabled, PD0E will also automatically be enabled.

4.7 Wake Up, Entry, and Exit times

Unless otherwise specified, these times are measured using the HFRCO at 19 MHz, with the DPLL disabled.

		Table 4.8. Wake Up, Entry, and Exit times
--	--	-------------------------------------------

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
WakeupTime from EM1	tEM1_WU	Code execution from flash	—	3	—	HCLKs
		Code execution from RAM	—	1.43	—	μs
WakeupTime from EM2	tEM2_WU	Code execution from flash, No Voltage Scaling	—	13.7	—	μs
		Code execution from RAM, No Voltage Scaling	—	5.1	—	μs
		Voltage scaling up one level1	—	37.8	—	μs
		Voltage scaling up two levels2	—	51.0	—	μs
WakupTime from EM3	tEM3_WU	Code execution from flash, No Voltage Scaling	—	13.7	—	μs
		Code execution from RAM, No Voltage Scaling	—	5.1	—	μs
		Voltage scaling up one level1	—	37.8	—	μs
		Voltage scaling up two levels2	—	51.0	—	μs
WakeupTime from EM4	tEM4_WU	Code execution from flash	—	31.0	—	ms
Entry time to EM1	tEM1_ENT	Code execution from flash	—	1.29	—	μs
Entry time to EM2	tEM2_ENT	Code execution from flash	—	5.9	—	μs
Entry time to EM3	tEM3_ENT	Code execution from flash	—	5.7	—	μs
Entry time to EM4	tEM4_ENT	Code execution from flash	—	10.7	—	μs
Voltage scaling in time in EM03	tSCALE	Up from VSCALE1 to VSCALE2	—	32	—	μs
		Down from VSCALE2 to VSCALE1	—	172	—	μs

Note:

1. Voltage scaling one level is between VSCALE0 and VSCALE1 or between VSCALE1 and VSCALE2.

2. Voltage scaling two levels is between VSCALE0 and VSCALE2.

3. During voltage scaling in EM0, RAM is inaccessible and processor will be halted until complete.

4.8 Flash Characteristics

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Flash Supply voltage during write or erase	VFLASH		1.71	—	3.8	V
Flash data retention1	RETFLASH		10	—	—	years
Flash erase cycles before failure1	ECFLASH		10,000	—	—	cycles
Program Time	tPROG	one word (32-bits)	TBD	43.5	TBD	μs
		average per word over 128 words	TBD	10.9	TBD	μs
Page Erase Time2	tPERASE		TBD	12.9	TBD	ms
Mass Erase Time3 4	tMERASE	512 kB	TBD	50.4	TBD	ms
Program Current	IWRITE	TA = 25 °C	—	—	2.4	mA
Page Erase Current	IERASE	TA = 25 °C	—	—	1.9	mA
Mass Erase Current	IMERASE	TA = 25 °C	—	—	1.9	mA

Table 4.9. Flash Characteristics

Note:

1. Flash data retention information is published in the Quarterly Quality and Reliability Report.

2. Page Erase time is measured from setting the ERASEPAGE bit in the MSC_WRITECMD register until the BUSY bit in the MSC-STATUS register is cleared to 0. Internal set-up and hold times are included.

3. Mass Erase is issued by the CPU and erases all of User space.

4. Mass Erase time is measured from setting the ERASEMAIN0 bit in the MSC_WRITECMD register until the BUSY bit in the MSC-STATUS register is cleared to 0. Internal set-up and hold times are included.

4.9 Oscillators

4.9.1 High Frequency Crystal Oscillator

Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.3 V. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.

Table 4.10. High Frequency Crystal Oscillator

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Crystal Frequency	FHFXO		38.0	39.0	40.0	MHz
Supported range of crystal load capacitance1	CL_HFXO		—	10	—	pF
Supported crystal maximum equivalent series resistance (ESR)	ESRHFXO	39.0 MHz 2	—	—	60	Ω
Supply Current	IHFXO		—	498	—	μA
Startup Time3	TSTARTUP	39.0 MHz, CL = 10 pF	—	178	—	μs
On-chip tuning cap step size4	SSHFXO		—	0.04	—	pF

Note:

1. Total load capacitance as seen by the crystal.

2. The crystal should have a maximum ESR less than or equal to this maximum rating.

3. Startup time does not include time implemented by programmable TIMEOUTSTEADY delay.

4. The tuning step size is the effective step size when incrementing both of the tuning capacitors by one count. The step size for the each of the individual tuning capacitors is twice this value.

4.9.2 Low Frequency Crystal Oscillator

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Crystal Frequency	FLFXO		—	32.768	—	kHz
Supported Crystal equivalent	ESRLFXO	GAIN = 0	—	—	80	kΩ
series resistance (ESR)		GAIN = 1 to 3	—	—	100	kΩ
Supported range of crystal	CL_LFXO	GAIN = 0	4	—	6	pF
load capacitance 1		GAIN = 1	6	—	10	pF
		GAIN = 2 (see note2)	10	—	12.5	pF
		GAIN = 3 (see note2)	12.5	—	18	pF
Current consumption	ICL12p5	ESR = 70 kΩ, CL = 12.5 pF, GAIN3 = 2, AGC4 = 1	—	290	—	nA
Startup Time	TSTARTUP	ESR = 70 kΩ, CL = 7 pF, GAIN3 = 1, AGC4 = 1	—	52	—	ms
On-chip tuning cap step size	SSLFXO		—	0.26	—	pF
On-chip tuning capacitor val ue at minimum setting5	CLFXO_MIN	CAPTUNE = 0	—	4	—	pF
On-chip tuning capacitor val ue at maximum setting5	CLFXO_MAX	CAPTUNE = 0x4F	—	24.5	—	pF

Table 4.11. Low Frequency Crystal Oscillator

Note:

1. Total load capacitance seen by the crystal

2. Crystals with a load capacitance of greater than 12 pF require external load capacitors.

3. In LFXO_CAL Register

4. In LFXO_CFG Register

5. The effective load capacitance seen by the crystal will be CLFXO/2. This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal

4.9.3 High Frequency RC Oscillator (HFRCO)

Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.3 V. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Frequency Accuracy	FHFRCO_ACC	For all production calibrated fre quencies	-3	—	3	%
Current consumption on all supplies 1	IHFRCO	FHFRCO = 4 MHz	—	28	—	μA
		FHFRCO = 5 MHz 2	—	29	—	μA
		FHFRCO = 7 MHz	—	59	—	μA
		FHFRCO = 10 MHz 2	—	63	—	μA
		FHFRCO = 13 MHz	—	77	—	μA
		FHFRCO = 16 MHz	—	87	—	μA
		FHFRCO = 19 MHz	—	90	—	μA
		FHFRCO = 20 MHz 2	—	107	—	μA
		FHFRCO = 26 MHz	—	116	—	μA
		FHFRCO = 32 MHz	—	139	—	μA
		FHFRCO = 38 MHz 3	—	170	—	μA
		FHFRCO = 40 MHz 2	—	172	—	μA
		FHFRCO = 48 MHz 3	—	207	—	μA
		FHFRCO = 56 MHz 3	—	228	—	μA
		FHFRCO = 64 MHz 3	—	269	—	μA
		FHFRCO = 80 MHz 3	—	285	—	μA
Clock out current for HFRCODPLL4	ICLKOUT_HFRCOD PLL	FORCEEN bit of HFRCO0_CTRL = 1	—	3.0	—	μA/MHz
Clock Out current for HFRCOEM234	ICLKOUT_HFRCOE M23	FORCEEN bit of HFRCOEM23_CTRL = 1	—	1.6	—	μA/MHz
Startup Time5	TSTARTUP	FREQRANGE = 0 to 7	—	1.2	—	μs
		FREQRANGE = 8 to 15	—	0.6	—	μs

Table 4.12. High Frequency RC Oscillator (HFRCO)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Band Frequency Limits6	fHFRCO_BAND	FREQRANGE = 0	3.71	—	5.24	MHz
		FREQRANGE = 1	4.39	—	6.26	MHz
		FREQRANGE = 2	5.25	—	7.55	MHz
		FREQRANGE = 3	6.22	—	9.01	MHz
		FREQRANGE = 4	7.88	—	11.6	MHz
		FREQRANGE = 6	11.5	—	17.0	MHz
		FREQRANGE = 7	14.1	—	20.9	MHz
		FREQRANGE = 8	16.4	—	24.7	MHz
		FREQRANGE = 9	19.8	—	30.4	MHz
		FREQRANGE = 10	22.7	—	34.9	MHz
		FREQRANGE = 11	28.6	—	44.4	MHz
		FREQRANGE = 12	33.0	—	51.0	MHz
		FREQRANGE = 13	42.2	—	64.6	MHz
		FREQRANGE = 14	48.8	—	74.8	MHz
		FREQRANGE = 15	57.6	—	87.4	MHz

Note:

1. Does not include additional clock tree current. See specifications for additional current when selected as a clock source for a particular clock multiplexer.

2. This frequency is calibrated for the HFRCOEM23 only.

3. This frequency is calibrated for the HFRCODPLL only.

4. When the HFRCO is enabled for characterization using the FORCEEN bit, the total current will be the HFRCO core current plus the specified CLKOUT current. When the HFRCO is enabled on demand, the clock current may be different.

5. Hardware delay ensures settling to within ± 0.5%. Hardware also enforces this delay on a band change.

6. The frequency band limits represent the lowest and highest frequency which each band can achieve over the operating range.

4.9.4 Fast Start_Up RC Oscillator (FSRCO)

Table 4.13. Fast Start_Up RC Oscillator (FSRCO)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
FSRCO frequency	FFSRCO		17.2	20	21.2	MHz

4.9.5 Low Frequency RC Oscillator (LFRCO)

Table 4.14. Low Frequency RC Oscillator (LFRCO)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Nominal oscillation frequen cy	FLFRCO		—	32.768	—	kHz
Frequency accuracy	FLFRCO_ACC		-3	—	3	%
Frequency calibration step	FTRIM_STEP	Typical trim step at mid-scale	—	0.33	—	%
Startup time	tSTARTUP		—	220	—	μs
Current consumption	ILFRCO		—	186	—	nA

4.9.6 Ultra Low Frequency RC Oscillator

Table 4.15. Ultra Low Frequency RC Oscillator

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Oscillation Frequency	FULFRCO		0.944	1.0	1.095	kHz

4.10 GPIO Pins (3V GPIO pins)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Leakage current	ILEAK_IO	MODEx = DISABLED, IOVDD = 1.71 V	—	1.9	—	nA
		MODEx = DISABLED, IOVDD = 3.3 V	—	2.5	—	nA
		MODEx = DISABLED, IOVDD = 3.8 V, TA = 125 °C, Pins PA00, PB00-PB01, and PC06-PC09	—	—	250	nA
		MODEx = DISABLED, IOVDD = 3.8 V, TA = 125 °C, all other GPIO	—	—	200	nA
Input low voltage1	VIL	Any GPIO pin	—	—	0.3*IOVDD	V
		RESETn	—	—	0.3*DVDD	V
Input high voltage1	VIH	Any GPIO pin	0.7*IOVDD	—	—	V
		RESETn	0.7*DVDD	—	—	V
Hysteresis of input voltage	VHYS	Any GPIO pin	0.05*IOVDD	—	—	V
		RESETn	0.05*DVDD	—	—	V
Output high voltage	VOH	Sourcing 20mA, IOVDD = 3.3 V	0.8 * IOVDD	—	—	V
		Sourcing 8mA, IOVDD = 1.71 V	0.6 * IOVDD	—	—	V
Output low voltage	VOL	Sinking 20mA, IOVDD = 3.3 V	—	—	0.2 * IOVDD	V
		Sinking 8mA, IOVDD = 1.71 V	—	—	0.4 * IOVDD	V
GPIO rise time	TGPIO_RISE	IOVDD = 3.3 V, Cload = 50pF, SLEWRATE = 4, 10% to 90%	—	8.4	—	ns
		IOVDD = 1.7 V, Cload = 50pF, SLEWRATE = 4, 10% to 90%	—	13	—	ns
GPIO fall time	TGPIO_FALL	IOVDD = 3.3 V, Cload = 50pF, SLEWRATE = 4, 90% to 10%	—	7.1	—	ns
		IOVDD = 1.7 V, Cload = 50pF, SLEWRATE = 4, 90% to 10%	—	11.9	—	ns
Pull up/down resistance2	RPULL	Any GPIO pin. Pull-up to IOVDD: MODEn = DISABLE DOUT=1. Pull-down to VSS: MODEn = WIREDORPULLDOWN DOUT = 0.	33	44	55	kΩ
		RESETn pin. Pull-up to DVDD	33	44	55	kΩ
Maximum filtered glitch width	TGF	MODE = INPUT, DOUT = 1

Table 4.16. GPIO Pins (3V GPIO pins)

• Note:
• 1. GPIO input thresholds are proportional to the IOVDD pin. RESETn input thresholds are proportional to DVDD.
• 1. GPIO pull-ups connect to IOVDD supply, pull-downs connect to VSS. RESETn pull-up connects to DVDD.

4.11 Analog to Digital Converter (IADC)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Main analog supply	VAVDD	Normal mode	1.71	—	3.8	V
		High-Speed mode	1.71	—	3.8	V
		High-Accuracy mode	1.71	—	3.8	V
Maximum Input Range1	VIN_MAX	Maximum allowable input voltage	0	—	AVDD	V
Full-Scale Voltage	VFS	Voltage required for Full-Scale measurement	—	VREF / Gain	—	V
Input Measurement Range	VIN	Differential Mode - Plus and Mi nus inputs	-VFS	—	+VFS	V
		Single Ended Mode - One input tied to ground	0	—	VFS	V
Input Sampling Capacitance	Cs	Analog Gain = 1x	—	1.8	—	pF
		Analog Gain = 2x	—	3.6	—	pF
		Analog Gain = 3x	—	5.4	—	pF
		Analog Gain = 4x	—	7.2	—	pF
		Analog Gain = 0.5x	—	0.9	—	pF
ADC clock frequency	fADC_CLK	Normal mode, Gain = 1x or 0.5x	—	—	10	MHz
		Normal mode, Gain = 2x	—	—	5	MHz
		Normal mode, Gain = 3x or 4x	—	—	2.5	MHz
		High-Speed mode, Gain = 1x or 0.5x	—	—	20	MHz
		High-Speed mode, Gain = 2x	—	—	10	MHz
		High-Speed mode, Gain = 3x or 4x	—	—	5	MHz
		High-Accuracy mode	—	—	5	MHz
Input sampling frequency	fS	Normal Mode	—	fADC_CLK/4	—	MHz
		High-Speed Mode	—	fADC_CLK/4	—	MHz
		High-Accuracy Mode	—	fADC_CLK/5	—	MHz
Throughput rate	fSAMPLE	Normal mode, fCLK = 10 MHz, OSR = 2	—	—	1	Msps
		Normal mode, fCLK = 10 MHz, OSR = 32	—	—	76.9	ksps
		High-Speed mode, fCLK = 20 MHz, OSR = 2	—	—	2	Msps
		High-Accuracy mode, fCLK = 5 MHz, OSR = 92	—	—	10.7	ksps
		High-Accuracy mode, fCLK = 5 MHz, OSR = 256	—	—	3.88	ksps

Table 4.17. Analog to Digital Converter (IADC)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Main analog supply	VAVDD	Normal mode	1.71	—	3.8	V
		High-Speed mode	1.71	—	3.8	V
		High-Accuracy mode	1.71	—	3.8	V
Maximum Input Range¹	VIN_MAX	Maximum allowable input voltage	0	—	AVDD	V
Full-Scale Voltage	VFS	Voltage required for Full-Scale measurement	—	VREF / Gain	—	V
Input Measurement Range	VIN	Differential Mode - Plus and Minus inputs	-VFS	—	+VFS	V
		Single Ended Mode - One input tied to ground	0	—	VFS	V
Input Sampling Capacitance	CS	Analog Gain = 1x	—	1.8	—	pF
		Analog Gain = 2x	—	3.6	—	pF
		Analog Gain = 3x	—	5.4	—	pF
		Analog Gain = 4x	—	7.2	—	pF
		Analog Gain = 0.5x	—	0.9	—	pF
ADC clock frequency	fADC_CLK	Normal mode, Gain = 1x or 0.5x	—	—	10	MHz
		Normal mode, Gain = 2x	—	—	5	MHz
		Normal mode, Gain = 3x or 4x	—	—	2.5	MHz
		High-Speed mode, Gain = 1x or 0.5x	—	—	20	MHz
		High-Speed mode, Gain = 2x	—	—	10	MHz
		High-Speed mode, Gain = 3x or 4x	—	—	5	MHz
		High-Accuracy mode	—	—	5	MHz
Input sampling frequency	fS	Normal Mode	—	fADC_CLK/4	—	MHz
		High-Speed Mode	—	fADC_CLK/4	—	MHz
		High-Accuracy Mode	—	fADC_CLK/5	—	MHz
Throughput rate	fSAMPLE	Normal mode, fCLK = 10 MHz, OSR = 2	—	—	1	Msps
		Normal mode, fCLK = 10 MHz, OSR = 32	—	—	76.9	ksps
		High-Speed mode, fCLK = 20 MHz, OSR = 2	—	—	2	Msps
		High-Accuracy mode, fCLK = 5 MHz, OSR = 92	—	—	10.7	ksps
		High-Accuracy mode, fCLK = 5 MHz, OSR = 256	—	—	3.88	ksps

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Main analog supply	VAVDD	Normal mode	1.71	—	3.8	V
		High-Speed mode	1.71	—	3.8	V
		High-Accuracy mode	1.71	—	3.8	V
Maximum Input Range¹	VIN_MAX	Maximum allowable input voltage	0	—	AVDD	V
Full-Scale Voltage	VFS	Voltage required for Full-Scale measurement	—	VREF / Gain	—	V
Input Measurement Range	VIN	Differential Mode - Plus and Minus inputs	-VFS	—	+VFS	V
		Single Ended Mode - One input tied to ground	0	—	VFS	V
Input Sampling Capacitance	Cs	Analog Gain = 1x	—	1.8	—	pF
		Analog Gain = 2x	—	3.6	—	pF
		Analog Gain = 3x	—	5.4	—	pF
		Analog Gain = 4x	—	7.2	—	pF
		Analog Gain = 0.5x	—	0.9	—	pF
ADC clock frequency	fADC_CLK	Normal mode, Gain = 1x or 0.5x	—	—	10	MHz
		Normal mode, Gain = 2x	—	—	5	MHz
		Normal mode, Gain = 3x or 4x	—	—	2.5	MHz
		High-Speed mode, Gain = 1x or 0.5x	—	—	20	MHz
		High-Speed mode, Gain = 2x	—	—	10	MHz
		High-Speed mode, Gain = 3x or 4x	—	—	5	MHz
		High-Accuracy mode	—	—	5	MHz
Input sampling frequency	fS	Normal Mode	—	fADC_CLK/4	—	MHz
		High-Speed Mode	—	fADC_CLK/4	—	MHz
		High-Accuracy Mode	—	fADC_CLK/5	—	MHz
Throughput rate	fSAMPLE	Normal mode, fCLK = 10 MHz, OSR = 2	—	—	1	Msps
		Normal mode, fCLK = 10 MHz, OSR = 32	—	—	76.9	ksps
		High-Speed mode, fCLK = 20 MHz, OSR = 2	—	—	2	Msps
		High-Accuracy mode, fCLK = 5 MHz, OSR = 92	—	—	10.7	ksps
		High-Accuracy mode, fCLK = 5 MHz, OSR = 256	—	—	3.88	ksps

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Main analog supply	VAVDD	Normal mode	1.71	—	3.8	V
		High-Speed mode	1.71	—	3.8	V
		High-Accuracy mode	1.71	—	3.8	V
Maximum Input Range¹	VIN_MAX	Maximum allowable input voltage	0	—	AVDD	V
Full-Scale Voltage	VFS	Voltage required for Full-Scale measurement	—	VREF / Gain	—	V
Input Measurement Range	VIN	Differential Mode - Plus and Minus inputs	-VFS	—	+VFS	V
		Single Ended Mode - One input tied to ground	0	—	VFS	V
Input Sampling Capacitance	Cs	Analog Gain = 1x	—	1.8	—	pF
		Analog Gain = 2x	—	3.6	—	pF
		Analog Gain = 3x	—	5.4	—	pF
		Analog Gain = 4x	—	7.2	—	pF
		Analog Gain = 0.5x	—	0.9	—	pF
ADC clock frequency	fADC_CLK	Normal mode, Gain = 1x or 0.5x	—	—	10	MHz
		Normal mode, Gain = 2x	—	—	5	MHz
		Normal mode, Gain = 3x or 4x	—	—	2.5	MHz
		High-Speed mode, Gain = 1x or 0.5x	—	—	20	MHz
		High-Speed mode, Gain = 2x	—	—	10	MHz
		High-Speed mode, Gain = 3x or 4x	—	—	5	MHz
		High-Accuracy mode	—	—	5	MHz
Input sampling frequency	fS	Normal Mode	—	fADC_CLK/4	—	MHz
		High-Speed Mode	—	fADC_CLK/4	—	MHz
		High-Accuracy Mode	—	fADC_CLK/5	—	MHz
Throughput rate	fSAMPLE	Normal mode, fCLK = 10 MHz, OSR = 2	—	—	1	Msps
		Normal mode, fCLK = 10 MHz, OSR = 32	—	—	76.9	ksps
		High-Speed mode, fCLK = 20 MHz, OSR = 2	—	—	2	Msps
		High-Accuracy mode, fCLK = 5 MHz, OSR = 92	—	—	10.7	ksps
		High-Accuracy mode, fCLK = 5 MHz, OSR = 256	—	—	3.88	ksps

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Main analog supply	VAVDD	Normal mode	1.71	—	3.8	V
		High-Speed mode	1.71	—	3.8	V
		High-Accuracy mode	1.71	—	3.8	V
Maximum Input Range¹	VIN_MAX	Maximum allowable input voltage	0	—	AVDD	V
Full-Scale Voltage	VFS	Voltage required for Full-Scale measurement	—	VREF / Gain	—	V
Input Measurement Range	VIN	Differential Mode - Plus and Minus inputs	-VFS	—	+VFS	V
		Single Ended Mode - One input tied to ground	0	—	VFS	V
Input Sampling Capacitance	Cs	Analog Gain = 1x	—	1.8	—	pF
		Analog Gain = 2x	—	3.6	—	pF
		Analog Gain = 3x	—	5.4	—	pF
		Analog Gain = 4x	—	7.2	—	pF
		Analog Gain = 0.5x	—

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Gain Error, High-speed mode	GEHS	GAIN = 1 and 0.5, using external VREF, direct mode.	-0.3	0.069	0.3	%
		GAIN = 2, using external VREF, direct mode.	-0.4	0.151	0.4	%
		GAIN = 3, using external VREF, direct mode.	-0.7	0.186	0.7	%
		GAIN = 4, using external VREF, direct mode.	-1.1	0.227	1.1	%
		Internal VREF 5, all GAIN settings	-1.5	0.023	1.5	%
Gain Error, High-accuracy mode3	GEHA	GAIN = 1 and 0.5, using external VREF, direct mode.	TBD	0.06	TBD	%
		GAIN = 2, using external VREF, direct mode.	TBD	0.16	TBD	%
		GAIN = 4, using external VREF, direct mode.	TBD	0.25	TBD	%
Internal Reference voltage	VIVREF		—	1.21	—	V

Note:

1. When inputs are routed to external GPIO pins, the maximum pin voltage is limited to the lower of the IOVDD and AVDD supplies.

2. ADC output resolution depends on the OSR and digital averaging settings. With no digital averaging, ADC output resolution is 12 bits at OSR = 2, 13 bits at OSR = 4, 14 bits at OSR = 8, 15 bits at OSR = 16, 16 bits at OSR = 32 and 17 bits at OSR = 64. Digital averaging has a similar impact on ADC output resolution. See the product reference manual for additional details.

3. High-Accuracy mode performance specifications are tested with inputs applied to the dedicated AIN pins.

4. The relationship between ENOB and SNDR is specified according to the equation: ENOB = (SNDR - 1.76) / 6.02.

5. Includes error from internal VREF drift.

4.12 Analog Comparator (ACMP)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
ACMP Supply current	IACMP	BIAS = 2 1, HYST = DISABLED	—	520	—	nA
		BIAS = 3 1, HYST = DISABLED	—	1.9	—	μA
		BIAS = 4, HYST = DISABLED	—	5.4	—	μA
		BIAS = 5, HYST = DISABLED	—	10.7	—	μA
		BIAS = 6, HYST = DISABLED	—	27	—	μA
		BIAS = 7, HYST = DISABLED	—	50	100	μA
ACMP Supply current with	IACMP_WHYS	BIAS = 2 1, HYST = SYM30MV	—	780	—	nA
Hysteresis		BIAS = 3 1, HYST = SYM30MV	—	2.8	—	μA
		BIAS = 4, HYST = SYM30MV	—	7.3	—	μA
		BIAS = 5, HYST = SYM30MV	—	15	—	μA
		BIAS = 6, HYST = SYM30MV	—	38	—	μA
		BIAS = 7, HYST = SYM30MV	—	71	—	μA
Current consumption from	IVREFDIV	NEGSEL = VREFDIVAVDD	—	3.4	—	μA
VREFDIV in continuous mode		NEGSEL = VREFDIV1V25	—	4.2	—	μA
		NEGSEL = VREFDIV2V5	—	6.9	—	μA
Current consumption from VREFDIV in sample/hold mode	IVREFDIV_SH	NEGSEL = VREFDIV2V5LP	—	76	—	nA
		NEGSEL = VREFDIV1V25LP	—	73	—	nA
		NEGSEL = VREFDIVAVDDLP	—	72	—	nA
Current consumption from VSENSEDIV in continuous mode	IVSENSEDIV	NEGSEL = VSENSE01DIV4	—	1.8	—	μA
Current consumption from VSENSEDIV in sample/hold mode	IVSENSEDIV_SH	NEGSEL = VSENSE01DIV4LP	—	58	—	nA
Hysteresis (BIAS = 4)	VHYST	HYST = SYM10MV2	—	18	—	mV
		HYST = SYM2

Table 4.18. Analog Comparator (ACMP)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Comparator delay with 100 mV overdrive	TDELAY	BIAS = 2	—	0.87	—	μs
		BIAS = 3	—	0.28	—	μs
		BIAS = 4	—	160	—	ns
		BIAS = 5	—	94	—	ns
		BIAS = 6	—	60	—	ns
		BIAS = 7	—	49	—	ns
Capacitive Sense Oscillator Resistance	RCSRESSEL	CSRESSEL = 0	—	14	—	kΩ
		CSRESSEL = 1	—	24	—	kΩ
		CSRESSEL = 2	—	43	—	kΩ
		CSRESSEL = 3	—	60	—	kΩ
		CSRESSEL = 4	—	80	—	kΩ
		CSRESSEL = 5	—	99	—	kΩ
		CSRESSEL = 6	—	120	—	kΩ

Note:

1. When using the 1.25 V or 2.5 V VREF in continuous mode (VREFDIV1V25 or VREFDIV2V5) and BIAS < 4, an additional 1 μA of supply current is required.

2. VCM = 1.25 V

4.13 Digital to Analog Converter (VDAC)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Output voltage	VDACOUT		0	—	VREF	V
Output Current	IDACOUT		-10	—	10	mA
DAC clock frequency	fDAC		—	—	1	MHz
Sample rate	SRDAC	fDAC = fDAC(max)	—	—	500	ksps
Resolution	NRESOLUTION		—	12	—	bits
Load Capacitance1	CLOAD	High Power and Lower Power Modes	—	—	50	pF
		High Capacitance Load Mode	25	—	—	nF
Load Resistance	RLOAD		5	—	—	kΩ
Current consumption, Dy namic, 500 ksps, 1 channel active2	IDAC_1_500	High Power Mode	—	255	—	μA
		Low Power Mode	—	150	—	μA
Current consumption, Dy namic, 500 ksps, 2 channels active2	IDAC_2_500	High Power Mode	—	421	—	μA
		Low Power Mode	—	216	—	μA
Current consumption, Static, 1 channel active3	IDAC_1_STAT	High Power Mode	—	136	—	μA
		Low Power Mode	—	31	—	μA
		High Capacitance Mode	—	44	—	μA
Current consumption, Static, 2 channels active3	IDAC_2_STAT	High Power Mode	—	263	TBD	μA
		Low Power Mode	—	53	TBD

Table 4.19. Digital to Analog Converter (VDAC)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Integral Non-Linearity	INLDAC	High Power Mode, Across full temperature range	-5	—	5	LSB
Differential Non-Linearity5	DNLDAC	High Power Mode, Across full temperature range	-1	—	1.3	LSB
Offset error6	VOFFSET	High Power mode	-15	—	15	mV
		Low Power Mode	-25	—	25	mV
		High Capacitance Load mode	-35	—	35	mV
Gain error6	VGAIN	1.25 V internal reference	-1.5	—	1.5	%
		2.5 V internal reference	-2	—	2	%
		External Reference	-0.6	—	0.6	%
External Reference Voltage7	VEXTREF		1.1	—	V_AVDD	V

Note:

1. Main outputs only.

2. Dynamic current specifications are for VDAC circuitry operating at max clock frequency with the output updated at the specified sampling rate using DMA transfers. Output is a 1 kHz sine wave from 10% to 90% full scale. Specified current does not include current required to drive the external load. Measurement includes all current from AVDD and DVDD supplies.

3. Static current specifications are for VDAC circuitry operating after a one-time update to a static output at 50% full scale, with the VDAC APB clock disabled. Specified current does not include current required to drive the external load. Measurement includes all current from AVDD and DVDD supplies.

• 1. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT).
• 1. Entire range is monotonic and has no missing codes.

1. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at 10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.

2. External reference voltage on VREFP pin or PA00 when used for VREFP

Table 4.20. LCD

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
LCD Temperature Range	TRANGE		-40	—	105	°C
Frame rate	fLCDFR		30	—	100	Hz
LCD supply range1 2	VLCDIN		1.71	—	3.8	V
LCD output voltage range2	VLCD	Step-down mode with external LCD capacitor	2.4	—	VLCDIN	V
		Charge pump mode with external LCD capacitor	2.4	—	1.9 * VLCDIN	V
Contrast control step size	STEPCONTRAST	Charge pump or Step-down mode	—	50	—	mV
Contrast control step accura cy3	ACCCONTRAST		—	+/-1.5	—	%

Note:

1. VLCDIN is selectable between the AVDD or DVDD supply pins, depending on EMU_PWRCTRL_ANASW.

2. VLCDIN and VLCD should be a maximum of 2 V above VIOVDDto avoid additional leakage through the GPIO pins used for LCD functions.

3. Step size accuracy is measured relative to the typical step size, and typ value represents one standard deviation.

4.15 Temperature Sensor

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Temperature sensor range1	TRANGE		-40	—	125	°C
Temperature sensor resolu tion	TRESOLUTION		—	0.25	—	°C
Measurement noise (RMS)	TNOISE	Single measurement	—	0.6	—	°C
		16-sample average (TEMPAVG NUM = 0)	—	0.17	—	°C
		64-sample average (TEMPAVG NUM = 1)	—	0.12	—	°C
Temperature offset	TOFF	Mean error of uncorrected output across full temperature range	—	3.7	—	°C
Temperature sensor accura cy2 3	TACC	Direct output accuracy after mean error (TOFF) removed	—	+/-3	—	°C
		After linearization in software, no calibration	—	+/-2	—	°C
		After linearization in software, with single-temperature calibration at 25 °C4	—	+/-1.5	—	°C
Measurement interval	tMEAS		—	250	—	ms

Table 4.21. Temperature Sensor

Note:

1. The sensor reports absolute die temperature in °K. All specifications are in °C to match the units of the specified product temperature range.

2. Error is measured as the deviation of the mean temperature reading from the expected die temperature. Accuracy numbers represent statistical minimum and maximum using ± 4 standard deviations of measured error.

3. The raw output of the temperature sensor is a predictable curve. It can be linearized with a polynomial function for additional accuracy.

4. Assuming calibration accuracy of ± 0.25 °C.

4.16 Brown Out Detectors

4.16.1 DVDD BOD

BOD thresholds on DVDD in EM0 and EM1 only, unless otherwise noted. Typical conditions are at T^A = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.

Table 4.22. DVDD BOD

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
BOD threshold	VDVDD_BOD	Supply Rising	—	1.67	1.71	V
		Supply Falling	1.62	1.65	—	V
BOD response time	tDVDD_BOD_DE LAY	Supply dropping at 100 mV/μs slew rate1	—	0.95	—	μs
BOD hysteresis	VDVDD_BOD_HYS T		—	22	—	mV

Note:

1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

4.16.2 LE DVDD BOD

BOD thresholds on DVDD pin for low energy modes EM2 to EM4, unless otherwise noted.

Table 4.23. LE DVDD BOD

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
BOD threshold	VDVDD_LE_BOD	Supply Falling	1.5	—	1.71	V
BOD response time	tDVDD_LE_BOD_D ELAY	Supply dropping at 2 mV/μs slew rate1	—	50	—	μs
BOD hysteresis	VDVDD_LE_BOD_ HYST		—	20	—	mV

Note:

1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

4.16.3 AVDD and IOVDD BODs

BOD thresholds for AVDD BOD and IOVDD BOD. Available in all energy modes.

Table 4.24. AVDD and IOVDD BODs

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
BOD threshold	VBOD	Supply falling	1.45	—	1.71	V
BOD response time	tBOD_DELAY	Supply dropping at 2 mV/μs slew rate1	—	50	—	μs
BOD hysteresis	VBOD_HYST		—	20	—	mV

Note:

1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

4.17 Pulse Counter

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Input frequency	FIN	Asynchronous Single and Quad rature Modes	—	—	1.0	MHz
		Sampled Modes with Debounce filter set to 0.	—	—	8	kHz
Setup time in asynchronous external clock mode	tSU_S1N_S0N	S1N (data) to S0N (clock)	50	—	—	ns
Hold time in asynchronous external clock mode	tHD_S0N_S1N	S0N (clock) to S1N (data)	50	—	—	ns

Table 4.25. Pulse Counter

Figure 4.1. SPI Main Timing (SMSDELAY = 0)

Figure 4.2. SPI Main Timing (SMSDELAY = 1)

4.18.1 USART SPI Main Interface Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew rate = 6.

Table 4.26. USART SPI Main Interface Timing, Voltage Scaling = VSCALE2

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK period 1 2 3	tSCLK		2*tPCLK	—	—	ns
CS to MOSI 1 2	tCS_MO		-17	—	22	ns
SCLK to MOSI 1 2	tSCLK_MO		-12	—	12	ns
MISO setup time 1 2	tSU_MI	IOVDD = 1.62 V	39	—	—	ns
		IOVDD = 3.3 V	28	—	—	ns
MISO hold time 1 2	tH_MI		-10	—	—	ns
Note:

1. Measurement done with 8 pF output loading at 10% and 90% of VDD.

2. tPCLK is one period of the selected PCLK.

4.18.2 USART SPI Main Interface Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew rate = 6.

Table 4.27. USART SPI Main Interface Timing, Voltage Scaling = VSCALE1

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK period 1 2 3	tSCLK		2*tPCLK	—	—	ns
CS to MOSI 1 2	tCS_MO		-24	—	32	ns
SCLK to MOSI 1 2	tSCLK_MO		-12	—	20	ns
MISO setup time 1 2	tSU_MI	IOVDD = 1.62 V	47	—	—	ns
		IOVDD = 3.3 V	39	—	—	ns
MISO hold time 1 2	tH_MI		-11	—	—	ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1.

2. Measurement done with 8 pF output loading at 10% and 90% of VDD.

3. tPCLK is one period of the selected PCLK.

4.19 USART SPI Secondary Timing

Figure 4.3. SPI Secondary Timing (SSSEARLY = 0)

Figure 4.4. SPI Secondary Timing (SSSEARLY = 1)

4.19.1 USART SPI Secondary Interface Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew rate = 6.

	Table 4.28. USART SPI Secondary Interface Timing, Voltage Scaling = VSCALE2
--	-----------------------------------------------------------------------------

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK period 1 2 3	tSCLK		6*tPCLK	—	—	ns
SCLK high time1 2 3	tSCLK_HI		2.5*tPCLK	—	—	ns
SCLK low time1 2 3	tSCLK_LO		2.5*tPCLK	—	—	ns
CS active to MISO 1 2	tCS_ACT_MI		18	—	75	ns
CS disable to MISO 1 2	tCS_DIS_MI		16	—	66	ns
MOSI setup time 1 2	tSU_MO		6	—	—	ns
MOSI hold time 1 2 3	tH_MO		5	—	—	ns
SCLK to MISO 1 2 3	tSCLK_MI		14 + 1.5*tPCLK	—	29 + 2.5*tPCLK	ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).

3. tPCLK is one period of the selected PCLK.

4.19.2 USART SPI Secondary Interface Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew rate = 6.

		Table 4.29. USART SPI Secondary Interface Timing, Voltage Scaling = VSCALE1
--	--	-----------------------------------------------------------------------------

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK period 1 2 3	tSCLK		6*tPCLK	—	—	ns
SCLK high time1 2 3	tSCLK_HI		2.5*tPCLK	—	—	ns
SCLK low time1 2 3	tSCLK_LO		2.5*tPCLK	—	—	ns
CS active to MISO 1 2	tCS_ACT_MI		23	—	102	ns
CS disable to MISO 1 2	tCS_DIS_MI		22	—	93	ns
MOSI setup time 1 2	tSU_MO		9	—	—	ns
MOSI hold time 1 2 3	tH_MO		9	—	—	ns
SCLK to MISO 1 2 3	tSCLK_MI		18 + 1.5*tPCLK	—	36 + 2.5*tPCLK	ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).

3. tPCLK is one period of the selected PCLK.

4.20 EUSART SPI Main Timing

Figure 4.5. SPI Main Timing

4.20.1 EUSART SPI Main Interface Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew rate = 6.

Table 4.30. EUSART SPI Main Interface Timing, Voltage Scaling = VSCALE2

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK period 1 2 3	tSCLK			—	—	ns
CS to MOSI 1 2	tCS_MO		-10	—	8	ns
SCLK to MOSI 1 2	tSCLK_MO		-3	—	8	ns
MISO setup time 1 2	tSU_MI		7	—	—	ns
MISO hold time 1 2	tH_MI		3	—	—	ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1.

2. Measurement done with 15 pF output loading at 10% and 90% of VDD.

3. tCLK is one period of the selected peripheral clock: EM01GRPCCLK for EUSART1/2, EUSART0CLK for EUSART0.

4.20.2 EUSART SPI Main Interface Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew rate = 6.

Table 4.31. EUSART SPI Main Interface Timing, Voltage Scaling = VSCALE1

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK period 1 2 3	tSCLK			—	—	ns
CS to MOSI 1 2	tCS_MO		-18	—	15	ns
SCLK to MOSI 1 2	tSCLK_MO		-4	—	13	ns
MISO setup time 1 2	tSU_MI		12	—	—	ns
MISO hold time 1 2	tH_MI		3	—	—	ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1.

2. Measurement done with 15 pF output loading at 10% and 90% of VDD.

3. tCLK is one period of the selected peripheral clock: EM01GRPCCLK for EUSART1/2, EUSART0CLK for EUSART0.

4.21 EUSART SPI Secondary Timing

4.21.1 EUSART SPI Secondary Interface Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew rate = 6.

Table 4.32. EUSART SPI Secondary Interface Timing, Voltage Scaling = VSCALE2

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK high time1 2	tSCLK_HI		50	—	—	ns
SCLK low time1 2	tSCLK_LO		50	—	—	ns
CS active to MISO 1 2	tCS_ACT_MI		5	—	50	ns
CS disable to MISO 1 2	tCS_DIS_MI		7	—	40	ns
MOSI setup time 1 2	tSU_MO		5	—	—	ns
MOSI hold time 1 2	tH_MO		6	—	—	ns
SCLK to MISO 1 2	tSCLK_MI	IOVDD = 1.8 V	9	—	40	ns
		IOVDD = 3.3 V	9	—	30	ns
Note:

1. Measurement done with 15 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).

4.21.2 EUSART SPI Secondary Interface Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew rate = 6.

Table 4.33. EUSART SPI Secondary Interface Timing, Voltage Scaling = VSCALE1

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK high time1 2	tSCLK_HI		50	—	—	ns
SCLK low time1 2	tSCLK_LO		50	—	—	ns
CS active to MISO 1 2	tCS_ACT_MI		6	—	75	ns
CS disable to MISO 1 2	tCS_DIS_MI		6	—	60	ns
MOSI setup time 1 2	tSU_MO		8	—	—	ns
MOSI hold time 1 2	tH_MO		11	—	—	ns
SCLK to MISO 1 2	tSCLK_MI	IOVDD = 1.8 V	10	—	50	ns
		IOVDD = 3.3 V	10	—	42	ns
Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 15 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).

4.21.3 EUSART SPI Secondary Interface Timing, Voltage Scaling = VSCALE0

Timing specifications at VSCALE0 apply to EUSART0 only, routed to DBUSAB on consecutive pins. All GPIO set to slew rate = 6.

Table 4.34. EUSART SPI Secondary Interface Timing, Voltage Scaling = VSCALE0

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCLK high time1 2	tSCLK_HI		100	—	—	ns
SCLK low time1 2	tSCLK_LO		100	—	—	ns
CS active to MISO 1 2	tCS_ACT_MI		8	—	112	ns
CS disable to MISO 1 2	tCS_DIS_MI		8	—	82	ns
MOSI setup time 1 2	tSU_MO		12	—	—	ns
MOSI hold time 1 2	tH_MO		32	—	—	ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 15 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).

4.22 I2C Electrical Specifications

4.22.1 I2C Standard-mode (Sm)

CLHR set to 0 in the I2Cn_CTRL register.

Table 4.35. I2C Standard-mode (Sm)

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCL clock frequency1	fSCL		0	—	100	kHz
SCL clock low time	tLOW		4.7	—	—	μs
SCL clock high time	tHIGH		4	—	—	μs
SDA set-up time	tSU_DAT		250	—	—	ns
SDA hold time	tHD_DAT		0	—	—	ns
Repeated START condition set-up time	tSU_STA		4.7	—	—	μs
Repeated START condition hold time	tHD_STA		4.0	—	—	μs
STOP condition set-up time	tSU_STO		4.0	—	—	μs
Bus free time between a STOP and START condition	tBUF		4.7	—	—	μs

Note:

1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV should be set to a value that keeps the SCL clock frequency below the max value listed.

4.22.2 I2C Fast-mode (Fm)

CLHR set to 1 in the I2Cn_CTRL register.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCL clock frequency¹	fSCL		0	—	400	kHz
SCL clock low time	tLOW		1.3	—	—	μs
SCL clock high time	tHIGH		0.6	—	—	μs
SDA set-up time	tSU_DAT		100	—	—	ns
SDA hold time	tHD_DAT		0	—	—	ns
Repeated START condition set-up time	tSU_STA		0.6	—	—	μs
Repeated START condition hold time	tHD_STA		0.6	—	—	μs
STOP condition set-up time	tSU_STO		0.6	—	—	μs
Bus free time between a STOP and START condition	tBUF		1.3	—	—	μs

Note:

1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV should be set to a value that keeps the SCL clock frequency below the max value listed.

4.22.3 I2C Fast-mode Plus (Fm+)

CLHR set to 1 in the I2Cn_CTRL register.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
SCL clock frequency1	fSCL		0	—	1000	kHz
SCL clock low time	tLOW		0.5	—	—	μs
SCL clock high time	tHIGH		0.26	—	—	μs
SDA set-up time	tSU_DAT		50	—	—	ns
SDA hold time	tHD_DAT		0	—	—	ns
Repeated START condition set-up time	tSU_STA		0.26	—	—	μs
Repeated START condition hold time	tHD_STA		0.26	—	—	μs
STOP condition set-up time	tSU_STO		0.26	—	—	μs
Bus free time between a STOP and START condition	tBUF		0.5	—	—	μs

Table 4.37. I2C Fast-mode Plus (Fm+)

Note:

1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV should be set to a value that keeps the SCL clock frequency below the max value listed.

4.23 Boot Timing

Secure boot impacts the recovery time from all sources of device reset. In addition to the root code authentication process, which cannot be disabled or bypassed, the root code can authenticate a bootloader, and the bootloader can authenticate the application. In projects that include only an application and no bootloader, the root code can authenticate the application directly. The duration of each authentication operation depends on two factors: the computation of the associated image hash, which is proportional to the size of the image, and the verification of the image signature, which is independent of image size.

The duration for the root code to authenticate the bootloader will depend on the SE firmware version as well as on the size of the bootloader.

The duration for the bootloader to authenticate the application can depend on the size of the application.

The configurations below assume that the associated bootloader and application code images do not contain a bootloader certificate or an application certificate. Authenticating a bootloader certificate or an application certificate will extend the boot time by an additional 6 to 7 ms.

The table below provides the durations from the termination of reset until the completion of the secure boot process (start of main() function in the application image) under various conditions.

Conditions:

• SE firmware version 2.1.4
• Gecko Bootloader size 24 kB

Timing is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any significant changes.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Boot time¹	tBOOT	Secure boot application check dis abled, 50 kB application size	—	46.4	—	ms
		Secure boot application check en abled, 50 kB application size	—	57.2	—	ms
		Secure boot application check en abled, 150 kB application size	—	59.9	—	ms
		Secure boot application check en abled, 350 kB application size	—	65.2	—	ms
Note:		1. Secure boot check of second stage bootloader enabled for all measurements.

Table 4.38. Boot Timing

4.24 Crypto Operation Timing for SE Manager API

Values in this table represent timing from SE Manager API call to return. The Cortex-M33 HCLK frequency is 39.0 MHz. The timing specifications below are measured at the SE Manager function call API. Each duration in the table contains some portion that is influenced by SE Manager build compilation and Cortex-M33 operating frequency and some portion that is influenced by the Hardware Secure Engine's firmware version and its operating speed (typically 80 MHz). The contributions of the Cortex-M33 properties to the overall specification timing are most pronounced for the shorter operations such as AES and hash when operating on small payloads. The overhead of command processing at the mailbox interface can also dominate the timing for shorter operations.

Conditions:

• SE firmware version 2.1.4
• GSDK version 3.2

Timing is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any significant changes.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
AES-128 timing	tAES128	AES-128 CCM encryption, PT 1 kB	—	548	—	μs
		AES-128 CCM encryption, PT 32 kB	—	1737	—	μs
		AES-128 CTR encryption, PT 1 kB	—	439	—	μs
		AES-128 CTR encryption, PT 32 kB	—	1006	—	μs
		AES-128 GCM encryption, PT 1 kB	—	492	—	μs
		AES-128 GCM encryption, PT 32 kB	—	1061	—	μs
AES-256 timing	tAES256	AES-256 CCM encryption, PT 1 kB	—	563	—	μs
		AES-256 CCM encryption, PT 32 kB	—	2161	—	μs
		AES-256 CTR encryption, PT 1 kB	—	446	—	μs
		AES-256 CTR encryption, PT 32 kB	—	1220	—	μs
		AES-256 GCM encryption, PT 1 kB	—	500	—	μs
		AES-256 GCM encryption, PT 32 kB	—	1274	—	μs
ECC P-256 timing	tECC_P256	ECC key generation, P-256	—	5.5	—	ms
		ECC signing, P-256	—	5.9	—	ms
		ECC verification, P-256	—	6.1	—	ms
ECC P-521 timing1	tECC_P521	ECC key generation, P-521	—	30.3	—	ms
		ECC signing, P-521	—	31	—	ms
		ECC verification, P-521	—	36.1	—	ms
ECC P-25519 timing2	tECC_P25519	ECC key generation, P-25519	—	4.5	—	ms
		ECC signing, P-25519	—	8.9	—	ms
		ECC verification, P-25519	—	6.3	—	ms
ECDH compute secret timing	tECDH	ECDH compute secret, P-5211	—	30.3	—	ms
		ECDH compute secret, P-255192	—	4.4	—	ms
		ECDH compute secret, P-256	—	5.7	—	ms

Table 4.39. StdCmd Timing

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
ECJPAKE client timing	tECJPAKE_C	ECJPAKE client write round one	—	21.5	—	ms
		ECJPAKE client read round one	—	11.7	—	ms
		ECJPAKE client write round two	—	15.2	—	ms
		ECJPAKE client read round two	—	6.4	—	ms
		ECJPAKE client derive secret	—	8.7	—	ms
ECJPAKE server timing	tECJPAKE_S	ECJPAKE server write round one	—	21.5	—	ms
		ECJPAKE server read round one	—	11.7	—	ms
		ECJPAKE server write round two	—	15.2	—	ms
		ECJPAKE server read round two	—	6.4	—	ms
		ECJPAKE server derive secret	—	8.8	—	ms
POLY-1305 timing¹	tPOLY1305	POLY-1305, PT 1 kB	—	478	—	μs
		POLY-1305, PT 32 kB	—	1140	—	μs
SHA-256 timing	tSHA256	SHA-256, PT 1 kB	—	263	—	μs
		SHA-256, PT 32 kB	—	685	—	μs
SHA-512 timing¹	tSHA512	SHA-512, PT 1 kB	—	260	—	μs
		SHA-512, PT 32 kB	—	573	—	μs

1. Option is not available on Secure Vault Mid devices with SE firmware earlier than v2.1.7.

4.25 Crypto Operation Average Current for SE Manager API

Values in this table represent current consumed by security core during the operation, and represent additions to the current consumed by the Cortex-M33 application CPU due to the Hardware Secure Engine CPU and its associated crypto accelerators. The current measurements below represent the average value of the current for the duration of the crypto operation. Instantaneous peak currents may be higher.

Conditions:

• SE firmware version 2.1.4
• GSDK version 3.2

Current consumption is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any significant changes.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
ECJPAKE client timing	ᵀECJPAKE_C	ECJPAKE client write round one	—	21.5	—	ms
		ECJPAKE client read round one	—	11.7	—	ms
		ECJPAKE client write round two	—	15.2	—	ms
		ECJPAKE client read round two	—	6.4	—	ms
		ECJPAKE client derive secret	—	8.7	—	ms
ECJPAKE server timing	ᵀECJPAKE_S	ECJPAKE server write round one	—	21.5	—	ms
		ECJPAKE server read round one	—	11.7	—	ms
		ECJPAKE server write round two	—	15.2	—	ms
		ECJPAKE server read round two	—	6.4	—	ms
		ECJPAKE server derive secret	—	8.8	—	ms
POLY-1305 timing¹	ᵀPOLY1305	POLY-1305, PT 1 kB	—	478	—	µs
		POLY-1305, PT 32 kB	—	1140	—	µs
SHA-256 timing	ᵀSHA256	SHA-256, PT 1 kB	—	263	—	µs
		SHA-256, PT 32 kB	—	685	—	µs
SHA-512 timing¹	ᵀSHA512	SHA-512, PT 1 kB	—	260	—	µs
		SHA-512, PT 32 kB	—	573	—	µs

Table 4.40. StdCmd Supply Current

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
ECJPAKE client current	IECJPAKE_C	ECJPAKE client write round one	—	2.5	—	mA
		ECJPAKE client read round one	—	2.5	—	mA
		ECJPAKE client write round two	—	2.5	—	mA
		ECJPAKE client read round two	—	2.4	—	mA
		ECJPAKE client derive secret	—	2.5	—	mA
ECJPAKE server current	IECJPAKE_S	ECJPAKE server write round one	—	2.5	—	mA
		ECJPAKE server read round one	—	2.5	—	mA
		ECJPAKE server write round two	—	2.5	—	mA
		ECJPAKE server read round two	—	2.4	—	mA
		ECJPAKE server derive secret	—	2.5	—	mA
POLY-1305 current¹	IPOLY1305	POLY-1305, PT 1 kB	—	1.5	—	mA
		POLY-1305, PT 32 kB	—	2.4	—	mA
SHA-256 current	ISHA256	SHA-256, PT 1 kB	—	1.5	—	mA
		SHA-256, PT 32 kB	—	3.1	—	mA
SHA-512 current¹	ISHA512	SHA-512, PT 1 kB	—	1.5	—	mA
		SHA-512, PT 32 kB	—	2.7	—	mA
Note:

1. Option is not available on Secure Vault Mid devices with SE firmware earlier than v2.1.7.

4.26 Typical Performance Curves

Typical performance curves indicate typical characterized performance under the stated conditions.

Figure 4.7. EM0 and EM1 Typical Supply Current vs. Temperature

Figure 4.8. EM2 and EM4 Typical Supply Current vs. Temperature

4.26.2 DC-DC Converter

Performance characterized with Samsung CIG22H2R2MNE (LDCDC = 2.2 uH ) and Samsung CL10B475KQ8NQNC (CDCDC = 4.7 uF)

Figure 4.9. DC-DC Efficiency

4.26.3 IADC

Typical performance is shown across diffefrent oversampling ratio (OSR) settings with the maximum speed ADC clock. The ADC clock speed is 10 MHz for Normal mode, 20 MHz for High Speed mode, and 5 MHz for High Accuracy mode.

Figure 4.10. Typical ENOB vs. Oversampling Ratio

Figure 4.11. VOH and VOL vs. Load Current

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at https://www.silabs.com/about-us/corporate-responsibility/commitment-toquality.

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Storage temperature range	TSTG		-50	—	+150	°C
Voltage on any supply pin	VDDMAX		-0.3	—	3.8	V
Junction temperature	TJMAX	-I grade	—	—	+125	°C
Voltage ramp rate on any supply pin	VDDRAMPMAX		—	—	1.0	V / μs
Voltage on HFXO pins	VHFXOPIN		-0.3	—	1.2	V
DC voltage on any GPIO pin1	VDIGPIN		-0.3	—	VIOVDD + 0.3	V
DC voltage on RESETn pin2	VRESETn		-0.3	—	3.8	V
Total current into VDD power lines	IVDDMAX	Source	—	—	200	mA
Total current into VSS ground lines	IVSSMAX	Sink	—	—	200	mA
Current per I/O pin	IIOMAX	Sink	—	—	50	mA
		Source	—	—	50	mA
Current for all I/O pins	IIOALLMAX	Sink	—	—	200	mA
		Source	—	—	200	mA

Package	Board	Parameter	Symbol	Test Condition	Value	Unit
40QFN (5x5mm)	JEDEC - High Thermal Cond.	Thermal Resistance, Junction to Ambient	ΘJA	Still Air	29.2	°C/W
	(2s2p)1	Thermal Resistance, Junction to Board	ΘJB		15.2	°C/W
		Thermal Resistance, Junction to Top Center	ѰJT		0.3	°C/W
		Thermal Resistance, Junction to Board	ѰJB		11.2	°C/W
	No Board	Thermal Resistance, Junction to Case	ΘJC	Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow.	24.6	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p)1	Thermal Resistance, Junction to Ambient	ΘJA	Still Air	27.7	°C/W
		Thermal Resistance, Junction to Board	ΘJB		14.6	°C/W
		Thermal Resistance, Junction to Top Center	ѰJT		0.69	°C/W
		Thermal Resistance, Junction to Board	ѰJB		11.85	°C/W
	No Board	Thermal Resistance, Junction to Case	ΘJC	Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow.	23.0	°C/W