DRV8302DCAR
Three-Phase Gate Driver with Dual Shunt Amplifiers and Buck RegulatorThe DRV8302DCAR is a three-phase gate driver with dual shunt amplifiers and buck regulator from Texas Instruments. View the full DRV8302DCAR datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
DRV8302DCAR shares its datasheet with DRV8302, whose page lists every part number it covers.
Official DRV8302DCAR datasheet (PDF) — the source this page was extracted from.
Manufacturer
Texas InstrumentsCategory
Three-Phase Gate Driver with Dual Shunt Amplifiers and Buck Regulator
Package
HTSSOP-56
DRV8302DCAR Key Specifications
| Parameter | Value |
|---|---|
| Control Interface | Hardware Control |
| Package Dimensions | 14.00mm x 6.10mm |
| Gate Drive Sink Current | 2.3A (peak) |
| Gate Drive Source Current | 1.7A (peak) |
| Operating Temperature Range | -40°C to 125°C |
| Shunt Amplifier Gain Options | 10V/V, 40V/V |
| Supply Voltage Range (PVDD1) | 8V to 60V |
| Buck Converter Output Current | 1.5A (max) |
| Standby Supply Current (PVDD1) | 20 µA (typ) |
| Gate Driver Switching Frequency | up to 200 kHz |
| Logic Interface Voltage Support | 3.3V and 5V |
| Buck Converter Switching Frequency | 450 kHz to 720 kHz |
| Buck Shutdown Supply Current (PVDD2) | 1.3 µA (typ) |
| Supply Voltage Range (PVDD2 For Buck) | 3.5V to 60V |
DRV8302DCAR Overview
Part: DRV8302 (DRV8302DCAR) — Texas Instruments
Type: Three-Phase Gate Driver with Dual Current Shunt Amplifiers and Buck Regulator (hardware controlled)
Description: 8–60 V, three-phase MOSFET gate driver with 1.7 A source / 2.3 A sink gate drive, dual current shunt amplifiers, and an integrated buck converter delivering up to 1.5 A.
Operating Conditions:
- Supply voltage: PVDD1 8–60 V (gate driver); PVDD2 3.5–60 V (buck converter)
- Operating temperature: -40 to 125 °C (ambient)
- Gate driver switching frequency: up to 200 kHz (Qg(TOT) = 25 nC or 30 mA total average gate drive current)
- Shunt amplifier REF voltage: 2–6 V
Absolute Maximum Ratings:
- Max supply voltage (PVDD, relative to PGND): 65 V
- Max supply voltage ramp rate: 1 V/μs
- Logic pin input voltage: -0.3 to 7 V
- GVDD pin: 13.2 V max
- AVDD pin: 8 V max
- DVDD pin: 3.6 V max
- Open-drain sink current (nFAULT, nOCTW): 7 mA
- Operating junction temperature: -40 to 150 °C
- Storage temperature: -55 to 150 °C
Key Specs:
- Gate drive current: 1.7 A source, 2.3 A sink
- Dead time (DTC): 50 ns (DTC to GND) to 500 ns (150 kΩ), linear approximation
- Current shunt amplifier gain: 10 V/V or 40 V/V (GAIN pin)
- Shunt amplifier output offset: adjustable up to 3 V
- Buck converter output current: up to 1.5 A
- Thermal resistance RθJA: 30.3 °C/W (HTSSOP-56 DCA)
- ESD: ±2000 V HBM, ±500 V CDM
- Max output capacitance on shunt amplifier outputs: 20 pF
Features:
- Bootstrap gate driver with trickle charge, supporting 100% duty cycle
- 6 or 3 PWM input modes
- Dual integrated current shunt amplifiers with adjustable gain and offset
- 3.3 V and 5 V interface support
- Hardware control interface
- Programmable dead time control and programmable overcurrent protection (VDS sensing)
- PVDD and GVDD UVLO, GVDD OVLO, overtemperature warning/shutdown
- Fault reporting through nFAULT and nOCTW pins
- Integrated buck converter with adjustable output and switching frequency
Applications:
- 3-phase BLDC and PMSM motors
- CPAP and pumps
- E-bikes
- Power tools
- Robotics and RC toys
- Industrial automation
Package:
- HTSSOP (56), 14.00 mm × 6.10 mm (DCA)
DRV8302DCAR Features
- 1 · 8-V to 60-V Operating Supply Voltage Range
- 1.7-A Source and 2.3-A Sink Gate Drive Current Capability
- Bootstrap Gate Driver With 100% Duty Cycle Support
- 6 or 3 PWM Input Modes
- Dual Integrated Current Shunt Amplifiers With Adjustable Gain and Offset
- 3.3-V and 5-V Interface Support
- Hardware Control Interface
- Protection Features:
- -Programmable Dead Time Control (DTC)
- -Programmable Overcurrent Protection (OCP)
- -PVDD and GVDD Undervoltage Lockout (UVLO)
- -GVDD Overvoltage Lockout (OVLO)
- -Overtemperature Warning/Shutdown (OTW/OTS)
- -Reported through nFAULT and nOCTW pins
DRV8302DCAR Applications
- 3-Phase BLDC and PMSM Motors
- CPAP and Pumps
- E-Bikes
- Power Tools
- Robotics and RC Toys
- Industrial Automation
DRV8302DCAR Pin Configuration
Pin Functions
| PIN - NO. | PIN - NAME | I/O (1) | DESCRIPTION |
|---|---|---|---|
| 1 | RT_CLK | I | Resistor timing and external clock for buck regulator. Resistor should connect to GND (PowerPAD™) with very short trace to reduce the potential clock jitter due to noise. |
| 2 | COMP | O | Buck error amplifier output and input to the output switch current comparator. |
| 3 | VSENSE | I | Buck output voltage sense pin. Inverting node of error amplifier. |
| 4 | PWRGD | I | An open drain output with external pullup resistor required. Asserts low if buck output voltage is low due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut down |
| 5 | nOCTW | O | Overcurrent and overtemperature warning indicator. This output is open drain with external pullup resistor required. |
| 6 | nFAULT | O | Fault report indicator. This output is open drain with external pullup resistor required. |
| 7 | DTC | I | Dead-time adjustment with external resistor to GND |
| 8 | M_PWM | I | Mode selection pin for PWM input configuration. If M_PWM = LOW, the device supports 6 independent PWM inputs. When M_PWM = HIGH, the device must be connected to ONLY 3 PWM input signals on INH_x. The complementary PWM signals for low side signaling will be internally generated from the high side inputs. |
| 9 | M_OC | I | Mode selection pin for over-current protection options. If M_OC = LOW, the gate driver will operate in a cycle-by-cycle current limiting mode. If M_OC = HIGH, the gate driver will shutdown the channel which detected an over-current event. |
| 10 | GAIN | O | Gain selection for integrated current shunt amplifiers. If GAIN = LOW, the internal current shunt amplifiers have a gain of 10V/V. If GAIN = HIGH, the current shunt amplifiers have a gain of 40V/V. |
| 11 | OC_ADJ | I | Overcurrent trip set pin. Apply a voltage on this pin to set the trip point for the internal overcurrent protection circuitry. A voltage divider from DVDD is recommended. |
| 12 | DC_CAL | I | When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller. |
(1) KEY: I =Input, O = Output, P = Power
DRV8302DCAR Electrical Characteristics
PVDD = 8 V to 60 V, TC = 25°C, unless specified under test condition
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL | INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL | INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL | INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL | INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL | INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL | INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL |
| V IH | High input threshold | 2 | V | |||
| V IL | Low input threshold | 0.8 | V | |||
| R EN_GATE | Internal pulldown resistor for EN_GATE | 100 | k Ω | |||
| R INH_X | Internal pulldown resistor for high side PWMs (INH_A, INH_B, and INH_C) | EN_GATE high | 100 | k Ω | ||
| R INH_X | Internal pulldown resistor for low side PWMs (INL_A, INL_B, and INL_C) | EN_GATE high | 100 | k Ω | ||
| R M_PWM | Internal pulldown resistor for M_PWM | EN_GATE high | 100 | k Ω | ||
| R M_OC | Internal pulldown resistor for M_OC | EN_GATE high | 100 | k Ω | ||
| R DC_CAL | Internal pulldown resistor for DC_CAL | EN_GATE high | 100 | k Ω | ||
| OUTPUT PINS: nFAULT AND nOCTW | OUTPUT PINS: nFAULT AND nOCTW | OUTPUT PINS: nFAULT AND nOCTW | OUTPUT PINS: nFAULT AND nOCTW | OUTPUT PINS: nFAULT AND nOCTW | OUTPUT PINS: nFAULT AND nOCTW | OUTPUT PINS: nFAULT AND nOCTW |
| V OL | Low output threshold | I O = 2 mA | 0.4 | V | ||
| V OH | High output threshold | External 47-k Ω pullup resistor connected to 3-5.5 V | 2.4 | V | ||
| I OH | Leakage current on open-drain pins When logic high (nFAULT and nOCTW) | 1 | μA | |||
| GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C | GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C | GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C | GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C | GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C | GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C | GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C |
| V GX_NORM | Gate driver Vgs voltage | PVDD = 8 V to 60 V | 9.5 | 11.5 | V | |
| I oso1 | Maximum source current setting 1, peak | Vgs of FET equals to 2 V | 1.7 | A | ||
| I osi1 | Maximum sink current setting 1, peak | Vgs of FET equals to 8 V | 2.3 | A | ||
| R gate_off | Gate output impedance during standby mode when EN_GATE low (pins GH_x, GL_x) | 1.6 | 2.4 | k Ω | ||
| SUPPLY CURRENTS | SUPPLY CURRENTS | SUPPLY CURRENTS | SUPPLY CURRENTS | SUPPLY CURRENTS | SUPPLY CURRENTS | SUPPLY CURRENTS |
| I PVDD1_STB | PVDD1 supply current, standby | EN_GATE is low. PVDD1 = 8 V. | 20 | 50 | μA | |
| I PVDD1_OP | PVDD1 supply current, operating | EN_GATE is high, no load on gate drive output, switching at 10 kHz, 100-nC gate charge | 15 | mA | ||
| I PVDD1_HIZ | PVDD1 Supply current, HiZ | EN_GATE is high, gate not switching | 2 | 5 | 11 | mA |
| INTERNAL REGULATOR VOLTAGE | INTERNAL REGULATOR VOLTAGE | INTERNAL REGULATOR VOLTAGE | INTERNAL REGULATOR VOLTAGE | INTERNAL REGULATOR VOLTAGE | INTERNAL REGULATOR VOLTAGE | INTERNAL REGULATOR VOLTAGE |
| A VDD | AVDD voltage | 6 | 6.5 | 7 | V | |
| D VDD | DVDD voltage | 3 | 3.3 | 3.6 | V | |
| VOLTAGE PROTECTION | VOLTAGE PROTECTION | VOLTAGE PROTECTION | VOLTAGE PROTECTION | VOLTAGE PROTECTION | VOLTAGE PROTECTION | VOLTAGE PROTECTION |
| V PVDD_UV | Undervoltage protection limit, PVDD | 6 | V | |||
| V GVDD_UV | Undervoltage protection limit, GVDD | 8 | V | |||
| V GVDD_OV | Overvoltage protection limit, GVDD | 16 | V | |||
| CURRENT PROTECTION, (VDS SENSING) | CURRENT PROTECTION, (VDS SENSING) | CURRENT PROTECTION, (VDS SENSING) | CURRENT PROTECTION, (VDS SENSING) | CURRENT PROTECTION, (VDS SENSING) | CURRENT PROTECTION, (VDS SENSING) | CURRENT PROTECTION, (VDS SENSING) |
| V DS_OC | Drain-source voltage protection limit | 0.125 | 2.4 | V | ||
| T oc | OC sensing response time | 1.5 | μs | |||
| T OC_PULSE | OCTW pin reporting pulse stretch length for OC event | 64 | μs |
DRV8302DCAR Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| V PVDD | Supply voltage | Relative to PGND | -0.3 | 65 | V |
| PVDD RAMP | Maximum supply voltage ramp rate | Voltage rising up to PVDD MAX | 1 | V/μs | |
| V PGND | Maximum voltage between PGND and GND | Maximum voltage between PGND and GND | -0.3 | 0.3 | V |
| I IN_MAX | Maximum current, all digital and analog input pins except nFAULT and nOCTW pins | Maximum current, all digital and analog input pins except nFAULT and nOCTW pins | -1 | 1 | mA |
| I IN_OD_MAX | Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins) | Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins) | 7 | mA | |
| V OPA_IN | Voltage range for SPx and SNx pins | Voltage range for SPx and SNx pins | -0.6 | 0.6 | V |
| V LOGIC | Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, M_PWM, M_OC, OC_ADJ, GAIN, DC_CAL) | Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, M_PWM, M_OC, OC_ADJ, GAIN, DC_CAL) | -0.3 | 7 | V |
| V GVDD | Maximum voltage for GVDD pin | Maximum voltage for GVDD pin | 13.2 | V | |
| V AVDD | Maximum voltage for AVDD pin | Maximum voltage for AVDD pin | 8 | V | |
| V DVDD | Maximum voltage for DVDD pin | Maximum voltage for DVDD pin | 3.6 | V | |
| V REF | Maximum reference voltage for current amplifier | Maximum reference voltage for current amplifier | 7 | V | |
| I REF | Maximum current for REF Pin | Maximum current for REF Pin | 100 | μA | |
| T J | Maximum operating junction temperature | Maximum operating junction temperature | -40 | 150 | °C |
| T stg | Storage temperature | Storage temperature | -55 | 150 | °C |
DRV8302DCAR Recommended Operating Conditions
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| V PVDD | DC supply voltage PVDD1 for normal operation Relative to PGND | DC supply voltage PVDD1 for normal operation Relative to PGND | 8 | 60 | V |
| V PVDD | DC supply voltage PVDD2 for buck converter | DC supply voltage PVDD2 for buck converter | 3.5 | 60 | V |
| I DIN_EN | Input current of digital pins when EN_GATE is high | Input current of digital pins when EN_GATE is high | 100 | μA | |
| I DIN_DIS | Input current of digital pins when EN_GATE is low | Input current of digital pins when EN_GATE is low | 1 | μA | |
| C O_OPA | Maximum output capacitance on outputs of shunt amplifier | Maximum output capacitance on outputs of shunt amplifier | 20 | pF | |
| R DTC | Dead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 k Ω ) with a linear approximation. | Dead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 k Ω ) with a linear approximation. | 0 | 150 | k Ω |
| I FAULT | FAULT pin sink current. Open drain | V = 0.4 V | 2 | mA | |
| I OCTW | OCTW pin sink current. Open drain | V = 0.4 V | 2 | mA | |
| V REF | External voltage reference voltage for current shunt amplifiers | External voltage reference voltage for current shunt amplifiers | 2 | 6 | V |
| f gate | Operating switching frequency of gate driver | Qg(TOT) = 25 nC or total 30-mA gate drive average current | 200 | kHz | |
| T A | Ambient temperature | Ambient temperature | -40 | 125 | °C |
DRV8302DCAR Thermal Information
| THERMAL METRIC (1) | THERMAL METRIC (1) | DRV8302 DCA (HTSSOP) 56 PINS | UNIT |
|---|---|---|---|
| R θ JA | Junction-to-ambient thermal resistance | 30.3 | °C/W |
| R θ JC(top) | Junction-to-case (top) thermal resistance | 33.5 | °C/W |
| R θ JB | Junction-to-board thermal resistance | 17.5 | °C/W |
| ψ JT | Junction-to-top characterization parameter | 0.9 | °C/W |
| ψ JB | Junction-to-board characterization parameter | 7.2 | °C/W |
| R θ JC(bot) | Junction-to-case (bottom) thermal resistance | 0.9 | °C/W |
DRV8302DCAR Typical Application
The DRV8302 is a gate driver designed to drive a 3-phase BLDC motor in combination with external power MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, two current shunt amplifiers, overcurrent protection, and a step-down buck regulator.
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| DRV8302 | Texas Instruments | HTSSOP-56 |
| DRV8302DCA | Texas Instruments | HTSSOP-56 |
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