DRV8302

Three-Phase Gate Driver with Dual Shunt Amplifiers and Buck Regulator

The DRV8302 is a three-phase gate driver with dual shunt amplifiers and buck regulator from Texas Instruments. View the full DRV8302 datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

Texas Instruments

Overview

Part: DRV8302 — Texas Instruments

Type: Three-Phase Gate Driver with Dual Shunt Amplifiers and Buck Regulator - Hardware Control

Description: The DRV8302 is a gate driver IC for three-phase motor drive applications, providing three half-bridge drivers capable of driving N-channel MOSFETs with up to 1.7A source and 2.3A peak sink current. It operates from an 8V to 60V supply, features two integrated shunt amplifiers for current measurement, and includes a switching mode buck converter capable of providing up to 1.5A.

Operating Conditions:

Supply voltage: 8–60 V (PVDD1), 3.5–60 V (PVDD2 for buck)
Operating temperature: -40 to 125 °C
Gate driver switching frequency: up to 200 kHz (Qg(TOT) = 25 nC or total 30-mA gate drive average current)
External voltage reference for current shunt amplifiers: 2–6 V

Absolute Maximum Ratings:

Max supply voltage: 65 V (V_PVDD relative to PGND)
Max junction temperature: 150 °C
Max storage temperature: 150 °C

Key Specs:

Gate drive source current: 1.7 A (peak)
Gate drive sink current: 2.3 A (peak)
Shunt amplifier gain: 10 V/V or 40 V/V (selectable)
Shunt amplifier output offset: up to 3 V (adjustable)
Buck converter output current: 1.5 A (max)
Buck converter output voltage: 1.2 V to 5.5 V (adjustable)
DVDD output voltage: 3.3 V (typical)
AVDD output voltage: 6 V (typical)

Features:

Bootstrap Gate Driver Supports 100% Duty Cycle
6 or 3 Pulse-Width Modulation (PWM) Input Modes
Two Integrated Shunt Amplifiers with Adjustable Gain and Offset
Supports 3.3V and 5V Interfaces
Hardware Control Interface
Protection Features: Programmable Dead Time Control (DTC), Programmable Overcurrent Protection (OCP), PVDD and GVDD Undervoltage Lockout (UVLO), GVDD Overvoltage Lockout (OVLO), Overtemperature Warning / Shutdown (OTW/OTS)

Applications:

Three-Phase Brushless DC (BLDC) Motors and Permanent Magnet Synchronous Motors (PMSM)
Continuous Positive Airway Pressure (CPAP) and Pumps
E-Bikes
Power Tools
Robotics and Remote Control (RC) Toys
Industrial Automation

Package:

HTSSOP (56) - 14.00mm x 6.10mm

Features

1. 8V to 60V Operating Supply Voltage Range
Gate Drive up to 1.7A Source and 2.3A Sink Current
Bootstrap Gate Driver Supports 100% Duty Cycle
6 or 3 Pulse-Width Modulation (PWM) Input Modes
Two Integrated Shunt Amplifiers with Adjustable Gain and Offset
Supports 3.3V and 5V Interfaces
Hardware Control Interface
Protection Features:
- Programmable Dead Time Control (DTC)
- Programmable Overcurrent Protection (OCP)
- PVDD and GVDD Undervoltage Lockout (UVLO)
- GVDD Overvoltage Lockout (OVLO)
- Overtemperature Warning / Shutdown (OTW/OTS)
- Reported via nFAULT and nOCTW Pins

Applications

Three-Phase Brushless DC (BLDC) Motors and Permanent Magnet Synchronous Motors (PMSM)
Continuous Positive Airway Pressure (CPAP) and Pumps
E-Bikes
Power Tools
Robotics and Remote Control (RC) Toys
Industrial Automation

Pin Configuration

Pin Functions

Pin Functions

PIN	PIN	I/O (1)	DESCRIPTION
NO.	NAME	I/O (1)	DESCRIPTION
1	RT_CLK	I	Resistor timing and external clock for buck regulator. Resistor should connect to GND (PowerPAD™) with very short trace to reduce the potential clock jitter due to noise.
2	COMP	O	Buck error amplifier output and input to the output switch current comparator.
3	VSENSE	I	Buck output voltage sense pin. Inverting node of error amplifier.
4	PWRGD	I	An open drain output with external pullup resistor required. Asserts low if buck output voltage is low due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut down
5	nOCTW	O	Overcurrent and overtemperature warning indicator. This output is open drain with external pullup resistor required.
6	nFAULT	O	Fault report indicator. This output is open drain with external pullup resistor required.
7	DTC	I	Dead-time adjustment with external resistor to GND
8	M_PWM	I	Mode selection pin for PWM input configuration. If M_PWM = LOW, the device supports 6 independent PWM inputs. When M_PWM = HIGH, the device must be connected to ONLY 3 PWM input signals on INH_x. The complementary PWM signals for low side signaling will be internally generated from the high side inputs.
9	M_OC	I	Mode selection pin for over-current protection options. If M_OC = LOW, the gate driver will operate in a cycle-by-cycle current limiting mode. If M_OC = HIGH, the gate driver will shutdown the channel which detected an over-current event.
10	GAIN	O	Gain selection for integrated current shunt amplifiers. If GAIN = LOW, the internal current shunt amplifiers have a gain of 10V/V. If GAIN = HIGH, the current shunt amplifiers have a gain of 40V/V.
11	OC_ADJ	I	Overcurrent trip set pin. Apply a voltage on this pin to set the trip point for the internal overcurrent protection circuitry. A voltage divider from DVDD is recommended.
12	DC_CAL	I	When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller.

Electrical Characteristics

PVDD = 8 V to 60 V, TC = 25°C, unless specified under test condition

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL
V IH	High input threshold		2			V
V IL	Low input threshold				0.8	V
R EN_GATE	Internal pulldown resistor for EN_GATE			100		k Ω
R INH_X	Internal pulldown resistor for high side PWMs (INH_A, INH_B, and INH_C)	EN_GATE high		100		k Ω
R INH_X	Internal pulldown resistor for low side PWMs (INL_A, INL_B, and INL_C)	EN_GATE high		100		k Ω
R M_PWM	Internal pulldown resistor for M_PWM	EN_GATE high		100		k Ω
R M_OC	Internal pulldown resistor for M_OC	EN_GATE high		100		k Ω
R DC_CAL	Internal pulldown resistor for DC_CAL	EN_GATE high		100		k Ω
OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW
V OL	Low output threshold	I O = 2 mA			0.4	V
V OH	High output threshold	External 47-k Ω pullup resistor connected to 3-5.5 V	2.4			V
I OH	Leakage current on open-drain pins When logic high (nFAULT and nOCTW)				1	μA
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
V GX_NORM	Gate driver Vgs voltage	PVDD = 8 V to 60 V	9.5		11.5	V
I oso1	Maximum source current setting 1, peak	Vgs of FET equals to 2 V		1.7		A
I osi1	Maximum sink current setting 1, peak	Vgs of FET equals to 8 V		2.3		A
R gate_off	Gate output impedance during standby mode when EN_GATE low (pins GH_x, GL_x)		1.6		2.4	k Ω
SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS
I PVDD1_STB	PVDD1 supply current, standby	EN_GATE is low. PVDD1 = 8 V.		20	50	μA
I PVDD1_OP	PVDD1 supply current, operating	EN_GATE is high, no load on gate drive output, switching at 10 kHz, 100-nC gate charge		15		mA
I PVDD1_HIZ	PVDD1 Supply current, HiZ	EN_GATE is high, gate not switching	2	5	11	mA
INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE
A VDD	AVDD voltage		6	6.5	7	V
D VDD	DVDD voltage		3	3.3	3.6	V
VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION
V PVDD_UV	Undervoltage protection limit, PVDD				6	V
V GVDD_UV	Undervoltage protection limit, GVDD				8	V
V GVDD_OV	Overvoltage protection limit, GVDD			16		V
CURRENT PROTECTION, (VDS SENSING)	CURRENT PROTECTION, (VDS SENSING)	CURRENT PROTECTION, (VDS SENSING)	CURRENT PROTECTION, (VDS SENSING)	CURRENT PROTECTION, (VDS SENSING)	CURRENT PROTECTION, (VDS SENSING)	CURRENT PROTECTION, (VDS SENSING)
V DS_OC	Drain-source voltage protection limit		0.125		2.4	V
T oc	OC sensing response time			1.5		μs
T OC_PULSE	OCTW pin reporting pulse stretch length for OC event			64		μs

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

			MIN	MAX	UNIT
V PVDD	Supply voltage	Relative to PGND	-0.3	65	V
PVDD RAMP	Maximum supply voltage ramp rate	Voltage rising up to PVDD MAX		1	V/μs
V PGND	Maximum voltage between PGND and GND	Maximum voltage between PGND and GND	-0.3	0.3	V
I IN_MAX	Maximum current, all digital and analog input pins except nFAULT and nOCTW pins	Maximum current, all digital and analog input pins except nFAULT and nOCTW pins	-1	1	mA
I IN_OD_MAX	Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins)	Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins)		7	mA
V OPA_IN	Voltage range for SPx and SNx pins	Voltage range for SPx and SNx pins	-0.6	0.6	V
V LOGIC	Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, M_PWM, M_OC, OC_ADJ, GAIN, DC_CAL)	Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, M_PWM, M_OC, OC_ADJ, GAIN, DC_CAL)	-0.3	7	V
V GVDD	Maximum voltage for GVDD pin	Maximum voltage for GVDD pin		13.2	V
V AVDD	Maximum voltage for AVDD pin	Maximum voltage for AVDD pin		8	V
V DVDD	Maximum voltage for DVDD pin	Maximum voltage for DVDD pin		3.6	V
V REF	Maximum reference voltage for current amplifier	Maximum reference voltage for current amplifier		7	V
I REF	Maximum current for REF Pin	Maximum current for REF Pin		100	μA
T J	Maximum operating junction temperature	Maximum operating junction temperature	-40	150	°C
T stg	Storage temperature	Storage temperature	-55	150	°C

Recommended Operating Conditions

			MIN	MAX	UNIT
V PVDD	DC supply voltage PVDD1 for normal operation Relative to PGND	DC supply voltage PVDD1 for normal operation Relative to PGND	8	60	V
V PVDD	DC supply voltage PVDD2 for buck converter	DC supply voltage PVDD2 for buck converter	3.5	60	V
I DIN_EN	Input current of digital pins when EN_GATE is high	Input current of digital pins when EN_GATE is high		100	μA
I DIN_DIS	Input current of digital pins when EN_GATE is low	Input current of digital pins when EN_GATE is low		1	μA
C O_OPA	Maximum output capacitance on outputs of shunt amplifier	Maximum output capacitance on outputs of shunt amplifier		20	pF
R DTC	Dead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 k Ω ) with a linear approximation.	Dead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 k Ω ) with a linear approximation.	0	150	k Ω
I FAULT	FAULT pin sink current. Open drain	V = 0.4 V		2	mA
I OCTW	OCTW pin sink current. Open drain	V = 0.4 V		2	mA
V REF	External voltage reference voltage for current shunt amplifiers	External voltage reference voltage for current shunt amplifiers	2	6	V
f gate	Operating switching frequency of gate driver	Qg(TOT) = 25 nC or total 30-mA gate drive average current		200	kHz
T A	Ambient temperature	Ambient temperature	-40	125	°C

Thermal Information

THERMAL METRIC (1)	THERMAL METRIC (1)	DRV8302 DCA (HTSSOP) 56 PINS	UNIT
R θ JA	Junction-to-ambient thermal resistance	30.3	°C/W
R θ JC(top)	Junction-to-case (top) thermal resistance	33.5	°C/W
R θ JB	Junction-to-board thermal resistance	17.5	°C/W
ψ JT	Junction-to-top characterization parameter	0.9	°C/W
ψ JB	Junction-to-board characterization parameter	7.2	°C/W
R θ JC(bot)	Junction-to-case (bottom) thermal resistance	0.9	°C/W

Typical Application

The DRV8302 is a gate driver designed to drive a 3-phase BLDC motor in combination with external power MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, two current shunt amplifiers, overcurrent protection, and a step-down buck regulator.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
DRV8302DCA	Texas Instruments	—
DRV8302DCAR	Texas Instruments	HTSSOP-56

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