DRV8301DCARG4

Three-Phase Gate Driver With Dual Current Shunt Amplifiers and Buck Regulator

The DRV8301DCARG4 is a three-phase gate driver with dual current shunt amplifiers and buck regulator from Texas Instruments. View the full DRV8301DCARG4 datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

Manufacturer

Texas Instruments

Key Specifications

Parameter	Value
Packaging	Reel
Standard Pack Qty	2000

Overview

Part: DRV8301, Texas Instruments

Type: Three-Phase Gate Driver with Dual Current Shunt Amplifiers and Buck Regulator

Description: The DRV8301 is a 6–60 V three-phase gate driver IC with 1.7-A source and 2.3-A sink gate drive capability, dual integrated current shunt amplifiers, and an integrated 1.5-A buck converter.

Operating Conditions:

Supply voltage: 6–60 V
Gate drive source current: 1.7 A
Gate drive sink current: 2.3 A
Buck converter output current: 1.5 A

Absolute Maximum Ratings:

Max supply voltage (V PVDD): 65 V
Max current for digital and analog inputs: 1 mA
Max sinking current for open-drain pins (nFAULT, nOCTW): 7 mA

Key Specs:

Operating supply voltage range: 6 V to 60 V
Gate drive current capability: 1.7-A source, 2.3-A sink
Integrated buck converter output current: 1.5 A
Current shunt amplifiers: Dual, with adjustable gain and offset
PWM input modes: 6- or 3-PWM
Bootstrap gate driver: With 100% duty cycle support
Interface support: 3.3-V and 5-V logic, SPI
Protection features: Programmable Dead Time Control (DTC), Programmable Overcurrent Protection (OCP), PVDD and GVDD Undervoltage Lockout (UVLO), GVDD Overvoltage Lockout (OVLO), Overtemperature Warning/Shutdown (OTW/OTS)

Features:

6-V to 60-V Operating Supply Voltage Range
1.7-A Source and 2.3-A Sink Gate Drive Current Capability
Slew Rate Control for EMI Reduction
Bootstrap Gate Driver With 100% Duty Cycle Support
6- or 3-PWM Input Modes
Dual Integrated Current Shunt Amplifiers With Adjustable Gain and Offset
Integrated 1.5-A Buck Converter
3.3-V and 5-V Interface Support
SPI
Protection Features: Programmable Dead Time Control (DTC), Programmable Overcurrent Protection (OCP), PVDD and GVDD Undervoltage Lockout (UVLO), GVDD Overvoltage Lockout (OVLO), Overtemperature Warning/Shutdown (OTW/OTS), Reported Through nFAULT, nOCTW, and SPI Registers

Applications:

3-Phase BLDC and PMSM Motors
CPAPs and Pumps
E-bikes
Power Tools
Robotics and RC Toys
Industrial Automation

Package:

HTSSOP (56)

Features

1 · 6-V to 60-V Operating Supply Voltage Range
1.7-A Source and 2.3-A Sink Gate Drive Current Capability
Slew Rate Control for EMI Reduction
Bootstrap Gate Driver With 100% Duty Cycle Support
6- or 3-PWM Input Modes
Dual Integrated Current Shunt Amplifiers With Adjustable Gain and Offset
Integrated 1.5-A Buck Converter
3.3-V and 5-V Interface Support
SPI
Protection Features:
-Programmable Dead Time Control (DTC)
-Programmable Overcurrent Protection (OCP)
-PVDD and GVDD Undervoltage Lockout (UVLO)
-GVDD Overvoltage Lockout (OVLO)
-Overtemperature Warning/Shutdown (OTW/OTS)
-Reported Through nFAULT, nOCTW, and SPI Registers

Applications

3-Phase BLDC and PMSM Motors
CPAPs and Pumps
E-bikes
Power Tools
Robotics and RC Toys
Industrial Automation

Pin Configuration

Electrical Characteristics

PVDD = 6 to 60 V, TC = 25°C, unless specified under test condition

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL	INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL
V IH	High input threshold		2			V
V IL	Low input threshold				0.8	V
RPULL_DOWN - INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS	RPULL_DOWN - INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS	RPULL_DOWN - INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS	RPULL_DOWN - INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS	RPULL_DOWN - INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS	RPULL_DOWN - INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS	RPULL_DOWN - INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS
R EN_GATE	Internal pulldown resistor for EN_GATE			100		k Ω
R INH_X	Internal pulldown resistor for high-side PWMs (INH_A, INH_B, and INH_C)	EN_GATE high		100		k Ω
R INH_X	Internal pulldown resistor for low-side PWMs (INL_A, INL_B, and INL_C)	EN_GATE high		100		k Ω
R nSCS	Internal pulldown resistor for nSCS	EN_GATE high		100		k Ω
R SDI	Internal pulldown resistor for SDI	EN_GATE high		100		k Ω
R DC_CAL	Internal pulldown resistor for DC_CAL	EN_GATE high		100		k Ω
R SCLK	Internal pulldown resistor for SCLK	EN_GATE high		100		k Ω
OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW	OUTPUT PINS: nFAULT AND nOCTW
V OL	Low output threshold	I O = 2 mA			0.4	V
V OH	High output threshold	External 47 k Ω pullup resistor connected to 3-5.5 V	2.4			V
I OH	Leakage Current on Open-Drain Pins When Logic High nFAULT and nOCTW)				1	μA
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C	GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
V GX_NORM	Gate driver Vgs voltage	PVDD = 8 to 60 V, I gate = 30 mA, C CP = 22 nF PVDD = 8 to 60 V, I gate = 30 mA,	9.5		11.5 11.5	V
V GX_MIN	Gate driver Vgs voltage	PVDD = 6 to 8 V, I gate = 15 mA, C CP = 22 nF PVDD = 6 to 8 V, I gate = 30 mA,	8.8			V
I	Maximum source current setting 1, peak	C CP = 220 nF	8.3			A
oso1 I	Maximum sink current setting 1, peak	Vgs of FET equals to 2 V. REG 0x02 Vgs of FET equals to 8 V. REG 0x02		1.7 2.3		A
osi1 I oso2	Source current setting 2, peak	Vgs of FET equals to 2 V. REG 0x02		0.7		A
I osi2	Sink current setting 2, peak	Vgs of FET equals to 8 V. REG 0x02		1		A
I oso3	Source current setting 3, peak	Vgs of FET equals to 2 V. REG 0x02		0.25		A
I osi3	Sink current setting 3, peak	Vgs of FET equals to 8 V. REG 0x02		0.5		A
R gate_off	Gate output impedence during standby mode when EN_GATE low (pins GH_x, GL_x)		1.6		2.4	k Ω
SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS	SUPPLY CURRENTS
I PVDD1_STB	PVDD1 supply current, standby	EN_GATE is low. PVDD1 = 8 V.		20	50	μA
I PVDD1_OP	PVDD1 supply current, operating	EN_GATE is high, no load on gate drive output, switching at 10 kHz, 100 nC gate charge		15		mA
I PVDD1_HIZ	PVDD1 Supply current, Hi-Z	EN_GATE is high, gate not switching	2	5	10	mA
INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE	INTERNAL REGULATOR VOLTAGE
A	AVDD voltage	PVDD = 8 to 60 V	6	6.5	7
VDD		PVDD = 6 to 60 V	5.5		6	V
D VDD	DVDD voltage		3	3.3	3.6	V
VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION	VOLTAGE PROTECTION
V	Undervoltage protection limit, PVDD	PVDD falling			5.9
PVDD_UV		PVDD rising			6	V
V GVDD_UV	Undervoltage protection limit, GVDD	GVDD falling			8	V

Absolute Maximum Ratings

see (1)

			MIN	MAX	UNIT
V PVDD	Supply voltage	Relative to PGND	-0.3	65	V
	Maximum supply voltage ramp rate	Voltage rising up to PVDD MAX		1	V/μS
V PGND	Maximum voltage between PGND and GND	Maximum voltage between PGND and GND	-0.3	0.3	V
I IN_MAX	Maximum current for all digital and analog inputs (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, SCLK, SCS, SDI, EN_GATE, DC_CAL, DTC)	Maximum current for all digital and analog inputs (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, SCLK, SCS, SDI, EN_GATE, DC_CAL, DTC)	-1	1	mA
I SINK_MAX	Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins)	Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins)		7	mA
V OPA_IN	Voltage for SPx and SNx pins	Voltage for SPx and SNx pins	-0.6	0.6	V
V LOGIC	Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)	Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)	-0.3	7	V
V GVDD	Maximum voltage for GVDD pin	Maximum voltage for GVDD pin		13.2	V
V AVDD	Maximum voltage for AVDD pin	Maximum voltage for AVDD pin		8	V
V DVDD	Maximum voltage for DVDD pin	Maximum voltage for DVDD pin		3.6	V
V VDD_SPI	Maximum voltage for VDD_SPI pin	Maximum voltage for VDD_SPI pin		7	V
V SDO	Maximum voltage for SDO pin	Maximum voltage for SDO pin		VDD_SPI + 0.3	V
V REF	Maximum reference voltage for current amplifier	Maximum reference voltage for current amplifier		7	V
I REF	Maximum current for REF pin	Maximum current for REF pin		100	μA
T J	Maximum operating junction temperature	Maximum operating junction temperature	-40	150	°C
T stg	Storage temperature	Storage temperature	-55	150	°C

Recommended Operating Conditions

			MIN	MAX	UNIT
V PVDD1	DC supply voltage PVDD1 for normal operation	Relative to PGND	6	60	V
V PVDD2	DC supply voltage PVDD2 for buck converter	DC supply voltage PVDD2 for buck converter	3.5	60	V
I DIN_EN	Input current of digital pins when EN_GATE is high	Input current of digital pins when EN_GATE is high		100	μA
I DIN_DIS	Input current of digital pins when EN_GATE is low	Input current of digital pins when EN_GATE is low		1	μA
C O_OPA	Maximum output capacitance on outputs of shunt amplifier	Maximum output capacitance on outputs of shunt amplifier		20	pF
R DTC	Dead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 k Ω ) with a linear approximation.	Dead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 k Ω ) with a linear approximation.	0	150	k Ω
I FAULT	nFAULT pin sink current, open-drain	V = 0.4 V		2	mA
I OCTW	nFAULT pin sink current, open-drain	V = 0.4 V		2	mA
V REF	External voltage reference voltage for current shunt amplifiers	External voltage reference voltage for current shunt amplifiers	2	6	V
ƒ gate	Operating switching frequency of gate driver	Q g(TOT) = 25 nC or total 30-mA gate drive average current		200	kHz
I gate	Total average gate drive current	Total average gate drive current		30	mA
T A	Ambient temperature	Ambient temperature	-40	125	°C

Thermal Information

THERMAL METRIC (1)		DRV8301 DCA (HTSSOP) 56 PINS	UNIT
R θ JA	Junction-to-ambient thermal resistance	30.3	°C/W
R θ JC(top)	Junction-to-case (top) thermal resistance	33.5	°C/W
R θ JB	Junction-to-board thermal resistance	17.5	°C/W
ψ JT	Junction-to-top characterization parameter	0.9	°C/W
ψ JB	Junction-to-board characterization parameter	7.2	°C/W
R θ JC(bot)	Junction-to-case (bottom) thermal resistance	0.9	°C/W

Typical Application

The DRV8301 is a gate driver designed to drive a 3-phase BLDC motor in combination with external power MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, two current shunt amplifiers, and overcurrent protection.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
DRV8301	Texas Instruments	HTSSOP-56
DRV8301-Q1	Texas Instruments	—
DRV8301DCA	Texas Instruments	—
DRV8301DCA.A	Texas Instruments	—
DRV8301DCAR	Texas Instruments	—
DRV8301DCAR.A	Texas Instruments	—

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