DA14531

Part: DA14531

Type: Ultra-low power Bluetooth 5.1 SoC

Description: Ultra-low power SoC integrating a 2.4 GHz transceiver and an Arm Cortex-M0+ microcontroller with 48 kB RAM, 32 kB OTP, and 144 kB ROM, compliant with Bluetooth Low Energy 5.1.

Operating Conditions:

• Supply voltage: 1.1–3.6 V
• Max clock: 16 MHz

Key Specs:

• CPU: 16 MHz 32-bit Arm Cortex-M0+
• RAM: 48 kB Retainable System RAM
• OTP: 32 kB One-Time-Programmable (OTP)
• ROM: 144 kB ROM
• Bluetooth Standard: v5.1
• TX current: 3.5 mA (system currents with DC-DC, VBAT_HIGH = 3 V and 0 dBm)
• RX current: 2.2 mA (system currents with DC-DC, VBAT_HIGH = 3 V and 0 dBm)
• Receiver sensitivity: -94 dBm
• Transmit output power: -19.5 dBm to +2.5 dBm
• Hibernation mode current: Buck 270 nA, Boost 240 nA

Features:

• Compatible with Bluetooth v5.1, ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan)
• Supports up to three Bluetooth LE connections
• Dedicated Link Layer and AES-128 Encryption Processor
• Software-based True Random Number Generator (TRNG)
• Integrated Buck/Boost DCDC converter
• Built-in temperature sensor for die temperature monitoring
• 2× General purpose Timers with capture and PWM capabilities
• 2× UARTs (one with flow control)
• SPI Master/Slave up to 32 MHz (Master)
• I2C bus at 100 kHz and 400 kHz
• 3-axis capable Quadrature Decoder
• Keyboard controller
• 4-channel 10-bit ADC
• Single wire antenna

Applications:

• Medical applications
• Disposables
• Beacons
• Proximity tags and trackers
• Wireless sensor nodes
• Fitness trackers
• Consumer health
• Smartwatches
• Human interface devices (HID)
• Stylus pens
• Keyboards
• Mouse devices
• Trackpads
• Toys
• Industrial appliances

Package:

• WLCSP 17 balls, 1.7 × 2.05, 0.5 mm pitch
• FCGQFN 24 pins, 2.2 × 3, 0.4 mm pitch

• ■ Compatible with Bluetooth ® v5.1, ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan) ■

• ■ Supports up to three Bluetooth ® LE connections

• ■ Typical cold boot to radio active 35 ms

• ■ Processing power

• □ 16 MHz 32-bit Arm ® Cortex-M0+ with SWD interface

• □ 18300 EEMBC IoTMark-BLE ® score

• □ Dedicated Link Layer and AES-128 Encryption Processor

• □ Software-based True Random Number Generator (TRNG)

• ■ Memories

• □ 32 kB One-Time-Programmable (OTP)

• □ 48 kB Retainable System RAM

• □ 144 kB ROM

• ■ Power management

• □ Integrated Buck/Boost DCDC converter

• □ Buck: 1.8 V ≤ VBAT_HIGH ≤ 3.6 V

• □ Boost: 1.1 V ≤ VBAT_LOW ≤ 1.65 V

• □ Clock-less hibernation mode: Buck 270 nA, Boost 240 nA

• □ Built-in temperature sensor for die temperature monitoring

• ■ Medical applications
• ■ Disposables
• ■ Beacons
• ■ Proximity tags and trackers
• ■ Wireless sensor nodes
• □ Fitness trackers
• □ Consumer health
• ■ Smartwatches
• ■ Human interface devices (HID)
• □ Stylus pens
• □ Keyboards
• □ Mouse devices
• □ Trackpads
• ■ Toys
• ■ Industrial appliances

The Programmable Pin Assignment (PPA) provides a multiplexing function to the I/O pins of on-chip peripherals. Any peripheral input or output signal can be freely mapped to any I/O port bit by setting Pxy_MODE_REG[4-0]:

0x00 to 0x1F: Peripheral IO ID (PID)

Refer to the registers of Px_MODE_REG (x = 00, 01, 02, to 11) for an overview of the available PIDs. The analog ADC has a fixed pin assignment so that the interference with the digital domain is limited. The SWD interface (JTAG) is mapped on P0_5 (or P0_1 or P0_10, see chapter 2 Pinout) for the SWDIO and on P0_2 for the SWCLK.

Datasheet

Revision 3.5

04-Mar-2022

Final

Final

Note 1

IBAT_HIGH is Buck configuration at VBAT = 3 V, at 25 °C

Note 2 IBAT_LOW is Boost configuration at VBAT = 1.5 V, at 25 °C

Final

Final

Final

Figure 85: WLCSP17 Package Outline Drawing

Revision 3.5

Datasheet

Final

Figure 86: FCGQFN24 Package Outline Drawing

Revision 3.5

Final