CYW43455XKUBGT

Part: CYW43455 — Cypress (an Infineon Technologies Company)

Type: Single-chip Wi-Fi 802.11ac and Bluetooth 5.0 combo device

Description: Single-stream IEEE 802.11a/b/g/n/ac (up to 433.3 Mbps) and Bluetooth 5.0 + EDR combo with an integrated MAC/baseband/radio, an ARM Cortex-R4 (ARMCR4) processor, and on-chip PMU, in a 140-ball WLBGA package.

Operating Conditions:

• VBAT supply: 3.0–5.25 V (Table 28 also lists a 6.0 V maximum)
• VDDIO: 1.62–3.63 V
• Core (VDD) and RF (VDDRF) supplies: 1.14–1.26 V (1.2 V typ.)
• WRF_TCXO_VDD: 1.62–1.98 V
• VDDIO_RF: 3.13–3.46 V

Absolute Maximum Ratings:

• VBAT: -0.5 to +6.0 V
• VDDIO: -0.5 to 3.9 V
• VDDIO_RF: -0.5 to 3.9 V
• VDDRF and VDDC: -0.5 to 1.32 V
• CLDO/LNLDO input supply: -0.5 to 1.575 V
• WRF_TCXO_VDD: -0.5 to 3.63 V
• I/O overshoot: VDDIO + 0.5 V (undershoot -0.5 V)
• Max junction temperature: 125 °C

Key Specs:

• Digital I/O at VDDIO = 1.8 V: VIH min 0.65 × VDDIO, VIL max 0.35 × VDDIO, VOH min VDDIO - 0.45 V and VOL max 0.45 V at 2 mA
• Digital I/O at VDDIO = 3.3 V: VIH min 2.00 V, VIL max 0.80 V, VOH min VDDIO - 0.4 V and VOL max 0.40 V at 2 mA
• RF switch control outputs at VDDIO_RF = 3.3 V: VOH min VDDIO - 0.4 V and VOL max 0.40 V at 2 mA; output capacitance max 5 pF
• External TSSI input: 0.15–0.95 V
• Internal POR threshold: 0.4–0.7 V
• Integrated PMU regulators: CBUCK 1.35 V (170 mA nominal, 600 mA max), LDO3P3 (200 mA nominal), BTLDO2P5 (15 mA nominal), LNLDO 1.2 V (100 mA nominal), CLDO 1.2 V (80 mA nominal)
• On-chip memory: 800 KB SRAM and 704 KB ROM
• GPIOs: 15

Features:

• IEEE 802.11ac with MCS0–MCS9 (256 QAM) on 20/40/80 MHz channels, TurboQAM, LDPC and explicit transmit beamforming
• Full 802.11a/b/g/n legacy compatibility
• On-chip 2.4 GHz and 5 GHz PAs and LNAs, with support for optional external FEMs
• Single dual-band antenna shared between Bluetooth and WLAN
• SDIO v3.0 host interface (DDR50 and SDR104), backward compatible with SDIO v2.0
• PCIe Gen1 ×1 interface (not brought up and not supported by Cypress firmware and drivers)
• Bluetooth 5.0 (Class 1 or 2) with eSCO, AFH, A2DP, high-speed HCI UART and PCM audio
• IEEE 802.15.2 external coexistence interface (e.g. LTE, GPS)
• Hardware AES and TKIP; WPA/WPA2 Personal
• 6 Kbit OTP
• Internal switching regulator and LDOs for direct battery operation

Applications:

• IoT devices
• Handheld and mobile wireless systems

Package:

• 140-ball WLBGA (4.47 mm × 5.27 mm, 0.4 mm pitch)

• ■ IEEE 802.11ac compliant.
• ■ Support for TurboQAM ® (MCS0-MCS8 86 Mbps and MCS0MCS9 96 Mbps) HT20, 20 MHz channel bandwidth.
• ■ Single-stream spatial multiplexing up to 433.3 Mbps data rate.
• ■ Supports 20, 40, and 80 MHz channels with optional SGI (256 QAM modulation).
• ■ Full IEEE 802.11a/b/g/n legacy compatibility with enhanced performance.
• ■ Supports explicit IEEE 802.11ac transmit beamforming.
• ■ TX and RX low-density parity check (LDPC) support for improved range and power efficiency.
• ■ On-chip power amplifiers and low-noise amplifiers for both bands.
• ■ Support for optional front-end modules (FEM) with external PAs and LNAs.
• ■ Supports optional integrated T/R switch for 2.4 GHz band.
• ■ Supports RF front-end architecture with a single dual-band antenna shared between Bluetooth and WLAN for lowest system cost.
• ■ Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN.
• ■ Internal fractional-n PLL allows support for a wide range of reference clock frequencies.
• ■ Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as LTE or GPS.

1. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

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• ■ Supports standard SDIO v3.0 (including DDR50 mode at 50 MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit) interfaces.
• ■ Backward compatible with SDIO v2.0 host interfaces.
• ■ PCIe 2 mode complies with PCI Express base specification revision 3.0 compliant Gen1 interface for ×1 lane and power management base specification.
• ■ Integrated ARMCR4 processor with tightly coupled memory for complete WLAN subsystem functionality and minimizing the need to wake-up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. On-chip memory includes 800KB SRAM and 704 KB ROM.

Figure 22. Signal Connections to SDIO Host (SD 4-Bit Mode)

Figure 23. Signal Connections to SDIO Host (SD 1-Bit Mode)

Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper programming of the SDIO host's internal pull-ups.

Figure 23. Signal Connections to SDIO Host (SD 1-Bit Mode)

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Caution! The absolute maximum ratings in Table 25 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Table 25. Absolute Maximum Ratings

Caution! Functional operation is not guaranteed outside of the limits shown in Table 28. Operation outside these limits for extended periods can adversely affect long-term reliability of the device.

Note: For DC absolute maximum rating (AMR), see Table 25.

Table 28. Recommended Operating Conditions and DC Characteristics