CYW43455XKUBGT

Part: Cypress CYW43455

Type: WLAN + Bluetooth Combo Chip

Description: Single-chip device integrating IEEE 802.11ac MAC/baseband/radio and Bluetooth 5.0, supporting WLAN data rates up to 433.3 Mbps with a 3.0 V to 5.25 V battery supply.

Operating Conditions:

• Supply voltage: 3.0 V to 5.25 V (VBAT), 1.8 V to 3.3 V (VIO)
• Operating temperature: -40 to +85 °C (Ambient)
• WLAN data rate: Up to 433.3 Mbps
• Bluetooth standard: v5.0

Absolute Maximum Ratings:

• Max supply voltage: 6.0 V (VBAT)
• Max continuous current: null
• Max junction/storage temperature: +125 °C (Junction)

Key Specs:

• WLAN Standard: IEEE 802.11ac (single-stream)
• WLAN Data Rate: Up to 433.3 Mbps (MCS0-MCS9, 80 MHz channels)
• Bluetooth Standard: v5.0 + EDR
• Host Interfaces: SDIO v3.0 (4b/1b), high-speed 4-wire UART, PCIe 1 Gen1 (PCIe not supported by firmware)
• On-chip Memory: 800KB SRAM, 704 KB ROM
• GPIOs: 15
• Integrated PAs and LNAs for 2.4 GHz and 5 GHz bands
• Supply Voltage Range: 3.0 V to 5.25 V (VBAT)

Features:

• IEEE 802.11ac compliant with TurboQAM®
• Bluetooth Core Specification v5.0 compliant
• On-chip power amplifiers and low-noise amplifiers for both bands
• Supports standard SDIO v3.0 (DDR50, SDR104) and PCIe 1 Gen1 interfaces
• Integrated ARMCR4 processor with tightly coupled memory for WLAN subsystem
• Enhanced collaborative coexistence hardware mechanisms and algorithms
• Supports battery voltage range from 3.0 V to 5.25 V
• 15 GPIOs

Applications:

• Internet of Things applications
• Handheld wireless systems
• Mobile devices

Package:

• 140-ball WLBGA (4.47 mm × 5.27 mm, 0.4 mm pitch)

• ■ IEEE 802.11ac compliant.
• ■ Support for TurboQAM ® (MCS0-MCS8 86 Mbps and MCS0MCS9 96 Mbps) HT20, 20 MHz channel bandwidth.
• ■ Single-stream spatial multiplexing up to 433.3 Mbps data rate.
• ■ Supports 20, 40, and 80 MHz channels with optional SGI (256 QAM modulation).
• ■ Full IEEE 802.11a/b/g/n legacy compatibility with enhanced performance.
• ■ Supports explicit IEEE 802.11ac transmit beamforming.
• ■ TX and RX low-density parity check (LDPC) support for improved range and power efficiency.
• ■ On-chip power amplifiers and low-noise amplifiers for both bands.
• ■ Support for optional front-end modules (FEM) with external PAs and LNAs.
• ■ Supports optional integrated T/R switch for 2.4 GHz band.
• ■ Supports RF front-end architecture with a single dual-band antenna shared between Bluetooth and WLAN for lowest system cost.
• ■ Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN.
• ■ Internal fractional-n PLL allows support for a wide range of reference clock frequencies.
• ■ Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as LTE or GPS.

1. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

·

·

·

• ■ Supports standard SDIO v3.0 (including DDR50 mode at 50 MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit) interfaces.
• ■ Backward compatible with SDIO v2.0 host interfaces.
• ■ PCIe 2 mode complies with PCI Express base specification revision 3.0 compliant Gen1 interface for ×1 lane and power management base specification.
• ■ Integrated ARMCR4 processor with tightly coupled memory for complete WLAN subsystem functionality and minimizing the need to wake-up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. On-chip memory includes 800KB SRAM and 704 KB ROM.

Figure 22. Signal Connections to SDIO Host (SD 4-Bit Mode)

Figure 23. Signal Connections to SDIO Host (SD 1-Bit Mode)

Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper programming of the SDIO host's internal pull-ups.

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Caution! The absolute maximum ratings in Table 25 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Table 25. Absolute Maximum Ratings

Caution! Functional operation is not guaranteed outside of the limits shown in Table 28. Operation outside these limits for extended periods can adversely affect long-term reliability of the device.

Note: For DC absolute maximum rating (AMR), see Table 25.

Table 28. Recommended Operating Conditions and DC Characteristics