CYW43455

Part: Cypress CYW43455

Type: Single-Chip 5G WiFi IEEE 802.11n/ac MAC/ Baseband/ Radio with Integrated Bluetooth 5.0

Key Specs:

• WLAN data rate: up to 433.3 Mbps
• Bluetooth version: 5.0
• Supply voltage range: 3.0 V to 5.25 V
• GPIOs: 15
• On-chip SRAM: 800 KB
• On-chip ROM: 704 KB

Features:

• IEEE 802.11ac compliant
• Single-stream spatial multiplexing
• Supports 20, 40, and 80 MHz channels
• On-chip 2.4 GHz and 5 GHz transmit amplifiers and receive low-noise amplifiers
• Support for optional external PAs and LNAs
• Shared Bluetooth and WLAN receive signal path
• SDIO v3.0 (4-bit and 1-bit) host interface
• High-speed 4-wire UART interface
• PCIe Gen1 (3.0 compliant) interface (not supported on CYW43455)
• Integrated ARMCR4 processor
• Bluetooth Core Specification v5.0 compliant
• Bluetooth Class 1 or Class 2 transmitter operation
• Supports extended synchronous connections (eSCO)
• Adaptive frequency hopping (AFH)
• Low power consumption
• Internal switching regulator
• 6 Kbit OTP
• WPA and WPA2 (Personal) support
• AES and TKIP in hardware

Applications:

• Internet of Things applications
• Handheld wireless system
• Mobile devices

Package:

• 140-ball WLBGA package: 4.47 mm × 5.27 mm, 0.4 mm pitch

• IEEE 802.11ac compliant.

• Support for TurboQAM® (MCS0–MCS8 86 Mbps and MCS0– MCS9 96 Mbps) HT20, 20 MHz channel bandwidth.

• Single-stream spatial multiplexing up to 433.3 Mbps data rate.

• Supports 20, 40, and 80 MHz channels with optional SGI (256 QAM modulation).

• Full IEEE 802.11a/b/g/n legacy compatibility with enhanced performance.

• Supports explicit IEEE 802.11ac transmit beamforming.

• TX and RX low-density parity check (LDPC) support for improved range and power efficiency.

• On-chip power amplifiers and low-noise amplifiers for both bands.

• Support for optional front-end modules (FEM) with external PAs and LNAs.

• Supports optional integrated T/R switch for 2.4 GHz band.

• Supports RF front-end architecture with a single dual-band antenna shared between Bluetooth and WLAN for lowest system cost.

• Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN.

• Internal fractional-n PLL allows support for a wide range of reference clock frequencies.

• Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as LTE or GPS.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-15051 Rev. *O Revised March 22, 2019

^1. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

• Supports standard SDIO v3.0 (including DDR50 mode at 50 MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit) interfaces.
• Backward compatible with SDIO v2.0 host interfaces.
• PCIe2 mode complies with PCI Express base specification revision 3.0 compliant Gen1 interface for ×1 lane and power management base specification.
• Integrated ARMCR4 processor with tightly coupled memory for complete WLAN subsystem functionality and minimizing the need to wake-up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. On-chip memory includes 800KB SRAM and 704 KB ROM.

12.1 Ball Map

Figure 28. 140-Ball WLBGA Map—Bottom View (Balls Facing Up)

| | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |---|---------------------|--------------------------|---------------------------|--------------------------|------------------|-------------------|-------------------|----------------|-------------------|------------------|-----------------|---| | A | | PCIE_TDN | PCIE_RDN | PCIE_RDP | SDIO_CLK | SDIO_DAT
A_3 | LDO_VDDB
AT5V | VOUT_3P3 | LDO_VDD1
P5 | SR_VDDBA
T5V | SR_PVSS | , | | B | PCIE_REF
CLKP | PCIE_TDP | PCIE_RXT
X_AVDD1P
2 | PCIE_CLK
REQ_L | SDIO_DAT
A_1 | SDIO_DAT
A_2 | VOUT_BTL
DO2P5 | VOUT_LNL
DO | VOUT_CLD
O | VOUT_PCI
ELDO | SR_VLX | E | | C | PCIE_REF
CLKN | PCIE_PLL_
AVDD1P2 | PCIE_VSS | VDDC | SDIO_DAT
A_0 | SDIO_CMD | VSSC | WL_REG_
ON | BT_REG_O
N | PMU_AVSS | GPIO_0 | ď | | D | GPIO_13 | GPIO_14 | NC1 | PERST_L | PCI_PME_
L | VDDIO_SD | VDDIO | GPIO_2 | GPIO_1 | GPIO_3 | GPIO_6 | [ | | E | NC2 | AVSS_BBP
LL | AVDD_BBP
LL | NC3 | VDDIO_RF | RF_SWCT
RL_8 | JTAG_SEL | GPIO_4 | GPIO_5 | VDDC | GPIO_7 | E | | F | RF_SW_CT
RL_0 | RF_SW_CT
RL_1 | VSSC | VDDC | RF_SWCT
RL_4 | RF_SWCT
RL_7 | VSSC | GPIO_9 | GPIO_10 | BT_VDDC | LPO_IN | F | | G | WRF_XTAL
XON | WRF_XTAL
GND1P2 | RF_SW_CT
RL_2 | RF_SW_CT
RL_3 | RF_SWCT
RL_5 | RF_SWCT
RL_6 | GPIO_8 | BT_VDDO | BT_PCM_S
YNC | VSSC | BT_PCM_I
N | G | | H | WRF_XTAL
XOP | WRF_XTAL
VDD1P35 | WRF_XTAL
VDD1P2 | WRF_SYN
TH_VDD3P
3 | | BT_GPIO
3 | BT_GPIO
4 | NC | BT_PCM_O
UT | BT_I2S_DO | BT_PCM_C
LK | F | | J | WRF_PMU
VDD1P35 | WRF_SYN
TH_VDD1P
2 | WRF_SYN
TH_GND | WRF_VCO
GND | BT_GPIO
2 | BT_UART
CTS_N | VDDC | BT_VDDC | BT_I2S_W
S | BT_I2S_DI | BT_I2S_CL
K | J | | K | WRF_RX5
G_GND | WRF_AFE
VDD1P35 | WRF_GEN
ERAL_GND | WRF_EXT
TSSIA | GPIO_15 | GPIO_16 | VSSC | BT_GPIO
5 | BT_UART_
RTS_N | BT_UART_
TXD | BT_UART_
RXD | ۲ | | L | WRF_RFIN
5G | WRF_GEN
ERAL2_GN
D | WRF_AFE
GND | WRF_GPAI
O_OUT | BT_LNAVD
D1P2 | BT_IFVSS | BT_PLLVS
S | BT_CLK_R
EQ | BT_HOST_
WAKE | VSSC | BT_VDDC | L | | M | WRF_PAO
UT_5G | WRF_PA_
GND3P3 | WRF_TXMI
X_VDD | WRF_RX2
G_GND | BT_LNAVS
S | BT_PAVSS | BT_PLLVD
D1P2 | FM_PLLVS
S | FM_RFVSS | FM_PLLVD
D1P2 | BT_DEV_W
AKE | N | | N | WRF_PA_V
DD3P3 | | WRF_PAO
UT_2G | WRF_RFIN
_2G | BT_RF | BT_PAVDD
2P5 | BT_IFVDD1
P2 | FM_RFIN | FM_RFVDD
1P2 | FM_AOUT2 | FM_AOUT1 | ١ | | | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | ì |

12.2 Pin List by Pin Number

Table 18 lists CYW43455 pins by pin number. For a list of CYW43455 pins by pin name, see Table 19

Table 18. Pin List by Pin Number

Ball Name A1 SR_PVSS A2 SR_VDDBAT5V A3 LDO_VDD1P5 A4 VOUT_3P3 A5 LDO_VDDBAT5V A6 SDIO_DATA_3 A7 SDIO_CLK A8 PCIE_RDP A9 PCIE_RDN A10 PCIE_TDN A11 – B1 SR_VLX B2 VOUT_PCIELDO B3 VOUT_CLDO B4 VOUT_LNLDO B5 VOUT_BTLDO2P5 B6 SDIO_DATA_2 B7 SDIO_DATA_1 B8 PCIE_CLKREQ_L B9 PCIE_RXTX_AVDD1P2 B10 PCIE_TDP B11 PCIE_REFCLKP C1 GPIO_0 C2 PMU_AVSS C3 BT_REG_ON C4 WL_REG_ON C5 VSSC C6 SDIO_CMD C7 SDIO_DATA_0 C8 VDDC C9 PCIE_VSS C10 PCIE_PLL_AVDD1P2 C11 PCIE_REFCLKN D1 GPIO_6 D2 GPIO_3 D3 GPIO_1 D4 GPIO_2

Table 18. Pin List by Pin Number (continued)

Ball	Name
D5	VDDIO
D6	VDDIO_SD
D7	PCI_PME_L
D8	PERST_L
D9	NC1
D10	GPIO_14
D11	GPIO_13
E1	GPIO_7
E2	VDDC
E3	GPIO_5
E4	GPIO_4
E5	JTAG_SEL
E6	RF_SW_CTRL_8
E7	VDDIO_RF
E8	NC3
E9	AVDD_BBPLL
E10	AVSS_BBPLL
E11	NC2
F1	LPO_IN
F2	BT_VDDC
F3	GPIO_10
F4	GPIO_9
F5	VSSC
F6	RF_SW_CTRL_7
F7	RF_SW_CTRL_4
F8	VDDC
F9	VSSC
F10	RF_SW_CTRL_1
F11	RF_SW_CTRL_0
G1	BT_PCM_IN
G2	VSSC
G3	BT_PCM_SYNC
G4	BT_VDDO
G5	GPIO_8
G6	RF_SW_CTRL_6
G7	RF_SW_CTRL_5
G8	RF_SW_CTRL_3

Document Number: 002-15051 Rev. *O Page 54 of 121

Table 18. Pin List by Pin Number (continued)

Ball	Name
G9	RF_SW_CTRL_2
G10	WRF_XTAL_GND1P2
G11	WRF_XTAL_XON
H1	BT_PCM_CLK
H2	BT_I2S_DO
H3	BT_PCM_OUT
H4	NC
H5	BT_GPIO_4
H6	BT_GPIO_3
H7	–
H8	WRF_SYNTH_VDD3P3
H9	WRF_XTAL_VDD1P2
H10	WRF_XTAL_VDD1P35
H11	WRF_XTAL_XOP
J1	BT_I2S_CLK
J2	BT_I2S_DI
J3	BT_I2S_WS
J4	BT_VDDC
J5	VDDC
J6	BT_UART_CTS_N
J7	BT_GPIO_2
J8	WRF_VCO_GND
J9	WRF_SYNTH_GND
J10	WRF_SYNTH_VDD1P2
J11	WRF_PMU_VDD1P35
K1	BT_UART_RXD
K2	BT_UART_TXD
K3	BT_UART_RTS_N
K4	BT_GPIO_5
K5	VSSC
K6	GPIO_16
K7	GPIO_15
K8	WRF_EXT_TSSIA
K9	WRF_GENERAL_GND
K10	WRF_AFE_VDD1P35
K11	WRF_RX5G_GND
L1	BT_VDDC
L2	VSSC
L3	BT_HOST_WAKE

Table 18. Pin List by Pin Number (continued)

Ball	Name
L4	BT_CLK_REQ
L5	BT_PLLVSS
L6	BT_IFVSS
L7	BT_LNAVDD1P2
L8	WRF_GPAIO_OUT
L9	WRF_AFE_GND
L10	WRF_GENERAL2_GND
L11	WRF_RFIN_5G
M1	BT_DEV_WAKE
M2	FM_PLLVDD1P2
M3	FM_RFVSS
M4	FM_PLLVSS
M5	BT_PLLVDD1P2
M6	BT_PAVSS
M7	BT_LNAVSS
M8	WRF_RX2G_GND
M9	WRF_TXMIX_VDD
M10	WRF_PA_GND3P3
M11	WRF_PAOUT_5G
N1	FM_AOUT1
N2	FM_AOUT2
N3	FM_RFVDD1P2
N4	FM_RFIN
N5	BT_IFVDD1P2
N6	BT_PAVDD2P5
N7	BT_RF
N8	WRF_RFIN_2G
N9	WRF_PAOUT_2G
N10	–
N11	WRF_PA_VDD3P3

12.3 Pin List by Pin Name

Table 19 lists CYW43455 pins by pin name. For a list of CYW43455 pins by pin number, see Table 18.

Table 19. Pin List by Pin Name

Name Ball AVDD_BBPLL E9 AVSS_BBPLL E10 BT_CLK_REQ L4 BT_DEV_WAKE M1 BT_GPIO_2 J7 BT_GPIO_3 H6 BT_GPIO_4 H5 BT_GPIO_5 K4 BT_HOST_WAKE L3 BT_I2S_CLK J1 BT_I2S_DI J2 BT_I2S_DO H2 BT_I2S_WS J3 BT_IFVDD1P2 N5 BT_IFVSS L6 BT_LNAVDD1P2 L7 BT_LNAVSS M7 BT_PAVDD2P5 N6 BT_PAVSS M6 BT_PCM_CLK H1 BT_PCM_IN G1 BT_PCM_OUT H3 BT_PCM_SYNC G3 BT_PLLVDD1P2 M5 BT_PLLVSS L5 BT_REG_ON C3 BT_RF N7 BT_UART_CTS_N J6 BT_UART_RTS_N K3 BT_UART_RXD K1 BT_UART_TXD K2 BT_VDDC F2 BT_VDDC J4 BT_VDDC L1 BT_VDDO G4 FM_AOUT1 N1 FM_AOUT2 N2

Table 19. Pin List by Pin Name (continued)

Name	Ball
FM_PLLVDD1P2	M2
FM_PLLVSS	M4
FM_RFIN	N4
FM_RFVDD1P2	N3
FM_RFVSS	M3
GPIO_0	C1
GPIO_1	D3
GPIO_2	D4
GPIO_3	D2
GPIO_4	E4
GPIO_5	E3
GPIO_6	D1
GPIO_7	E1
GPIO_8	G5
GPIO_9	F4
GPIO_10	F3
GPIO_13	D11
GPIO_14	D10
GPIO_15	K7
GPIO_16	K6
JTAG_SEL	E5
LDO_VDD1P5	A3
LDO_VDDBAT5V	A5
LPO_IN	F1
NC	H4
NC1	D9
NC2	E11
NC3	E8
PCIE_CLKREQ_L	B8
PCIE_PLL_AVDD1P2	C10
PCIE_RDN	A9
PCIE_RDP	A8
PCIE_REFCLKN	C11
PCIE_REFCLKP	B11
PCIE_RXTX_AVDD1P2	B9
PCIE_TDN	A10
PCIE_TDP	B10
Document Number: 002-15051 Rev. *O Page 56 of 121

Table 19. Pin List by Pin Name (continued)

PCIE_VSS C9 PCI_PME_L D7 PERST_L D8 PMU_AVSS C2 RF_SW_CTRL_0 F11 RF_SW_CTRL_1 F10 RF_SW_CTRL_2 G9 RF_SW_CTRL_3 G8 RF_SW_CTRL_4 F7 RF_SW_CTRL_5 G7 RF_SW_CTRL_6 G6 RF_SW_CTRL_7 F6 RF_SW_CTRL_8 E6 SDIO_CLK A7 SDIO_CMD C6 SDIO_DATA_0 C7 SDIO_DATA_1 B7 SDIO_DATA_2 B6 SDIO_DATA_3 A6 SR_PVSS A1 SR_VDDBAT5V A2 SR_VLX B1 VDDC C8 VDDC E2 VDDC F8 VDDC J5 VDDIO D5 VDDIO_RF E7 VDDIO_SD D6 VOUT_3P3 A4 VOUT_BTLDO2P5 B5 VOUT_CLDO B3 VOUT_LNLDO B4 VOUT_PCIELDO B2 VSSC C5 VSSC F5 VSSC F9 VSSC G2 VSSC K5 Name Ball

Table 19. Pin List by Pin Name (continued)

Name	Ball
VSSC	L2
WL_REG_ON	C4
WRF_AFE_GND	L9
WRF_AFE_VDD1P35	K10
WRF_EXT_TSSIA	K8
WRF_GENERAL2_GND	L10
WRF_GENERAL_GND	K9
WRF_GPAIO_OUT	L8
WRF_PAOUT_2G	N9
WRF_PAOUT_5G	M11
WRF_PA_GND3P3	M10
WRF_PA_VDD3P3	N11
WRF_PMU_VDD1P35	J11
WRF_RFIN_2G	N8
WRF_RFIN_5G	L11
WRF_RX2G_GND	M8
WRF_RX5G_GND	K11
WRF_SYNTH_GND	J9
WRF_SYNTH_VDD1P2	J10
WRF_SYNTH_VDD3P3	H8
WRF_TXMIX_VDD	M9
WRF_VCO_GND	J8
WRF_XTAL_GND1P2	G10
WRF_XTAL_VDD1P2	H9
WRF_XTAL_VDD1P35	H10
WRF_XTAL_XON	G11
WRF_XTAL_XOP	H11
–	A11
–	H7
–	N10

12.4 Pin Descriptions

The signal name, type, and description of each pin in the CYW43455 is listed in Table 20. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.

Table 20. Signal Descriptions

Signal Name	WLBGA Ball	Type	Description
WLAN and Bluetooth Receive RF Signal Interface
WRF_RFIN_2G	N8	I	2.4 GHz Bluetooth and WLAN receiver shared input.
WRF_RFIN_5G	L11	I	5 GHz WLAN receiver input.
WRF_PAOUT_2G	N9	O	2.4 GHz WLAN PA output.
WRF_PAOUT_5G	M11	O	5 GHz WLAN PA output.
WRF_EXT_TSSIA	K8	I	5 GHz TSSI input from an optional external power amplifier/power detector.
WRF_GPAIO_OUT	L8	I/O	GPIO or 2.4 GHz TSSI input from an optional external power amplifier/power detector.
RF Switch Control Lines
RF_SW_CTRL_0	F11	O	Programmable RF switch control lines. The
RF_SW_CTRL_1	F10	O	control lines are programmable via the driver and NVRAM file.
RF_SW_CTRL_2	G9	O
RF_SW_CTRL_3	G8	O
RF_SW_CTRL_4	F7	O
RF_SW_CTRL_5	G7	O
RF_SW_CTRL_6	G6	O
RF_SW_CTRL_7	F6	O
RF_SW_CTRL_8	E6	O
WLAN PCI Express Interface			Note: The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.
PCIE_CLKREQ_L	B8	OD	PCIe clock request signal which indicates when the REFCLK to the PCIe interface can be gated. 1 = the clock can be gated. 0 = the clock is required.
PERST_L	D8	I (PU)	PCIe System Reset. This input is the PCIe reset as defined in the PCIe Base Specifi cation Version 1.1.
PCIE_RDN	A9	I	Receiver differential pair (×1 lane).
PCIE_RDP	A8	I
PCIE_REFCLKN	C11	I	PCIe differential clock inputs (negative and
PCIE_REFCLKP	B11	I	positive), 100 MHz differential.
PCIE_TDN	A10	O	Transmitter differential pair (×1 lane).
PCIE_TDP	B10	O

Table 20. Signal Descriptions (continued)

Signal Name	WLBGA Ball	Type	Description
PCI_PME_L	D7	OD	PCI power management event output. Used to request a change in the device or system power state. The assertion and deassertion of this signal is asynchronous to the PCIe reference clock. This signal has an open-drain output structure, as per the PCI Bus Local Bus Specification, Revision 2.3.
WLAN SDIO Bus Interface Note: These signals can also have alternate functionality depending on package and host interface mode.
SDIO_CLK	A7	I	SDIO clock input.
SDIO_CMD	C6	I/O	SDIO command line.
SDIO_DATA_0	C7	I/O	SDIO data line 0.
SDIO_DATA_1	B7	I/O	SDIO data line 1.
SDIO_DATA_2	B6	I/O	SDIO data line 2.
SDIO_DATA_3	A6	I/O	SDIO data line 3.
WLAN GPIO Interface			Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to behave as various specific functions.
GPIO_0	C1	I/O	Programmable GPIO pins:
GPIO_1	D3	I/O	GPIO_2 is TCK/SWCLK if JTAG_SEL = 1
GPIO_2	D4	I/O	GPIO_3 is TMS/SWDIO if
GPIO_3	D2	I/O	JTAG_SEL = 1
GPIO_4	E4	I/O	GPIO_4 is TDIO if JTAG_SEL = 1 GPIO_5 is TDO if JTAG_SEL = 1
GPIO_5	E3	I/O	GPIO_6 is TRST_L if JTAG_SEL = 1
GPIO_6	D1	I/O
GPIO_7	E1	I/O
GPIO_8	G5	I/O
GPIO_9	F4	I/O
GPIO_10	F3	I/O
GPIO_13	D11	I/O
GPIO_14	D10	I/O
GPIO_15	K7	I/O
GPIO_16	K6	I/O

Table 20. Signal Descriptions (continued)

Signal Name	WLBGA Ball	Type	Description
JTAG/SWD Interface
JTAG_SEL	E5	I/O	JTAG select. This pin must be connected to ground if the JTAG/SWD interface is not used. It must be high to select SWD OR JTAG. When JTAG_SEL = 1: GPIO_2 is TCK/SWCLK GPIO_3 is TMS/SWDIO GPIO_4 is TDIO GPIO_5 is TDO GPIO_6 is TRST_L
Clocks
WRF_XTAL_XOP	H11	I	XTAL oscillator input.
WRF_XTAL_XON	G11	O	XTAL oscillator output.
LPO_IN	F1	I	External sleep clock input (32.768 kHz).
BT_CLK_REQ	L4	O	Reference clock request (shared by BT and WLAN).
Bluetooth/FM Transceiver
BT_RF	N7	O	Bluetooth PA output.
FM_RFIN	N4	I	FM radio antenna port.
FM_AOUT1	N1	O	FM DAC output 1.
FM_AOUT2	N2	O	FM DAC output 2.
Bluetooth PCM
BT_PCM_CLK	H1	I/O	PCM or SLIMbus clock; can be master (output) or slave (input).
BT_PCM_IN	G1	I	PCM data input or SLIMbus transport sensing.
BT_PCM_OUT	H3	O	PCM data output.
BT_PCM_SYNC	G3	I/O	PCM sync; can be master (output) or slave (input), or SLIMbus data.
Bluetooth UART
BT_UART_CTS_N	J6	I	UART clear-to-send. Active-low clear-to-send signal for the HCI UART interface.
BT_UART_RTS_N	K3	O	UART request-to-send. Active-low request-to-send signal for the HCI UART interface. BT LED control pin.
BT_UART_RXD	K1	I	UART serial input. Serial data input for the HCI UART interface. BT RF disable pin 2.
BT_UART_TXD	K2	O	UART serial output. Serial data output for the HCI UART interface.
Bluetooth/FM/I2S
BT_I2S_CLK	J1	I/O	I2S clock, can be master (output) or slave (input).

Table 20. Signal Descriptions (continued)

Signal Name	WLBGA Ball	Type	Description
BT_I2S_DI	J2	I/O	I2S data input.
BT_I2S_DO	H2	I/O	I2S data output.
BT_I2S_WS	J3	I/O	I2S WS; can be master (output) or slave (input).
Bluetooth GPIO
BT_GPIO_2	J7	I/O	Bluetooth general-purpose I/O.
BT_GPIO_3	H6	I/O	Bluetooth general-purpose I/O.
BT_GPIO_4	H5	I/O	Bluetooth general-purpose I/O.
BT_GPIO_5	K4	I/O	Bluetooth general-purpose I/O.
Miscellaneous
WL_REG_ON	C4	I	Used by PMU to power-up or power down the internal CYW43455 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming.
BT_REG_ON	C3	I	Used by PMU to power-up or power down the internal CYW43455 regulators used by the Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/FM section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming.
BT_DEV_WAKE	M1	I/O	Bluetooth DEV_WAKE.
BT_HOST_WAKE	L3	I/O	Bluetooth HOST_WAKE.
Integrated Voltage Regulators
SR_VDDBAT5V	A2	I	VBAT.
SR_VLX	B1	O	CBUCK switching regulator output. Refer to Table 44 for details of the inductor and capacitor required on this output.
LDO_VDD1P5	A3	I	LNLDO input.
LDO_VDDBAT5V	A5	I	LDO VBAT.
WRF_XTAL_VDD1P35	H10	I	XTAL LDO input (1.35V).
WRF_XTAL_VDD1P2	H9	O	XTAL LDO output (1.2V).
VOUT_LNLDO	B4	O	Output of LNLDO.
VOUT_CLDO	B3	O	Output of core LDO.
VOUT_BTLDO2P5	B5	O	Output of BT LDO.
VOUT_3P3	A4	O	LDO 3.3 V output.
Bluetooth Supplies
BT_PAVDD2P5	N6	PWR	Bluetooth PA power supply.
BT_LNAVDD1P2	L7	PWR	Bluetooth LNA power supply.
BT_IFVDD1P2	N5	PWR	Bluetooth IF block power supply.

Table 20. Signal Descriptions (continued)

Signal Name	WLBGA Ball	Type	Description
BT_PLLVDD1P2	M5	PWR	Bluetooth RF PLL power supply.
FM Transceiver Supplies
FM_RFVDD1P2	N3	PWR	FM RF power supply.
FM_PLLVDD1P2	M2	PWR	FM PLL power supply.
WLAN Supplies
WRF_SYNTH_VDD3P3	H8	PWR	Synthesizer VDD 3.3 V supply.
WRF_PA_VDD3P3	N11	PWR	2 GHz and 5 GHz PA 3.3 V VBAT supply.
WRF_PMU_VDD1P35	J11	PWR	PMU 1.35 V supply.
WRF_TXMIX_VDD	M9	PWR	3.3 V supply for the TX Mix.
WRF_SYNTH_VDD1P2	J10	PWR	1.2 V supply for the synthesizer.
WRF_AFE_VDD1P35	K10	PWR	1.35 V supply for the AFE.
Miscellaneous Supplies
VDDC	C8, E2, F8, J5	PWR	1.2 V core supply for the WLAN.
VDDIO	D5	PWR	1.8 V–3.3 V VDDIO supply for the WLAN. Must be directly connected to PMU_VDDO and BT_VDDO on the PCB.
BT_VDDC	F2, J4, L1	PWR	1.2 V core supply for the BT.
BT_VDDO	G4	PWR	1.8 V–3.3 V VDDIO supply for the BT. Must be directly connected to PMU_VDDO and VDDIO on the PCB.
VDDIO_SD	D6	PWR	1.8 V–3.3 V supply for the SDIO pads.
VDDIO_RF	E7	PWR	IO supply for the RF switch control pads (3.3 V).
AVDD_BBPLL	E9	PWR	1.2 V supply for the baseband PLL.
PCIE_PLL_AVDD1P2	C10	PWR	1.2 V supply for the PCIe PLL.
VOUT_PCIELDO	B2	PWR	1.2 V supply for the PCIe.
PCIE_RXTX_AVDD1P2	B9	PWR	1.2 V supply for the PCIe TX/RX.
Ground
WRF_VCO_GND	J8	GND	VCO/LOGEN ground.
WRF_AFE_GND	L9	GND	AFE ground.
WRF_XTAL_GND1P2	G10	GND	XTAL ground.
WRF_RX2G_GND	M8	GND	RX 2 GHz ground.
WRF_RX5G_GND	K11	GND	RX 5 GHz ground.
WRF_PA_GND3P3	M10	GND	PA ground.
WRF_GENERAL_GND	K9	GND	General ground.
WRF_GENERAL2_GND	L10	GND	General ground.
WRF_SYNTH_GND	J9	GND	Ground.
VSSC	C5, F5, F9, G2, K5, L2	GND	Core ground for WLAN and BT.
SR_PVSS	A1	GND	Power ground.

Document Number: 002-15051 Rev. *O Page 62 of 121

Table 20. Signal Descriptions (continued)

Signal Name	WLBGA Ball	Type	Description
PMU_AVSS	C2	GND	Quiet ground.
BT_PAVSS	M6	GND	Bluetooth PA ground.
BT_LNAVSS	M7	GND	Bluetooth LNA ground.
BT_IFVSS	L6	GND	Bluetooth IF block ground.
BT_PLLVSS	L5	GND	Bluetooth PLL ground.
FM_PLLVSS	M4	GND	FM PLL ground.
FM_RFVSS	M3	GND	FM RF ground.
AVSS_BBPLL	E10	GND	Baseband PLL ground.
PCIE_VSS	C9	GND	PCIe ground.
No Connect
NC1	D9	–	No connect.
NC2	E11
NC3	E8
NC	H4	–	No connect.
Depopulated Pins
–	A11, H7, N10	–	–

12.5 WLAN GPIO Signals and Strapping Options

This section describes WLAN GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kΩ resistor or less.

Note: Refer to the reference board schematics for more information.

Table 21. Strapping Options

Pin Name	Strap	WLBGA Ball		Default Internal Pull During Strap	Description
GPIO_7	sdio_padvddio	E1	1		Default pull = 1.
					SDIO interface voltage. 1 = 1.8 V, 0 = 3.3 V. Default is 1.8 V.
GPIO_16	host_iface_sdio	K6	0		Default is PCIe. Pull high during POR to select SDIO.

12.5.1 Multiplexed Bluetooth GPIO Signals

The Bluetooth GPIO pins (BT_GPIO_0 to BT_GPIO_7) are multiplexed pins and can be programmed to be used as GPIOs or for other Bluetooth interface signals such as ^I2S. The specific function for a given BT_GPIO_X pin is chosen by programming the Pad Function Control register for that specific pin. Table 22 shows the possible options for each BT_GPIO_X pin. Note that each BT_GPIO_X pin's Pad Function Control register setting is independent (BT_GPIO_5 can be set to pad function 7 at the same time that BT_GPIO_3 is set to pad function 0). When the Pad Function Control register is set to 0, the BT_GPIOs do not have specific functions assigned to them and behave as generic GPIOs. The A_GPIO_X pins described below are multiplexed behind the CYW43455's PCM and I2S interface pins.

Table 22. GPIO Multiplexing Matrix

| | | | | Pa
d
Fu
t
io
nc
n | Co
tro
l
Re
is
te
n
g | Se
t
t
ing
r | |---------------------------------------------------|-------------------------------------------------------|----------------------------------|----------------------------------|-------------------------------------|-----------------------------------------------------------|----------------------------------|---|------------------------------------------------------|----------------------------------------| | P
in
Na
me | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1
5 | | B
T_
U
A
R
T_
C
T
S_
N | U
A
R
T_
C
T
S_
N | – | – | – | – | – | – | A_
G
P
I
O
[
1
] | – | | B
T_
U
A
R
T_
R
T
S_
N | U
A
R
T_
R
T
S_
N | – | – | – | – | – | – | A_
G
P
I
O
[
0
] | – | | B
T_
U
A
R
T_
R
X
D | U
A
R
T_
R
X
D | – | – | – | – | – | – | G
P
I
O
[
5
] | – | | B
T_
U
A
R
T_
T
X
D | U
A
R
T_
T
X
D | – | – | – | – | – | – | G
P
I
O
[
4
] | – | | B
T_
P
C
M_
I
N | A_
G
P
I
O
[
3
] | P
C
M_
I
N | P
C
M_
I
N | H
C
L
K | – | – | – | I
2
S_
S
S
D
I
/
M
S
D | I
S
F_
M
I
S
O | | B
T_
P
C
M_
O
U
T | A_
G
P
I
O
[
2
] | P
C
M_
O
U
T | P
C
M_
O
U
T | L
I
N
K_
I
N
D | – | I
2
S_
M
S
D
O | – | I
2
S_
S
S
D
O | S
F_
M
O
S
I | | C
S
C
B
T_
P
M_
Y
N | G
O
A_
P
I
[
1
] | C
S
C
P
M_
Y
N | C
S
C
P
M_
Y
N | C
H
L
K | – | S_
S
I
2
M
W | – | S_
S
S
I
2
W | S
S
C
S
F_
P
I_
N | | C
C
B
T_
P
M_
L
K | G
O
A_
P
I
[
0
] | C
C
P
M_
L
K | C
C
P
M_
L
K | – | – | S_
S
C
I
2
M
K | – | S_
S
S
C
I
2
K | S
S
C
F_
P
I_
L
K | | B
T_
I
2
S_
D
O | A_
G
P
I
O
[
]
5 | P
C
M_
O
U
T | – | – | I
2
S_
S
S
D
O | I
2
S_
M
S
D
O | – | S
T
A
T
U
S | – | | B
T_
I
2
S_
D
I | A_
G
P
I
O
[
6
] | P
C
M_
I
N | – | H
C
L
K | I
2
S_
S
S
D
I
/
M
S
D
I | – | – | T
X_
C
O
N_
F
X | – | | B
T_
I
2
S_
W
S | G
P
I
O
[
]
7 | P
C
M_
S
Y
N
C | – | L
I
N
K_
I
N
D | – | I
2
S_
M
W
S | – | I
2
S_
S
W
S | – | | B
T_
I
2
S_
C
L
K | G
P
I
O
[
6
] | P
C
M_
C
L
K | – | – | – | I
2
S_
M
S
C
K | – | I
2
S_
S
S
C
K | – | | B
T_
G
P
I
O_
5 | G
P
I
O
[
5
] | H
C
L
K | – | I
2
S_
M
S
C
K | I
2
S_
S
S
C
K | – | – | C
L
K_
R
E
Q | – | | B
T_
G
P
I
O_
4 | G
P
I
O
[
4
] | L
I
N
K_
I
N
D | – | I
2
S_
M
S
D
O | I
2
S_
S
S
D
O | – | – | – | – | | B
T_
G
P
I
O_
3 | G
P
I
O
[
3
] | – | – | I
2
S_
M
W
S | I
2
S_
S
W
S | – | – | – | – | | G
O_
B
T_
P
I
2 | G
O
P
I
[
2
] | – | – | – | S_
S
S
/
S
I
2
D
I
M
D
I | – | – | – | – | | B
T_
C
L
K_
R
E
Q | W
L
/
B
T_
C
L
K_
R
E
Q | – | – | – | – | – | – | A_
G
P
I
O
[
7
] | – |

The multiplexed GPIO signals are described in Table 23.

Table 23. Multiplexed GPIO Signals

Pin Name	Type	Description
UART_CTS_N	I	Host UART clear to send.
UART_RTS_N	O	Device UART request to send.
UART_RXD	I	Device UART receive data.
UART_TXD	O	Host UART transmit data.
PCM_IN	I	PCM data input.
PCM_OUT	O	PCM data output.
PCM_SYNC	I/O	PCM sync signal, can be master (output) or slave (input).
PCM_CLK	I/O	PCM clock, can be master (output) or slave (input).
GPIO[7:0]	I/O	General-purpose I/O.
A_GPIO[7:0]	I/O	A group general-purpose I/O.
I2S_MSDO	O	I2S master data output.
I2S_MWS	O	I2S master word select.
I2S_MSCK	O	I2S master clock.
I2S_SSCK	I	I2S slave clock.
I2S_SSDO	O	I2S slave data output.
I2S_SWS	I	I2S slave word select.
I2S_SSDI/MSDI	I	I2S slave/master data input.
STATUS	O	Signals Bluetooth priority status.
TX_CON_FX	I	WLAN-BT coexist. Transmission confirmation; permission for BT to transmit.
RF_ACTIVE	O	WLAN-BT coexist. Asserted (logic high) during local BT RX and TX slots.
LINK_IND	O	BT receiver/transmitter link indicator.
CLK_REQ	O	WLAN/BT clock request output.
SF_SPI_CLK	O	SFlash SCLK: serial clock (output from master).
SF_MISO	I	SFlash MISO; SOMI: master input, slave output (output from slave).
SF_MOSI	O	SFlash MOSI; SIMO: master output, slave input (output from master).
SF_SPI_CSN	O	SFlash SS: slave select (active low, output from master).

12.6 I/O States

The following notations are used in Table 24:

• I: Input signal
• O: Output signal
• I/O: Input/Output signal
• PU = Pulled up
• PD = Pulled down
• NoPull = Neither pulled up nor pulled down

Table 24. I/O States

Name	I/O	Keeper 1	Active Mode	Low Power State/Sleep (All Pow- er Present)	Power-down 2 (BT_REG_ON and WL_REG_ON Held Low)	Out-of-Reset; Before SW Download (BT_REG_ON High; WL_REG_ON High)	(WL_REG_ON High and BT_REG_ON = 0) and VDDIOs Are Present	Power Rail
WL_REG_ON	I	N	Input; PD (pull-down can be disabled)	Input; PD (pull-down can be disabled)	Input; PD (of 200K)	Input; PD (of 200K)	Input; PD (of 200K)	_
BT_REG_ON	I	N	Input; PD (pull down can be disabled)	Input; PD (pull down can be disabled)	Input; PD (of 200K)	Input; PD (of 200K)	Input; PD (of 200K)	_
BT_CLK_REQ	I/O	Υ	Open drain or push-pull (program-mable). Active high.	Open drain or push-pull (program- mable). Active high	High-Z, NoPull	Open drain. Active high	Open drain. Active high.	BT_VDDO
BT_HOST_WA KE	I/O	Υ	Input/Output; PU, PD, NoPull (programmable)	Input/Output; PU, PD, NoPull (programmable)	High-Z, NoPull	Input, PU	Input, PD	BT_VDDO
BT_DEV_WAK E	I/O	Υ	Input/Output; PU, PD, NoPull (programmable)	Input; PU, PD, NoPull (programmable)	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_GPIO_2, BT_GPIO_3	I/O	Υ	Input/Output; PU, PD, NoPull (programmable)	Input/Output; PU, PD, NoPull (programmable)	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_GPIO_4, BT_GPIO_5	I/O	Υ	Input/Output; PU, PD, NoPull (programmable)	Input/Output; PU, PD, NoPull (programmable)	High-Z, NoPull	Input, PU	Input, PU	BT_VDDO
BT_UART_CTS _N	I	Υ	Input; NoPull	Input; NoPull	High-Z, NoPull	Input; PU	Input; PU	BT_VDDO
BT_UART_RTS _N	0	Y	Output; NoPull	Output; NoPull	High-Z, NoPull	Input; PU	Input; PU	BT_VDDO
BT_UART_RXD	I	Υ	Input; PU	Input; NoPull	High-Z, NoPull	Input; PU	Input; PU	BT_VDDO
BT_UART_TXD	0	Υ	Output; NoPull	Output; NoPull	High-Z, NoPull	Input; PU	Input; PU	BT_VDDO

Document Number: 002-15051 Rev. *O Page 66 of 121

Table 24. I/O States (continued)

Name	I/O	Keeper 1	Active Mode	Low Power State/Sleep (All Pow- er Present)	Power-down 2 (BT_REG_ON and WL_REG_ON Held Low)	Out-of-Reset; Before SW Download (BT_REG_ON High; WL_REG_ON High)	(WL_REG_ON High and BT_REG_ON = 0) and VDDIOs Are Present	Power Rail
SDIO_DATA[0:3]	I/O	N	Input/Output; PU (SDIO Mode)	Input; PU (SDIO Mode)	High-Z, NoPull	Input; PU (SDIO Mode)	Input; PU (SDIO Mode)	WL_VDDI O
SDIO_CMD	I/O	N	Input/Output; PU (SDIO Mode)	Input; PU (SDIO Mode)	High-Z, NoPull	Input; PU (SDIO Mode)	Input; PU (SDIO Mode)	WL_VDDI O
SDIO_CLK	I	N	Input; NoPull	Input; noPull	High-Z, NoPull	Input; noPull	Input; noPull	WL_VDDI O
BT_PCM_CLK	I/O	Υ	Input; NoPull 3	Input; NoPull 3	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_PCM_IN	I/O	Υ	Input; NoPull 3	Input; NoPull 3	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_PCM_OUT	I/O	Υ	Input; NoPull 3	Input; NoPull 3	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_PC- M_SYNC	I/O	Y	Input; NoPull 3	Input; NoPull 3	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_I2S_WS	I/O	Υ	Input; NoPull 4	Input; NoPull 4	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_I2S_CLK	I/O	Υ	Input; NoPull 4	Input; NoPull 4	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_I2S_DI	I/O	Υ	Input; NoPull 4	Input; NoPull 4	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
BT_I2S_DO	I/O	Υ	Input; NoPull 4	Input; NoPull 4	High-Z, NoPull	Input, PD	Input, PD	BT_VDDO
GPIO_0	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: PD])	Input/Output; PU, PD, NoPull (programmable [Default: PD])	High-Z, NoPull	Input; PD	Input; PD	WL_VDDIO
GPIO_1	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDIO
GPIO_2	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDIO
GPIO_3	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: PD])	Input/Output; PU, PD, NoPull (programmable [Default: PD])	High-Z, NoPull	Input; PD	Input; PD	WL_VDDIO
GPIO_4	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDIO

Document Number: 002-15051 Rev. *O

Table 24. I/O States (continued)

Name	I/O	Keeper 1	Active Mode	Low Power State/Sleep (All Pow- er Present)	Power-down 2 (BT_REG_ON and WL_REG_ON Held Low)	Out-of-Reset; Before SW Download (BT_REG_ON High; WL_REG_ON High)	(WL_REG_ON High and BT_REG_ON = 0) and VDDIOs Are Present	Power Rail
GPIO_5	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: PD])	Input/Output; PU, PD, NoPull (programmable [Default: PD])	High-Z, NoPull	Input; PD	Input; PD	WL_VDDIO
GPIO_6	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDIO
GPIO_7	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDIO
GPIO_8	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: PD]) 5	Input/Output; PU, PD, NoPull (programmable [Default: PD]) 5	High-Z, NoPull	Input; PD 5	Input; PD 5	WL_VDDIO
GPIO_9	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: PD])	Input/Output; PU, PD, NoPull (programmable [Default: PD])	High-Z, NoPull	Input; PD	Input; PD	WL_VDDIO
GPIO_10	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDI O
GPIO_13	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDI O
GPIO_14	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDI O
GPIO_15	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDI O
GPIO_16	I/O	Y	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	Input/Output; PU, PD, NoPull (programmable [Default: NoPull])	High-Z, NoPull	Input; NoPull	Input; NoPull	WL_VDDI O

Document Number: 002-15051 Rev. *O

Table 24. I/O States (continued)

Name	I/O	Keeper 1	Active Mode	Low Power State/Sleep (All Pow- er Present)	Power-down 2 (BT_REG_ON and WL_REG_ON Held Low)	Out-of-Reset; Before SW Download (BT_REG_ON High; WL_REG_ON High)	(WL_REG_ON High and BT_REG_ON = 0) and VDDIOs Are Present	Power Rail
RF_SW_CTRL [0:8]	I/O	Υ	Output; NoPull	Output; NoPull	High-Z	Output; NoPull	Output; NoPull	VDDIO_R F

^1. Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in power-down state. If there is no keeper, and it is an input and there is NoPull, then the pad should be driven to prevent leakage due to floating pad (SDIO_CLK, for example).

Document Number: 002-15051 Rev. *O Page 69 of 121

^2. In the power-down state (xx_REG_ON=0): High-Z; NoPull => the pad is disabled because power is not supplied.

^3. Depending on whether the PCM interface is enabled and the configuration of PCM is in master or slave mode, it can be either output or input.

^4. Depending on whether the I²S interface is enabled and the configuration of I²S is in master or slave mode, it can be either output or input.

^5. NoPull when in SDIO mode.

13. DC Characteristics

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

13.1 Absolute Maximum Ratings

Caution! The absolute maximum ratings in Table 25 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Table 25. Absolute Maximum Ratings

Rating	Symbol	Value	Unit
DC supply for the VBAT and PA driver supply	VBAT	–0.5 to +6.0	V
DC supply voltage for digital I/O	VDDIO	–0.5 to 3.9	V
DC supply voltage for RF switch I/Os	VDDIO_RF	–0.5 to 3.9	V
DC input supply voltage for CLDO and LNLDO	–	–0.5 to 1.575	V
DC supply voltage for RF analog	VDDRF	–0.5 to 1.32	V
DC supply voltage for core	VDDC	–0.5 to 1.32	V
WRF_TCXO_VDD	–	–0.5 to 3.63	V
Maximum undershoot voltage for I/O1	Vundershoot	–0.5	V
Maximum overshoot voltage for I/O1	Vovershoot	VDDIO + 0.5	V
Maximum junction temperature	Tj	125	°C

^1. Duration not to exceed 25% of the duty cycle.

13.2 Environmental Ratings

The environmental ratings are shown in Table 26.

Table 26. Environmental Ratings

Characteristic	Value	Units	Conditions/Comments
Ambient Temperature (TA)	–30 to +85	°C	Functional operation1
Storage Temperature	–40 to +125	°C	–
Relative Humidity	Less than 60	%	Storage
	Less than 85	%	Operation

^1. Functionality is guaranteed across this ambient temperature range. Optimal RF performance specified in the data sheet, however, is guaranteed only for –20°C to 75°C.

13.3 Electrostatic Discharge Specifications

Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.

Document Number: 002-15051 Rev. *O Page 70 of 121

Table 27. ESD Specifications

Pin Type	Symbol	Condition	Minimum ESD Rating	Unit
ESD Handling Reference: NQY00083, Section 3.4, Group D9, Table B	ESD_HAND_HBM	Human body model contact discharge per JEDEC EID/JESD22-A114	1	kV
CDM	ESD_HAND_CDM	Charged device model contact discharge per JEDEC EIA/JESD22-C101	250	V

13.4 Recommended Operating Conditions and DC Characteristics

Caution! Functional operation is not guaranteed outside of the limits shown in Table 28. Operation outside these limits for extended periods can adversely affect long-term reliability of the device.

Note: For DC absolute maximum rating (AMR), see Table 25.

Table 28. Recommended Operating Conditions and DC Characteristics

| | | | Value | |-----------------------------------------|--------------|--------------|---------|--------------|------| | Parameter | Symbol | Minimum | Typical | Maximum | Unit | | DC supply voltage for VBAT | VBAT | 3.01 | – | 5.2526.0 | V | | DC supply voltage for core | VDD | 1.14 | 1.2 | 1.26 | V | | DC supply voltage for RF blocks in chip | VDDRF | 1.14 | 1.2 | 1.26 | V | | DC supply voltage for TCXO input buffer | WRF_TCXO_VDD | 1.62 | 1.8 | 1.98 | V | | DC supply voltage for digital I/O | VDDIO | 1.62 | – | 3.63 | V | | DC supply voltage for RF switch I/Os | VDDIO_RF | 3.13 | 3.3 | 3.46 | V | | External TSSI input | TSSI | 0.15 | – | 0.95 | V | | Internal POR threshold | Vth_POR | 0.4 | – | 0.7 | V | | Other Digital I/O Pins | | For VDDIO = 1.8 V: | | Input high voltage | VIH | 0.65 × VDDIO | – | – | V | | Input low voltage | VIL | – | – | 0.35 × VDDIO | V | | Output high voltage @ 2 mA | VOH | VDDIO – 0.45 | – | – | V | | Output low voltage @ 2 mA | VOL | – | – | 0.45 | V | | For VDDIO = 3.3V: | | Input high voltage | VIH | 2.00 | – | – | V | | Input low voltage | VIL | – | – | 0.80 | V | | Output high voltage @ 2 mA | VOH | VDDIO – 0.4 | – | – | V | | Output low Voltage @ 2 mA | VOL | – | – | 0.40 | V | | RF Switch Control Output Pins3 | | For VDDIO_RF = 3.3 V: | | Output high voltage @ 2 mA | VOH | VDDIO – 0.4 | – | – | V | | Output low voltage @ 2 mA | VOL | – | – | 0.40 | V | | Output capacitance | COUT | – | – | 5 | pF |

^1. The CYW43455 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3.2 V < VBAT < 4.8 V.

Document Number: 002-15051 Rev. *O Page 71 of 121

^2. The maximum continuous voltage is 5.25 V.

^3. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.

14. Bluetooth RF Specifications

Note: Values in this data sheet are design goals and are subject to change based on device characterization results.

Unless otherwise stated, limit values apply for the conditions specified in Table 26 and Table 28. Typical values apply for the following conditions:

• VBAT = 3.6 V
• Ambient temperature +25°C

Note: All Bluetooth specifications are measured at the chip port, unless otherwise defined.

Note: The specifications in Table 28 are measured at the chip port input, unless otherwise defined.

Table 29. Bluetooth Receiver RF Specifications

Parameter	Conditions	Minimum	Typical	Maximum	Unit
General
Frequency range	–	2402	–	2480	MHz
RX sensitivity1	GFSK, 0.1% BER, 1 Mbps	–	–93.5	–	dBm
	/4-DQPSK, 0.01% BER, 2 Mbps	–	–95.5	–	dBm
	8-DPSK, 0.01% BER, 3 Mbps	–	–89.5	–	dBm
Input IP3	–	–16	–	–	dBm
Maximum input at RF port	–	–	–	–20	dBm
RX LO Leakage
2.4 GHz band	–	–	–	–90	dBm
Interference Performance2
C/I co-channel	GFSK, 0.1% BER	–	–	11	dB
C/I 1 MHz adjacent channel	GFSK, 0.1% BER	–	–	0	dB
C/I 2 MHz adjacent channel	GFSK, 0.1% BER	–	–	–30	dB
C/I  3 MHz adjacent channel	GFSK, 0.1% BER	–	–	–40	dB
C/I image channel	GFSK, 0.1% BER	–	–	–9	dB

Document Number: 002-15051 Rev. *O Page 72 of 121

Table 29. Bluetooth Receiver RF Specifications (continued)

Parameter	Conditions	Minimum	Typical	Maximum	Unit
C/I 1-MHz adjacent to image channel	GFSK, 0.1% BER	–	–	–20	dB
C/I co-channel	/4-DQPSK, 0.1% BER	–	–	13	dB
C/I 1 MHz adjacent channel	/4-DQPSK, 0.1% BER	–	–	0	dB
C/I 2 MHz adjacent channel	/4-DQPSK, 0.1% BER	–	–	–30	dB
C/I  3 MHz adjacent channel	/4-DQPSK, 0.1% BER	–	–	–40	dB
C/I image channel	/4-DQPSK, 0.1% BER	–	–	–7	dB
C/I 1 MHz adjacent to image channel	/4-DQPSK, 0.1% BER	–	–	–20	dB
C/I co-channel	8-DPSK, 0.1% BER	–	–	21	dB
C/I 1 MHz adjacent channel	8-DPSK, 0.1% BER	–	–	5	dB
C/I 2 MHz adjacent channel	8-DPSK, 0.1% BER	–	–	–25	dB
C/I  3 MHz adjacent channel	8-DPSK, 0.1% BER	–	–	–33	dB
C/I Image channel	8-DPSK, 0.1% BER	–	–	0	dB
C/I 1 MHz adjacent to image channel	8-DPSK, 0.1% BER	–	–	–13	dB
Out-of-Band Blocking Performance (CW)
30–2000 MHz	0.1% BER	–	–10	–	dBm
2000–2399 MHz	0.1% BER	–	–27	–	dBm
2498–3000 MHz	0.1% BER	–	–27	–	dBm
3000 MHz–12.75 GHz	0.1% BER	–	–10	–	dBm
Out-of-Band Blocking Performance, Modulated Interferer
	GFSK (1 Mbps) 3
698–716 MHz	WCDMA	–	–14	–	dBm
776–849 MHz	WCDMA	–	–14	–	dBm
824–849 MHz	GSM850	–	–14	–	dBm
824–849 MHz	WCDMA	–	–14	–	dBm
880–915 MHz	E-GSM	–	–13	–	dBm
880–915 MHz	WCDMA	–	–13	–	dBm
1710–1785 MHz	GSM1800	–	–18	–	dBm
1710–1785 MHz	WCDMA	–	–17	–	dBm
1850–1910 MHz	GSM1900	–	–20	–	dBm
1850–1910 MHz	WCDMA	–	–19	–	dBm
1880–1920 MHz	TD-SCDMA	–	–20	–	dBm
1920–1980 MHz	WCDMA	–	–20	–	dBm
2010–2025 MHz	TD–SCDMA	–	–20	–	dBm
2500–2570 MHz	WCDMA	–	–23	–	dBm
2500–2570 MHz4	Band 7	–	–25	–	dBm
2300–2400 MHz5	Band 40	–	–35.2	–	dBm
2570–2620 MHz6	Band 38	–	–21	–	dBm
2545–2575 MHz7	XGP Band	–	–22	–	dBm
	/4-DPSK (2 Mbps) 3
698–716 MHz	WCDMA	–	–10	–	dBm
776–794 MHz	WCDMA	–	–10	–	dBm

Table 29. Bluetooth Receiver RF Specifications (continued)

Parameter	Conditions	Minimum	Typical	Maximum	Unit
824–849 MHz	WCDMA	–	–11	–	dBm
880–915 MHz	E-GSM	–	–10	–	dBm
880–915 MHz	WCDMA	–	–10	–	dBm
1710–1785 MHz	GSM1800	–	–16	–	dBm
1710–1785 MHz	WCDMA	–	–16	–	dBm
1850–1910 MHz	GSM1900	–	–17	–	dBm
1850–1910 MHz	WCDMA	–	–16	–	dBm
1880–1920 MHz	TD-SCDMA	–	–18	–	dBm
1920–1980 MHz	WCDMA	–	–17	–	dBm
2010–2025 MHz	TD-SCDMA	–	–19	–	dBm
2500–2570 MHz	WCDMA	–	–23	–	dBm
2500–2570 MHzd	Band 7	–	–24.4	–	dBm
2300–2400 MHze	Band 40	–	–36.5	–	dBm
2570–2620 MHzf	Band 38	–	–21	–	dBm
2545–2575 MHzg	XGP Band	–	–22	–	dBm
	8-DPSK (3 Mbps) 3
698-716 MHz	WCDMA	–	–13	–	dBm
776-794 MHz	WCDMA	–	–13	–	dBm
824-849 MHz	GSM850	–	–13	–	dBm
824-849 MHz	WCDMA	–	–14	–	dBm
880-915 MHz	E-GSM	–	–13	–	dBm
880-915 MHz	WCDMA	–	–13	–	dBm
1710-1785 MHz	GSM1800	–	–18	–	dBm
1710-1785 MHz	WCDMA	–	–17	–	dBm
1850-1910 MHz	GSM1900	–	–19	–	dBm
1850-1910 MHz	WCDMA	–	–19	–	dBm
1880-1920 MHz	TD-SCDMA	–	–19	–	dBm
1920-1980 MHz	WCDMA	–	–19	–	dBm
2010-2025 MHz	TD-SCDMA	–	–20	–	dBm
2500-2570 MHz	WCDMA	–	–23	–	dBm
2500–2570 MHzd	Band 7	–	–24.7	–	dBm
2300–2400 MHze	Band 40	–	–36.7	–	dBm
2570–2620 MHzf	Band 38	–	–21	–	dBm
2545–2575 MHzg	XGP Band	–	–22	–	dBm

Table 29. Bluetooth Receiver RF Specifications (continued)

Parameter	Conditions	Minimum	Typical	Maximum	Unit
Spurious Emissions
30 MHz-1 GHz		_	-95	-62	dBm
1–12.75 GHz		_	-70	-4 7	dBm
851–894 MHz		-	-147	-	dBm/Hz
925–960 MHz		_	-147	_	dBm/Hz
1805–1880 MHz		_	-147	_	dBm/Hz
1930–1990 MHz		_	-147	-	dBm/Hz
2110–2170 MHz		_	-147	-	dBm/Hz

• 1. Dirty TX is off.
• 1. The maximum value represents the actual Bluetooth specification required for Bluetooth qualification as defined in the version 4.1 specification.
• 3.3 dB receiver desense.
• 1. 2560 MHz performance is used.
• 1. 2360 MHz performance is used.
• 1. 2580 MHz performance is used.
• 1. 2555 MHz performance is used.

Table 30. Bluetooth Transmitter RF Specifications

Parameter	Conditions	Minimum	Typical	Maximum	Unit
Note: The specifications in this table are	e measured at the Bluetooth chip port ou	tput, unless	otherwise de	fined.
General
Frequency range		2402	_	2480	MHz
Basic rate (GFSK) TX power at Bluetoo	oth	_	12	_	dBm
QPSK TX Power at Bluetooth		_	8	-	dBm
8PSK TX Power at Bluetooth		_	8	_	dBm
Power control step	_	2	4	8	dB
Note: Output power is with TCA and TS	SI enabled.
GFSK In-Band Spurious Emissions
-20 dBc BW	_	_	0.93	1	MHz
EDR In-Band Spurious Emissions
1.0 MHz < M – N < 1.5 MHz	M – N = the frequency range for which	_	-38	-26	dBc
1.5 MHz < M – N < 2.5 MHz	the spurious emission is measured relative to the transmit center frequency.	_	-31	-20	dBm
$ M-N \geq 2.5 ; MHz^1$	,	_	-43	-40	dBm
Out-of-Band Spurious Emissions
30 MHz to 1 GHz	_	_	-	-36 2, 3	dBm
1 GHz to 12.75 GHz	_	_	-	-30 b, 4, 5	dBm
1.8 GHz to 1.9 GHz	_	_	-	-4 7	dBm
5.15 GHz to 5.3 GHz	_	_		-4 7	dBm
GPS Band Spurious Emissions
Spurious emissions	_	_	-103	_	dBm

Document Number: 002-15051 Rev. *O

Table 30. Bluetooth Transmitter RF Specifications (continued)

Parameter	Conditions	Minimum	Typical	Maximum	Unit
Out-of-Band Noise Floor 6
65–108 MHz	FM RX	–	–147	–	dBm/Hz
776–794 MHz	CDMA2000	–	–146	–	dBm/Hz
869–960 MHz	cdmaOne, GSM850	–	–146	–	dBm/Hz
925–960 MHz	E-GSM	–	–146	–	dBm/Hz
1570–1580 MHz	GPS	–	–146	–	dBm/Hz
1805–1880 MHz	GSM1800	–	–144	–	dBm/Hz
1930–1990 MHz	GSM1900, cdmaOne, WCDMA	–	–143	–	dBm/Hz
2110–2170 MHz	WCDMA	–	–137	–	dBm/Hz
2500–2570 MHz	Band 7	–	–130	–	dBm/Hz
2300–2400 MHz	Band 40	–	–130	–	dBm/Hz
2570–2620 MHz	Band 38	–	–132	–	dBm/Hz
2545–2575 MHz	XGP Band	–	–135	–	dBm/Hz

• 1. The typical number is measured at ± 3 MHz offset.
• 1. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification.
• 1. The spurious emissions during Idle mode are the same as specified in Table 30.
• 1. Specified at the Bluetooth Antenna port.
• 1. Meets this specification using a front-end band-pass filter.
• 1. Transmitted power in cellular and FM bands at the antenna port. See Figure 29 for location of the port.

Table 31. Local Oscillator Performance

Parameter	Minimum	Typical	Maximum	Unit
LO Performance
Lock time	–	72	–	µs
Initial carrier frequency tolerance	–	±25	±75	kHz
Frequency Drift
DH1 packet	–	±8	±25	kHz
DH3 packet	–	±8	±40	kHz
DH5 packet	–	±8	±40	kHz
Drift rate	–	5	20	kHz/50 µs
Frequency Deviation
00001111 sequence in payload1	140	155	175	kHz
10101010 sequence in payload2	115	140	–	kHz
Channel spacing	–	1	–	MHz

^1. This pattern represents an average deviation in payload.

Document Number: 002-15051 Rev. *O Page 76 of 121

^2. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations.

Table 32. BLE RF Specifications

Parameter	Conditions	Minimum	Typical	Maximum	Unit
Frequency range	–	2402	–	2480	MHz
RX sense1	GFSK, 0.1% BER, 1 Mbps	–	–96.5	–	dBm
TX power2	–	–	8.5	–	dBm
Mod Char: delta F1 average	–	225	255	275	kHz
Mod Char: delta F2 max.3	–	230	–	–	%
Mod Char: ratio	–	0.8	1	–	%

^1. Dirty TX is Off.

^2. The BLE TX power cannot exceed 10 dBm EIRP specification limit. The front-end losses and antenna gain/loss must be factored in so as not to exceed the limit.

^3. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz.

15. WLAN RF Specifications

15.1 Introduction

The CYW43455 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This section describes the RF characteristics of the 2.4 GHz and 5 GHz radio.

Note: Values in this section of the data sheet are design goals and are subject to change based on device characterization results. Unless otherwise stated, limit values apply for the conditions specified in Table 26 and Table 28. Typical values apply for the following conditions:

• VBAT = 3.6 V
• Ambient temperature +25°C

Optional Filter BT 2G LNA 5G LNA 2G 5G PA Diplexer Chip Port Antenna Port Antenna Port 2.4G Configured with iTR RF Port Optional Filter BT PA 2G PA LNA 5G LNA 2G 5G PA Diplexer RF Port Chip Port 2.4G Configured with eTR Chip Port Chip Port Chip Port Chip Port Chip Port Chip Port RF Port 4345XCT-DS1X15_f_040_1

Figure 30. Port Locations for WLAN Testing

Note: Unless otherwise defined, all WLAN specifications are provided at the chip port.

15.2 2.4 GHz Band General RF Specifications

Table 33. 2.4 GHz Band General RF Specifications

Item	Condition	Minimum	Typical	Maximum	Unit
TX/RX switch time	Including TX ramp down	–	–	5	µs
RX/TX switch time	Including TX ramp up	–	–	2	µs
Power-up and power-down ramp time	DSSS/CCK modulations	–	–	<2	µs

15.3 WLAN 2.4 GHz Receiver Performance Specifications

Note: The specifications shown in the following table are provided at the chip port, unless otherwise defined.

Table 34. WLAN 2.4 GHz Receiver Performance Specifications

Frequency range – 2400 – 2500 MHz RX sensitivity IEEE 802.11b 1 Mbps DSSS – –98.7 – dBm (8% PER for 1024 octet PSDU) 2 Mbps DSSS – –96.0 – dBm 5.5 Mbps DSSS – –94.4 – dBm 11 Mbps DSSS – –90.7 – dBm RX sensitivity IEEE 802.11g 6 Mbps OFDM – –95.3 – dBm (10% PER for 1024 octet PSDU) 9 Mbps OFDM – –94.3 – dBm 12 Mbps OFDM – –93.5 – dBm 18 Mbps OFDM – –90.9 – dBm 24 Mbps OFDM – –87.7 – dBm 36 Mbps OFDM – –84.4 – dBm 48 Mbps OFDM – –79.6 – dBm 54 Mbps OFDM – –78.2 – dBm RX sensitivity IEEE 802.11n 20 MHz channel spacing for all MCS rates (10% PER for 4096 octet PSDU) MCS0 – –94.8 – dBm 1 Defined for default parameters: MCS1 – –92.3 – dBm 800 ns GI and non-STBC. MCS2 – –89.8 – dBm MCS3 – –86.4 – dBm MCS4 – –83.3 – dBm MCS5 – –78.6 – dBm MCS6 – –76.7 – dBm MCS7 – –74.7 – dBm RX sensitivity IEEE 802.11ac 20 MHz channel spacing for all MCS rates (10% PER for 4096 octet PSDU) MCS0 – –95.0 – dBm 2 Defined for default parameters: MCS1 – –92.3 – dBm 800 ns GI and non-STBC MCS2 – –90.1 – dBm MCS3 – –87.0 – dBm MCS4 – –83.6 – dBm MCS5 – –78.7 – dBm MCS6 – –76.8 – dBm MCS7 – –75.9 – dBm MCS8 – –71.5 – dBm RX sensitivity IEEE 802.11ac with 20 MHz channel spacing for all MCS rates LDPC (10% PER for 4096 octet MCS7 – –77.8 – dBm PSDU) at RF port. Defined for default parameters: 800 ns GI, MCS8 – –74.0 – dBm LDPC coding, and non-STBC. MCS9 – –72.0 – dBm	Parameter	Condition/Notes	Minimum	Typical	Maximum	Unit

Table 34. WLAN 2.4 GHz Receiver Performance Specifications (continued)

| Parameter | Condition/Notes | Minimum | Typical | Maximum | Unit | |----------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------|---------|---------|---------|------|--|--| | Blocking level for 3 dB RX sensi | 776–794 MHz (CDMA2000): | | tivity degradation (without
external filtering)3 | Blocker frequency = 794 MHz | – | –16 | – | dBm | | | 824–849 MHz4 (cdmaOne): | | | Blocker frequency = 849 MHz | – | –11 | – | dBm | | | 824–849 MHz (GSM850): | | | Blocker frequency = 849 MHz | – | –11 | – | dBm | | | 880–915 MHz (E-GSM): | | | Blocker frequency = 915 MHz | – | –11 | – | dBm | | | 1710–1785 MHz (GSM1800): | | | Blocker frequency = 1785 MHz | – | –12 | – | dBm | | | 1850–1910 MHz (GSM1900): | | | Blocker frequency = 1910 MHz | – | –13 | – | dBm | | | 1850–1910 MHz (cdmaOne): | | | Blocker frequency = 1910 MHz | – | –5 | – | dBm | | | 1850–1910 MHz (WCDMA): | | | Blocker frequency = 1910 MHz | – | –19 | – | dBm | | | 1920–1980 MHz (WCDMA): | | | Blocker frequency = 1980 MHz | – | –19 | – | dBm | | | 2300–2400 MHz (LTE band 40) | | | Blocker frequency = 2300 MHz | – | –29 | – | dBm | | | Blocker frequency = 2365 MHz | – | –35 | – | dBm | | | 2500–2570 MHz (LTE band 7): | | | Blocker frequency = 2505 MHz | – | –39 | – | dBm | | | Blocker frequency = 2565 MHz | – | –35 | – | dBm | | | 2570–2620 MHz (LTE band 38): | | | Blocker frequency = 2575 MHz | – | –35 | – | dBm | | | 2496-2690 MHz (LTE band 41): | | | Blocker frequency = 2501 MHz | – | –42 | – | dBm | | | Blocker frequency = 2685 MHz | – | –17 | – | dBm | | | 2545–2575 MHz (XGP Band): | | | Blocker frequency = 2550 MHz | – | –33 | – | dBm | | In-band static CW jammer
immunity
(fc – 8 MHz < fcw < + 8 MHz) | RX PER < 1%, 54 Mbps OFDM,
1000 octet PSDU for:
(RxSens + 23 dB < Rxlevel < max. input
level) | –80 | – | – | dBm | | Input In-Band IP3 | Maximum LNA gain | – | –10 | – | dBm | | | Minimum LNA gain | – | 15 | – | dBm | | Maximum Receive Level | @ 1, 2 Mbps (8% PER, 1024 octets) | –3.5 | – | – | dBm | | @ 2.4 GHz | @ 5.5, 11 Mbps (8% PER, 1024 octets) | –9.5 | – | – | dBm | | | @ 6–54 Mbps (10% PER, 1024 octets) | –9.5 | – | – | dBm | | | @ MCS0–MCS7 rates (10% PER, 4095
octets) | –9.5 | – | – | dBm | | | @ MCS8–MCS9 rates (10% PER, 4095
octets) | –11.5 | – | – | dBm |

Table 34. WLAN 2.4 GHz Receiver Performance Specifications (continued)

Parameter	Condition/Notes		Minimum	Typical	Maximum	Unit
Adjacent channel rejection-DSSS		Desired and interfering signal 30 MHz apart
(Difference between interfering	1 Mbps DSSS	–74 dBm	35	–	–	dB
and desired signal at 8% PER for 1024 octet PSDU with desired	2 Mbps DSSS	–74 dBm	35	–	–	dB
signal level as specified in		Desired and interfering signal 25 MHz apart
Condition/Notes)	5.5 Mbps DSSS	–70 dBm	35	–	–	dB
	11 Mbps DSSS	–70 dBm	35	–	–	dB
Adjacent channel rejection-OFDM (Difference between interfering and desired signal (25 MHz apart)	6 Mbps OFDM	–79 dBm	16	–	–	dB
	9 Mbps OFDM	–78 dBm	15	–	–	dB
	12 Mbps OFDM	–76 dBm	13	–	–	dB
at 10% PER for 1024 octet PSDU	18 Mbps OFDM	–74 dBm	11	–	–	dB
with desired signal level as specified in Condition/Notes)	24 Mbps OFDM	–71 dBm	8	–	–	dB
	36 Mbps OFDM	–67 dBm	4	–	–	dB
	48 Mbps OFDM	–63 dBm	0	–	–	dB
	54 Mbps OFDM	–62 dBm	–1	–	–	dB
Adjacent channel rejection	MCS0	–79 dBm	16	–	–	dB
MCS0–MCS9 (Difference between interfering and desired	MCS1	–76 dBm	13	–	–	dB
signal (25 MHz apart) at 10% PER	MCS2	–74 dBm	11	–	–	dB
for 4096 octet PSDU with desired signal level as specified in	MCS3	–71 dBm	8	–	–	dB
Condition/Notes)	MCS4	–67 dBm	4	–	–	dB
	MCS5	–63 dBm	0	–	–	dB
	MCS6	–62 dBm	–1	–	–	dB
	MCS7	–61 dBm	–2	–	–	dB
	MCS8	–59 dBm	–4	–	–	dB
	MCS9	–57 dBm	–6	–	–	dB
Maximum receiver gain	–	–	–	70	–	dB
Gain control step	–	–	–	3	–	dB
RSSI accuracy5	Range –956 dBm to –30 dBm		–5	–	5	dB
	Range above –30 dBm		–8	–	8	dB
Return loss	Zo = 50Ω, across the dynamic range		10	11.5	13	dB
Receiver cascaded noise figure	At maximum gain		–	4	–	dB

^1. Sensitivity degradations for alternate settings in MCS modes. SGI: 2 dB drop.

^2. Sensitivity degradations for alternate settings in MCS modes. SGI: 2 dB drop.

^3. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country.

^4. The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to third harmonic signals (3 × 824 MHz) falling within band.)

^5. The minimum and maximum values shown have a 95% confidence level.

^{6. –95} dBm with calibration at time of manufacture, –92 dBm without calibration.

15.4 WLAN 2.4 GHz Transmitter Performance Specifications

Note: Unless otherwise noted, the values shown in the following table are provided at the WLAN chip port output.

Table 35. WLAN 2.4 GHz Transmitter Performance Specifications

Parameter	Condition/Notes	Minimum	Typical	Maximum	Unit
Frequency range	–	2400	–	2500	MHz
Transmitted power in cellular and	776-794 MHz (CDMA2000)	–	–164	–	dBm/Hz
FM bands (at +21 dBm, 100% duty cycle, 1 Mbps CCK) 1	869–960 MHz (cdmaOne, GSM850)	–	–163	–	dBm/Hz
	1450–1495 (DAB)	–	–153.6	–	dBm/Hz
	1570–1580 MHz (GPS)	–	–151.2	–	dBm/Hz
	1592–1610 MHz (GLONASS)	–	–150.4	–	dBm/Hz
	1710–1800 (DSC-1800-Uplink)	–	–145	–	dBm/Hz
	1805–1880 MHz (GSM 1800)	–	–139	–	dBm/Hz
	1850–1910 MHz (GSM 1900)	–	–139	–	dBm/Hz
	1910–1930 MHz (TDSCDMA,LTE)	–	–140	–	dBm/Hz
	1930–1990 MHz (GSM1900, cdmaOne, WCDMA)	–	–128	–	dBm/Hz
	2010–2075 MHz (TDSCDMA)	–	–131	–	dBm/Hz
	2110–2170 MHz (WCDMA)	–	–125	–	dBm/Hz
	2305–2370 (LTE band 40)	–	–95	–	dBm/Hz
	2370–2400 (LTE band 40)	–	–80	–	dBm/Hz
	2496-2530 (LTE band 41)	–	–90	–	dBm/Hz
	2530-2560 (LTE band 41)	–	–110	–	dBm/Hz
	2570-2690 (LTE band 41)	–	–116	–	dBm/Hz
	5000-5900 (WLAN 5G)	–	–155	–	dBm/Hz
	EVM Does Not Exceed
TX power at the chip port for highest power level setting at 25°C	802.11b –9 dB (DSSS/CCK)	–	20.5	–	dBm
and VBAT = 3.6V with spectral mask and EVM compliance	OFDM, BPSK –8 dB	–	20	–	dBm
	OFDM, 64QAM –25 dB	–	19	–	dBm
	MCS7 –27 dB	–	19	–	dBm
	MCS8 –30 dB	–	17	–	dBm
Phase noise	37.4 MHz crystal, integrated from 10 kHz to 10 MHz	–	0.45	–	Degrees
TX power control dynamic range	–	10	–	–	dB
Closed-loop TX power variation at highest power level setting	Across full temperature and voltage range. Applies to 10 dBm to 20 dBm output power range.	–	–	±1.5	dB
Carrier suppression	–	15	–	–	dBc
Gain control step	–	–	0.25	–	dB
Return loss at Chip port TX	Zo = 50Ω	–	6	–	dB

^1. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands.

Document Number: 002-15051 Rev. *O Page 82 of 121

15.5 WLAN 5 GHz Receiver Performance Specifications

Note: Unless otherwise noted, the values shown in the following table are provided at the chip port input.

Table 36. WLAN 5 GHz Receiver Performance Specifications

Parameter	Condition/Notes	Minimum	Typical	Maximum	Unit
Frequency range	–	4900	–	5845	MHz
RX sensitivity 1 IEEE 802.11a (10%	6 Mbps OFDM	–	–94.5	–	dBm
PER for 1000 octet PSDU)	9 Mbps OFDM	–	–93.5	–	dBm
	12 Mbps OFDM	–	–92.7	–	dBm
	18 Mbps OFDM	–	–90.1	–	dBm
	24 Mbps OFDM	–	–86.9	–	dBm
	36 Mbps OFDM	–	–83.6	–	dBm
	48 Mbps OFDM	–	–78.6	–	dBm
	54 Mbps OFDM	–	–77.4	–	dBm
RX sensitivity 1 IEEE 802.11n (10%	20 MHz channel spacing for all MCS rates
PER for 4096 octet PSDU)	MCS0	–	–94.0	–	dBm
Defined for default parameters: 800 ns GI and non-STBC.	MCS1	–	–91.5	–	dBm
	MCS2	–	–89.0	–	dBm
	MCS3	–	–85.6	–	dBm
	MCS4	–	–82.5	–	dBm
	MCS5	–	–77.8	–	dBm
	MCS6	–	–75.9	–	dBm
	MCS7	–	–73.9	–	dBm
RX sensitivity 1 IEEE 802.11n (10%	40 MHz channel spacing for all MCS rates
PER for 4096 octet PSDU)	MCS0	–	–92.0	–	dBm
Defined for default parameters: 800 ns GI and non-STBC.	MCS1	–	–89.0	–	dBm
	MCS2	–	–86.5	–	dBm
	MCS3	–	–83.2	–	dBm
	MCS4	–	–79.9	–	dBm
	MCS5	–	–75.3	–	dBm
	MCS6	–	–73.8	–	dBm
	MCS7	–	–72.2	–	dBm
RX sensitivity 1 IEEE 802.11ac	20 MHz channel spacing for all MCS rates
(10% PER for 4096 octet PSDU)	MCS0	–	–94.2	–	dBm
Defined for default parameters: 800 ns GI and non-STBC.	MCS1	–	–91.5	–	dBm
	MCS2	–	–89.3	–	dBm
	MCS3	–	–86.2	–	dBm
	MCS4	–	–82.8	–	dBm
	MCS5	–	–77.9	–	dBm
	MCS6	–	–76.0	–	dBm
	MCS7	–	–75.1	–	dBm
	MCS8	–	–70.7	–	dBm

Table 36. WLAN 5 GHz Receiver Performance Specifications (continued)

| Parameter | | Condition/Notes | Minimum | Typical | Maximum | Unit | |----------------------------------------------------------------------------------------------------------------------------------|------------------------------------------|------------------------------------------|---------|---------|---------|------|--|--| | RX sensitivity 1 IEEE
802.11ac | | 40 MHz channel spacing for all MCS rates | | (10% PER for 4096 octet PSDU) | MCS0 | | – | –92.3 | – | dBm | | Defined for default parameters:
800 ns GI and non-STBC. | MCS1 | | – | –89.3 | – | dBm | | | MCS2 | | – | –86.9 | – | dBm | | | MCS3 | | – | –83.6 | – | dBm | | | MCS4 | | – | –80.2 | – | dBm | | | MCS5 | | – | –75.6 | – | dBm | | | MCS6 | | – | –74.0 | – | dBm | | | MCS7 | | – | –72.6 | – | dBm | | | MCS8 | | – | –68.3 | – | dBm | | | MCS9 | | – | –66.7 | – | dBm | | RX sensitivity 1 IEEE
802.11ac
(10% PER for 4096 octet PSDU)
Defined for default parameters: 800
ns GI and non-STBC. | 80 MHz channel spacing for all MCS rates | | | MCS0 | | – | –89.0 | – | dBm | | | MCS1 | | – | –86.0 | – | dBm | | | MCS2 | | | –83.3 | – | dBm | | | MCS3 | | – | –80.1 | – | dBm | | | MCS4 | | – | –76.8 | – | dBm | | | MCS5 | | – | –72.2 | – | dBm | | | MCS6 | | – | –70.9 | – | dBm | | | MCS7 | | – | –69.2 | – | dBm | | | MCS8 | | – | –65.2 | – | dBm | | | MCS9 | | – | –63.6 | – | dBm | | RX sensitivity 1 IEEE
802.11ac | MCS7 | 20 MHz | – | –76.8 | – | dBm | | 20/40/80 MHz channel spacing with
LDPC (10% PER for 4096 octet | MCS8 | 20 MHz | – | –72.9 | – | dBm | | PSDU) at RF port. | MCS9 | 20 MHz | – | –70.7 | – | dBm | | Defined for default parameters: 800 | MCS7 | 40 MHz | – | –74.8 | – | dBm | | ns GI, LDPC coding and non-STBC. | MCS8 | 40 MHz | – | –70.9 | – | dBm | | | MCS9 | 40 MHz | – | –68.9 | – | dBm | | | MCS7 | 80 MHz | – | –71.5 | – | dBm | | | MCS8 | 80 MHz | – | –67.6 | – | dBm | | | MCS9 | 80 MHz | – | –65.5 | – | dBm |

Table 36. WLAN 5 GHz Receiver Performance Specifications (continued)

| Parameter | Condition/Notes | Minimum | Typical | Maximum | Unit | |--------------------------------------------------|------------------------------|---------|---------|---------|------|--|--|--|--| | Blocking level for 3 dB RX sensitivity | 776–794 MHz (CDMA2000): | | degradation (without external
filtering)2 | Blocker frequency = 794 MHz | – | –21 | – | dBm | | | 824–849 MHz3 (cdmaOne): | | | Blocker frequency = 849 MHz | – | –20 | – | dBm | | | 824–849 MHz (GSM850): | | | Blocker frequency = 849 MHz | – | –10 | – | dBm | | | 880–915 MHz (E-GSM): | | | Blocker frequency = 915 MHz | – | –12 | – | dBm | | | 1710–1785 MHz (GSM1800): | | | Blocker frequency = 1785 MHz | – | –13 | – | dBm | | | 1850–1910 MHz (GSM1900): | | | Blocker frequency = 1910 MHz | – | –13 | – | dBm | | | 1850–1910 MHz (cdmaOne): | | | Blocker frequency = 1910 MHz | – | –18 | – | dBm | | | 1850–1910 MHz (WCDMA): | | | Blocker frequency = 1910 MHz | – | –20 | – | dBm | | | 1920–1980 MHz (WCDMA): | | | Blocker frequency = 1980 MHz | – | –20 | – | dBm | | | 2300–2400 MHz (LTE band 40) | | | Blocker frequency = 2395 MHz | – | –19 | – | dBm | | | 2500–2570 MHz (LTE band 7): | | | Blocker frequency = 2565 MHz | – | –16 | – | dBm | | | 2570–2620 MHz (LTE band 38): | | | Blocker frequency = 2615 MHz | – | –16 | – | dBm | | | 2496-2690 MHz (LTE band 41): | | | Blocker frequency = 2685 MHz | – | –16 | – | dBm | | | 2545–2575 MHz (XGP Band): | | | Blocker frequency = 2570 MHz | – | –18 | – | dBm | | Input In-Band IP3 | Maximum LNA gain | – | –11 | – | dBm | | | Minimum LNA gain | – | 5 | – | dBm | | Maximum receive level @ 5.24 GHz @ 6, 9, 12 Mbps | | –9.5 | – | – | dBm | | | @ 18, 24, 36, 48, 54 Mbps | –14.5 | – | – | dBm |

Table 36. WLAN 5 GHz Receiver Performance Specifications (continued)

Parameter		Condition/Notes	Minimum	Typical	Maximum	Unit
Adjacent channel rejection	6 Mbps OFDM	–79 dBm	16	–	–	dB
(Difference between interfering and	9 Mbps OFDM	–78 dBm	15	–	–	dB
desired signal (20 MHz apart) at 10% PER for 1000 octet PSDU with desired signal level as specified in	12 Mbps OFDM	–76 dBm	13	–	–	dB
Condition/Notes)	18 Mbps OFDM	–74 dBm	11	–	–	dB
	24 Mbps OFDM	–71 dBm	8	–	–	dB
	36 Mbps OFDM	–67 dBm	4	–	–	dB
	48 Mbps OFDM	–63 dBm	0	–	–	dB
	54 Mbps OFDM	–62 dBm	–1	–	–	dB
	65 Mbps OFDM	–61 dBm	–2	–	–	dB
Alternate adjacent channel rejection	6 Mbps OFDM	–78.5 dBm	32	–	–	dB
(Difference between interfering and	9 Mbps OFDM	–77.5 dBm	31	–	–	dB
desired signal (40 MHz apart) at 10% PER for 10004 octet PSDU with desired signal level as specified in	12 Mbps OFDM	–75.5 dBm	29	–	–	dB
Condition/Notes)	18 Mbps OFDM	–73.5 dBm	27	–	–	dB
	24 Mbps OFDM	–70.5 dBm	24	–	–	dB
	36 Mbps OFDM	–66.5 dBm	20	–	–	dB
	48 Mbps OFDM	–62.5 dBm	16	–	–	dB
	54 Mbps OFDM	–61.5 dBm	15	–	–	dB
	65 Mbps OFDM	–60.5 dBm	14	–	–	dB
Maximum receiver gain	–		–	65	–	dB
Gain control step	–		–	3	–	dB
RSSI accuracy5	Range –98 dBm to –30 dBm		–5	–	5	dB
	Range above –30 dBm		–8	–	8	dB
Return loss	Zo = 50Ω, across the dynamic range		10	–	13	dB
Receiver cascaded noise figure	At maximum gain		–	4	–	dB

^1. For PCIE derate 5G RX sensitivity by 1.5 dB

^2. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country.

^3. The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to third harmonic signals (3 × 824 MHz) falling within band.)

^4. For 65 Mbps, the size is 4096.

^5. The minimum and maximum values shown have a 95% confidence level.

15.6 WLAN 5 GHz Transmitter Performance Specifications

Note: Unless otherwise noted, the values shown in the following table are provided at the WLAN chip port output.

Table 37. WLAN 5 GHz Transmitter Performance Specifications

Parameter	Condition/Notes	Minimum	Typical	Maximum	Unit
Frequency range	–	4900	–	5845	MHz
Transmitted power in cellular and FM	776–794 MHz (CDMA2000)	–	–164	–	dBm/Hz
bands (at +18.5 dBm, 100% duty cycle, 6 Mbps OFDM) 1	869–960 MHz (cdmaOne, GSM850)	–	–166	–	dBm/Hz
	1450–1495 (DAB)	–	–166	–	dBm/Hz
	1570–1580 MHz (GPS)	–	–166	–	dBm/Hz
	1592–1610 MHz (GLONASS)	–	–165.5	–	dBm/Hz
	1710–1800(DSC-1800-Uplink)	–	–135	–	dBm/Hz
	1805–1880 MHz (GSM 1800)	–	–165	–	dBm/Hz
	1850–1910 MHz (GSM 1900)	–	–165	–	dBm/Hz
	1910–1930 MHz (TDSCDMA, LTE)	–	–165	–	dBm/Hz
	1930–1990 MHz (GSM1900, cdmaOne, WCDMA)	–	–165	–	dBm/Hz
	2010–2075 MHz (TDSCDMA)	–	–164.5	–	dBm/Hz
	2110–2170 MHz (WCDMA)	–	–164	–	dBm/Hz
	2305–2370 (LTE band 40)	–	–160	–	dBm/Hz
	2370–2400 (LTE band 40)	–	–163	–	dBm/Hz
	2400–2500 (WLAN 2G)	–	–160	–	dBm/Hz
	2496–2530 (LTE band 41)	–	–161.5	–	dBm/Hz
	2530–2560 (LTE band 41)	–	–161.5	–	dBm/Hz
	2570–2690 (LTE band 41)	–	–161	–	dBm/Hz
	EVM Does Not Exceed
TX power at the chip port for highest	OFDM, BPSK –8 dB	–	21.5	–	dBm
power level setting at 25°C and VBAT = 3.6V with spectral mask and	OFDM, 64QAM –25 dB	–	19	–	dBm
EVM compliance	MCS7 –27 dB	–	19	–	dBm
	MCS9 –32 dB	–	16	–	dBm
Phase noise	37.4 MHz Crystal, Integrated from 10 kHz to 10 MHz	–	0.5	–	Degrees
TX power control dynamic range	–	10	–	–	dB
Closed loop TX power variation at highest power level setting	Across full-temperature and voltage range. Applies across 10 to 20 dBm output power range.	–	–	±2.0	dB
Carrier suppression	–	15	–	–	dBc
Gain control step	–	–	0.25	–	dB
Return loss	Zo = 50Ω	–	6	–	dB

^1. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands.

Document Number: 002-15051 Rev. *O Page 87 of 121

15.7 General Spurious Emissions Specifications

This section provides the TX and RX spurious emissions specifications for both the WLAN 2.4 GHz and 5 GHz bands. The recommended spectrum analyzer settings for the spurious emissions specifications are provided in Table 38.

Table 38. Recommended Spectrum Analyzer Settings

Parameter	Setting
Resolution Bandwidth (RBW):	1 MHz
Video Bandwidth (VBW):	1 MHz
Sweep:	Auto
Span:	100 MHz
Detector:	Maximum Peak
Trace:	Maximum Hold
Modulation:	OFDM (Orthogonal Frequency-division Multiplexing)

15.7.1 Transmitter Spurious Emissions Specifications

The TX spurious emissions specifications in this subsection are based on the following definitions:

• AFE = VCO/16 for 2G channels
• AFE = VCO/18 for 5G 20 MHz channels
• AFE = VCO/9 for 5G 40 MHz channels
• AFE = VCO/6 for 5G 80 MHz channels
• LO = Channel frequency

2.4 GHz Band Spurious Emissions

20 MHz Channel Spacing

Note: Possible AFE combinations are as follows. The AFE=VCO/16 specifications for channel 2442 are listed in Table 39.

Table 39. 2.4 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications¹

			Frequency (Fch; MHz) Channel 2442
Spurious Frequency	Power (dBm)	Typical (dBm)	Maximum (dBm)
HD2	21	–22.78	–
HD3	21	–19.54	–
HD4	21	–41.79	–
HD5	21	–61.78	–
VCO – LO	21	–55.13	–
VCO + LO	21	–63.40	–
VCO	21	–48.56	–
LO + AFE	21	–59.2	–
LO-AFE	21	–59.3	–
LO + AFE × 2	21	–68.2	–
LO – AFE × 2	21	–67.4	–
LO + XTAL × 2	21	–56.2	–
LO – XTAL × 2	21	–56.3	–
LO + XTAL × 4	21	–57.5	–
LO – XTAL × 4	21	–56.7	–
LO + XTAL × 8	21	–59.1	–
LO – XTAL × 8	21	–67.2	–

^1. VCO = 1.5 × Fch, where Fch is the center frequency of the channel.

5 GHz Band Spurious Emissions

20 MHz Channel Spacing

Note: Possible AFE combinations are as follows. The AFE=VCO/18 specifications for channels 5180, 5500, and 5825 are listed in Table 40.

Table 40. 5 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications

| | | | CH51801 | CH55001 | | CH58251 | |--------------------|-------------|---------------|---------------|---------------|---------------|---------------|---------------| | Spurious Frequency | Power (dBm) | Typ.
(dBm) | Max.
(dBm) | Typ.
(dBm) | Max.
(dBm) | Typ.
(dBm) | Max.
(dBm) | | HD2 | 19 | –29.33 | – | –32.56 | – | –33.14 | – | | HD3 | 19 | –39.71 | – | –38.93 | – | –39.87 | – | | VCO | 19 | –49.03 | – | –48.35 | – | –46.70 | – | | VCO × 2 | 19 | –55.64 | – | –60.40 | – | –64.77 | – | | LO + VCO | 19 | –63.94 | – | –62.80 | – | –62.16 | – | | LO – VCO | 19 | –81.58 | – | –72.56 | – | –70.58 | – | | LO – AFE | 19 | –62.1 | – | –63.3 | – | –60.4 | – | | LO + AFE | 19 | –57.8 | – | –59.6 | – | –60.6 | – | | LO – XTAL × 4 | 19 | –60.1 | – | –60.1 | – | –58.7 | – | | LO + XTAL × 4 | 19 | –57.2 | – | –57.4 | – | –58.2 | – | | LO – XTAL × 6 | 19 | –63.4 | – | –59.3 | – | –61.1 | – | | LO + XTAL × 6 | 19 | –60.2 | – | –58.9 | – | –60.8 | – | | LO – XTAL × 8 | 19 | –66.1 | – | –67.3 | – | –63.8 | – | | LO + XTAL × 8 | 19 | –64.2 | – | –63.8 | – | –65.8 | – | | AFE × 12 | 19 | – | – | – | – | – | – |

^1. VCO = (2/3) × Fch, where Fch is the center frequency of the channel.

Document Number: 002-15051 Rev. *O Page 90 of 121

40 MHz Channel Spacing

Note: Possible AFE combinations are as follows. The AFE=VCO/9 specifications for channels 5190, 5510, and 5795 are listed in Table 41.

Table 41. 5 GHz Band, 40 MHz Channel Spacing TX Spurious Emissions Specifications

| | | | CH5190m1 | CH5510m1 | | CH5795m1 | |--------------------|-------------|---------------|---------------|---------------|---------------|---------------|---------------| | Spurious Frequency | Power (dBm) | Typ.
(dBm) | Max.
(dBm) | Typ.
(dBm) | Max.
(dBm) | Typ.
(dBm) | Max.
(dBm) | | HD2 | 19 | –33.43 | – | –35.53 | – | –36.49 | – | | HD3 | 19 | –41.81 | – | –42.13 | – | –42.33 | – | | VCO | 19 | –48.36 | – | –47.65 | – | –46.93 | – | | VCO × 2 | 19 | –55.87 | – | –59.26 | – | –64.45 | – | | LO + VCO | 19 | –65.58 | – | –64.96 | – | – | – | | LO – VCO | 19 | – | – | – | – | – | – | | LO – AFE | 19 | –65.3 | – | –67.2 | – | –65.2 | – | | LO + AFE | 19 | –63.2 | – | –64.3 | – | –67.3 | – | | LO – XTAL × 4 | 19 | –59.3 | – | –59.7 | – | –59.6 | – | | LO + XTAL × 4 | 19 | –58.3 | – | –57.4 | – | –57.9 | – | | LO – XTAL × 6 | 19 | –64.1 | – | –63.4 | – | –63.2 | – | | LO + XTAL × 6 | 19 | –61.5 | – | –59.4 | – | –61.2 | – | | LO – XTAL × 8 | 19 | –66.3 | – | –67.1 | – | –64.3 | – | | LO + XTAL × 8 | 19 | –63.8 | – | –64.7 | – | –61.2 | – | | AFE × 12 | 19 | –65.2 | – | –66.3 | – | –65.4 | – |

^1. VCO = (2/3) × Fch, where Fch is the center frequency of the channel.

80 MHz Channel Spacing

Note: Possible AFE combinations are as follows. The AFE=VCO/6 specifications for channels 5210, 5530, and 5775 are listed in Table 42.

Table 42. 5 GHz Band, 80 MHz Channel Spacing TX Spurious Emissions Specifications

| | | CH5210q1 | | CH5530q1 | | CH5775q1 | |--------------------|-------------|---------------|---------------|---------------|---------------|---------------|---------------| | Spurious Frequency | Power (dBm) | Typ.
(dBm) | Max.
(dBm) | Typ.
(dBm) | Max.
(dBm) | Typ.
(dBm) | Max.
(dBm) | | HD2 | 19 | –36.28 | – | –39.59 | – | –41.02 | – | | HD3 | 19 | –45.00 | – | –44.82 | – | –46.10 | – | | VCO | 19 | –48.00 | – | –47.34 | – | –46.01 | – | | VCO × 2 | 19 | –57.04 | – | –62.82 | – | –66.84 | – | | LO + VCO | 19 | –66.66 | – | –66.11 | – | –66.40 | – | | LO – VCO | 19 | – | – | – | – | – | – | | LO – AFE | 19 | –68.5 | – | –67.8 | – | –66.9 | – | | LO + AFE | 19 | –63.8 | – | –66.3 | – | –68.6 | – | | LO – XTAL × 4 | 19 | – | – | – | – | – | – | | LO + XTAL × 4 | 19 | – | – | – | – | – | – | | LO – XTAL × 6 | 19 | – | – | – | – | – | – | | LO + XTAL × 6 | 19 | – | – | – | – | – | – | | LO – XTAL × 8 | 19 | – | – | – | – | – | – | | LO + XTAL × 8 | 19 | – | – | – | – | – | – | | AFE × 12 | 19 | – | – | – | – | – | – |

^1. VCO = (2/3) × Fch, where Fch is the center frequency of the channel.

15.7.2 Receiver Spurious Emissions Specifications

Table 43. 2G and 5G General Receiver Spurious Emissions

Band	Frequency Range	Typical	Maximum	Unit
2G	2.4 GHz < f < 2.5 GHz	–92	–	dBm
	3.6 GHz < f < 3.8 GHz	–75.16	–	dBm
5G	5150 MHz < f < 5850 MHz	–70.4	–	dBm
	3.45 GHz < f < 3.9 GHz	–59.2	–	dBm

16. Internal Regulator Electrical Specifications

16.1 Core Buck Switching Regulator

Note: Values in this data sheet are design goals and are subject to change based on device characterization results.

Note: Functional operation is not guaranteed outside of the specification limits provided in this section.

Table 44. Core Buck Switching Regulator (CBUCK) Specifications

Specification	Notes	Min.	Typ.	Max.	Unit
Input supply voltage (DC)	DC voltage range inclusive of disturbances.	3.0	3.6	5.2516. 0	V
	PWM mode switching frequency CCM, Load > 100 mA VBAT = 3.6V	–	4	–	MHz
PWM output current	–	–	–	600	mA
Output current limit	–	–	1400	–	mA
Output voltage range	Programmable, 30 mV steps. Default = 1.35V	1.2	1.35	1.5	V
PWM output voltage DC accuracy	Includes load and line regulation. Forced PWM mode.	–4	–	4	%
PWM ripple voltage, static	Measure with 20 MHz bandwidth limit.	–	7	20	mVpp
	Static Load. Max. Ripple based on VBAT = 3.6V, Vout = 1.35V, Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH, Cap + Board total-ESR < 20 mΩ, Cout > 1.9 μF, ESL<200 pH
PWM mode peak efficiency	Peak Efficiency at 200 mA load	78	86	–	%
PFM mode efficiency	10 mA load current	70	80	–	%
Start-up time from power down	VIO already ON and steady. Time from REG_ON rising edge to CLDO reaching 1.2V.	–	400	500	μs
External inductor	0806 size, 2.2 µH, DCR=0.11Ω, ACR=1.18Ω @ 4 MHz	–	2.2	–	μH
External output capacitor	Ceramic, X5R, 0402, ESR <30 mΩ at 4 MHz, 4.7 µF ±20%, 6.3V	2.0	4.7	102	μF
External input capacitor	For SR_VDDBATP5V pin, ceramic, X5R, 0603, ESR < 30 mΩ at 4 MHz, ±4.7uF ±20%, 6.3V	0.672	4.7	–	μF
Input supply voltage ramp-up time	0 to 4.3V	40	–	–	μs

^1. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.

Document Number: 002-15051 Rev. *O Page 93 of 121

^2. Total capacitance includes those connected at the far end of the active load.

16.2 3.3V LDO (LDO3P3)

Table 45. LDO3P3 Specifications

Specification	Notes	Min.	Typ.	Max.	Units
Input supply voltage, V in	Min. = $V_0$ + 0.2V = 3.5V dropout voltage requirement must be met under maximum load for performance specifications.	3.0	3.6	5.25 1 6.0	V
Output current	_	0.001	_	450	mA
Nominal output voltage, V o	Default = 3.3V	-	3.3	_	V
Dropout voltage	At max. load.	_	_	200	mV
Output voltage DC accuracy	Includes line/load regulation.	- 5	-	+5	%
Quiescent current	No load	_	-	100	μA
Line regulation	V in from (V o + 0.2V) to 5.25V, max. load	-	_	3.5	mV/V
Load regulation	load from 1 mA to 450 mA	_	-	0.3	mV/mA
PSRR	$V_{in} \ge V_o + 0.2V$ , $V_o = 3.3V$ , $C_o = 4.7 \mu F$ , Max. load, 100 Hz to 100 kHz	20	_	_	dB
LDO turn-on time	Chip already powered up.	_	160	250	μs
External output capacitor, C o	Ceramic, X5R, 0402, (ESR: 5 mΩ-240 mΩ), ± 10%, 10V	1.0 2	4.7	10	μF
External input capacitor	For SR_VDDBATA5V pin (shared with Bandgap) Ceramic, X5R, 0402, (ESR: 30m-200 mΩ), ± 10%, 10V. Not needed if sharing VBAT capacitor 4.7 μF with SR_VDDBATP5V.	-	4.7	_	μF

^1. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.

^2. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

16.3 2.5V LDO (BTLDO2P5)

Table 46. BTLDO2P5 Specifications

Specification	Notes	Min.	Typ.	Max.	Units
Input supply voltage	Min. = 2.5V + 0.2V = 2.7V. Dropout voltage requirement must be met under maximum load for performance specifications.	3.0	3.6	5.251 6.0	V
Nominal output voltage	Default = 2.5V.	–	2.5	–	V
Output voltage programmability	Range	2.2	2.5	2.8	V
	Accuracy at any step (including line/load regulation), load > 0.1 mA.	–5	–	5	%
Dropout voltage	At maximum load.	–	–	200	mV
Output current	–	0.1	–	70	mA
Quiescent current	No load.	–	8	16	μA
	Maximum load at 70 mA.	–	660	700	μA
Leakage current	Power-down mode.	–	1.5	5	μA
Line regulation	Vin from (Vo + 0.2V) to 5.25V, maximum load.	–	–	3.5	mV/V
Load regulation	Load from 1 mA to 70 mA, Vin = 3.6V.	–	–	0.3	mV/mA
PSRR	Vin ≥ Vo + 0.2V, Vo = 2.5V, Co = 2.2 μF, maximum load, 100 Hz to 100 kHz.	20	–	–	dB
LDO turn-on time	Chip already powered up.	–	–	150	μs
In-rush current	Vin = Vo + 0.15V to 5.25V, Co = 2.2 μF, No load.	–	–	250	mA
External output capacitor, Co	Ceramic, X5R, 0402, (ESR: 5m–240 mΩ), ±10%, 10V	0.72	2.2	2.64	μF
External input capacitor	For SR_VDDBATA5V pin (shared with Bandgap) ceramic, X5R, 0402, (ESR: 30–200 mΩ), ±10%, 10V. Not needed if sharing VBAT 4.7 μF capacitor with SR_VDDBATP5V.	–	4.7	–	μF

^1. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.

^2. The minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.

16.4 CLDO

Table 47. CLDO Specifications

Specification	Notes	Min.	Typ.	Max.	Units
Input supply voltage, Vin	Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement must be met under maximum load.	1.3	1.35	1.5	V
Output current	–	0.2	–	200	mA
Output voltage, Vo	Programmable in 10 mV steps. Default = 1.2.V	0.95	1.2	1.26	V
Dropout voltage	At max. load	–	–	150	mV
Output voltage DC accuracy	Includes line/load regulation	–4	–	+4	%
Quiescent current	No load	–	13	–	μA
	200 mA load	–	1.24	–	mA
Line Regulation	Vin from (Vo + 0.15V) to 1.5V, maximum load	–	–	5	mV/V
Load Regulation	Load from 1 mA to 300 mA	–	0.02	0.05	mV/mA
Leakage Current	Power down	–	5	20	μA
	Bypass mode	–	1	3	μA
PSRR	@1 kHz, Vin ≥ 1.35V, Co = 4.7 μF	20	–	–	dB
Start-up Time of PMU	VIO up and steady. Time from the REG_ON rising edge to the CLDO reaching 1.2V.	–	–	700	μs
LDO Turn-on Time	LDO turn-on time when rest of the chip is up	–	140	180	μs
External Output Capacitor, Co	Total ESR: 5 mΩ–240 mΩ	1.11	2.2	–	μF
External Input Capacitor	Only use an external input capacitor at the VDD_LDO pin if it is not supplied from CBUCK output.	–	1	2.2	μF

^1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

16.5 LNLDO

Table 48. LNLDO Specifications

Specification	Notes	Min.	Typ.	Max.	Units
Input supply voltage, Vin	Min. VIN = VO + 0.15V = 1.35V (where VO = 1.2V)dropout voltage requirement must be met under maximum load.	1.3	1.35	1.5	V
Output Current	–	0.1	–	150	mA
Output Voltage, Vo	Programmable in 25 mV steps. Default = 1.2V	1.1	1.2	1.275	V
Dropout Voltage	At maximum load	–	–	150	mV
Output Voltage DC Accuracy	Includes line/load regulation	–4	–	+4	%
Quiescent current	No load	–	44	–	μA
	Max. load	–	970	990	μA
Line Regulation	Vin from (Vo + 0.1V) to 1.5V, 150 mA load	–	–	5	mV/V
Load Regulation	Load from 1 mA to 150 mA	–	0.02	0.05	mV/mA
Leakage Current	Power-down	–	–	10	μA
Output Noise	@30 kHz, 60–150 mA load Co = 2.2 μF @100 kHz, 60–150 mA load Co = 2.2 μF	–	–	60 35	nV/rt Hz nV/rt Hz
PSRR	@ 1kHz, Input > 1.35V, Co= 2.2 μF, Vo = 1.2V	20	–	–	dB
LDO Turn-on Time	LDO turn-on time when rest of chip is up	–	140	180	μs
External Output Capacitor, Co	Total ESR (trace/capacitor): 5 mΩ–240 mΩ	0.51	2.2	4.7	μF
External Input Capacitor	Only use an external input capacitor at the VDD_LDO pin if it is not supplied from CBUCK output. Total ESR (trace/capacitor): 30 mΩ–200 mΩ	–	1	2.2	μF

^1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

16.6 PCIe LDO

Note: The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Table 49. PCIe LDO Specifications

Specification	Notes	Min.	Typ.	Max.	Units
Input supply voltage, Vin	Min. $V_{IN} = V_O + 0.15V = 1.35V$ (where $V_O = 1.2V$ )dropout voltage requirement must be met under maximum load.	1.3	1.35	1.5	V
Output Current	Peak load=80 mA. Average load=35 mA	0.1	_	55	mA
Output Voltage, V o	Programmable in 25 mV steps. Default = 1.2V	1.1	1.2	1.275	V
Dropout Voltage	At maximum load	-	_	150	mV
Output Voltage DC Accuracy	Includes line/load regulation	-4	_	+4	%
Quiescent current	No load	-	10	12	μA
	55 mA load	_	550	570	μΑ
Line Regulation	V IN from (V O + 0.1V) to 1.5V, 150 mA load	-	_	5	mV/V
Load Regulation	Load from 1 mA to 150 mA	-	0.02	0.05	mV/mA
Leakage Current	Power-down	_	5	20	μA
	Bypass mode	_	0.02	1.5	μΑ
Output Noise	@30 kHz, 60–150 mA load $C_0$ = 2.2 $\mu$ F	-	-	60 35	nV/rt Hz nV/rt Hz
PSRR	@ 1kHz, Input > 1.35V, $C_0$ = 2.2 μF, $V_0$ = 1.2V	20	_	_	dB
LDO Turn-on Time	LDO turn-on time when balance of chip is up	_	140	180	μs
External Output Capacitor, Co	Total ESR (trace/capacitor): 5 m $\Omega$ –240 m $\Omega$	0.27 1	0.47	_	μF
External Input Capacitor	Only use an external input capacitor at the VDD_LDO pin if it is not supplied from CBUCK output. Total ESR (trace/capacitor): $30 \text{ m}\Omega$ – $200 \text{ m}\Omega$	-	1	2.2	μF

^1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

Document Number: 002-15051 Rev. *O

17. System Power Consumption

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Note: Unless otherwise stated, these values apply for the conditions specified in Table 28: "Recommended Operating Conditions and DC Characteristics".

17.1 WLAN Current Consumption

The tables in this subsection show the typical, total current consumed by the CYW43455. All values shown are with the Bluetooth core in reset mode with Bluetooth off.

17.1.1 2.4 GHz Mode

Table 50. 2.4 GHz Mode WLAN Power Consumption

| | VBAT = 3.6V, VDDIO = 1.8V, TA25°C | |------------------------------------------------------|-----------------------------------|--------------|--| | Mode | VBAT, mA | 1
VIO, uA | | Sleep Modes | | Radio off 2 | 0.006 | 5 | | Sleep 3 | 0.020 | 200 | | IEEE Power Save: DTIM = 1, single RX 4 | 1.25 | 200 | | IEEE Power Save: DTIM = 3, single RX | 0.45 | 200 | | Active RX Modes | | Continuous RX mode: MCS7, HT20, 1SS 5, 6 | 55 | 60 | | CRS: HT20 7 | 50 | 60 | | Active TX Modes – Internal PA | | Continuous TX mode: 1 Mbps @ 21.5 dBm 8 | 400 | 60 | | Continuous TX mode: MCS7, HT20, 1SS, 1 TX @ 19 dBm 8 | 350 | 60 | ^1. VIO is specified with all pins idle (not switching) and not driving any loads.

^2. WL_REG_ON and BT_REG_ON are both low. All supplies are present.

^3. Idle, not associated, or inter-beacon.

^4. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.

^5. Duty cycle is 100%. Carrier sense (CS) detect/packet receive.

^6. Measured using packet engine test mode.

^7. Carrier sense (CCA) when no carrier present.

^8. Duty cycle is 100%.

17.1.2 5 GHz Mode

Table 51. 5 GHz Mode WLAN Power Consumption

| | VBAT = 3.6V, VDDIO = 1.8V, TA25°C | |------------------------------------------------------|-----------------------------------|--------------| | Mode | VBAT , mA | 1
VIO, uA | | Sleep Modes | | Radio off 2 | 0.006 | 5 | | Sleep 3 | 0.025 | 200 | | IEEE Power Save: DTIM = 1, single RX 4 | 1.1 | 200 | | IEEE Power Save: DTIM = 3, single RX | 0.4 | 200 | | Active RX Modes | | Continuous RX mode: MCS7, HT20, 1SS 5, 6 | 74 | 60 | | Continuous RX mode: MCS7, HT40, 1SS 5, 6 | 82 | 60 | | Continuous RX mode: MCS9, HT40, 1SS 5, 6 | 86 | 60 | | Continuous RX mode: MCS9, HT80, 1SS 5, 6 | 117 | 60 | | CRS: HT20 7 | 70 | 60 | | CRS: HT40 7 | 79 | 60 | | CRS: HT80 7 | 100 | 60 | | Active TX Modes – Internal PA | | Continuous TX mode: MCS7, HT20, 1SS, 1 TX @ 19 dBm 8 | 330 | 60 | | Continuous TX mode: MCS7, HT40, 1SS, 1 TX @ 19 dBm 8 | 345 | 60 | | Continuous TX mode: MCS9, HT40, 1SS, 1 TX @ 16 dBm 8 | 320 | 60 | | Continuous TX mode: MCS9, HT80, 1SS, 1 TX @ 16 dBm 8 | 340 | 60 |

^1. VIO is specified with all pins idle (not switching) and not driving any loads.

^2. WL_REG_ON and BT_REG_ON are both low. All supplies present.

^3. Idle, not associated, or inter-beacon.

^4. Beacon Interval = 102.4 ms. Beacon duration = 1ms @ 1Mbps. Average current over 3x DTIM intervals.

^5. Duty cycle is 100%. Carrier sense (CS) detect/packet receive.

^6. Measured using packet engine test mode.

^7. Carrier sense (CCA) when no carrier present.

^8. Duty cycle is 100%.

17.2 Bluetooth Current Consumption

The Bluetooth and BLE current consumption measurements are shown in Table 52.

Note: The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 52. Note: The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.

Table 52. Bluetooth and BLE Current Consumption

Operating Mode	VBAT	VDDIO	Units
Sleep	6	133	µA
Standard 1.28s Inquiry Scan	165	130	µA
500 ms Sniff Master	168	127	µA
DM1/DH1 Master	25.8	0.057	mA
DM3/DH3 Master	32.1	0.071	mA
DM5/DH5 Master	33.2	0.074	mA
3DH5/3DH1 Master	27.7	0.143	mA
SCO HV3 Master	12.2	0.113	mA
BLE Scan1	179	132	µA
BLE Adv—Unconnectable 1.00 sec	73	131	µA
BLE Connected 1 sec	62	130	µA

^1. No devices present. A 1.28 second interval with a scan window of 11.25 ms.

18. Interface Timing and AC Characteristics

18.1 SDIO Timing

18.1.1 SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 31 and Table 53.

tWL tWH fPP tTHL tISU tTLH tIH tODLY (max) tODLY (min) Input Output SDIO_CLK

Figure 31. SDIO Bus Timing (Default Mode)

Table 53. SDIO Bus Timing1 Parameters (Default Mode)

| Parameter | Symbol | Minimum | Typical | Maximum | Unit | |--------------------------------------------------------------------|--------|---------|---------|---------|------|--|--|--|--|--| | SDIO CLK (All values are referred to minimum VIH and maximum VIL2) | | Frequency – Data Transfer mode | fPP | 0 | – | 25 | MHz | | Frequency – Identification mode | fOD | 0 | – | 400 | kHz | | Clock low time | tWL | 10 | – | – | ns | | Clock high time | tWH | 10 | – | – | ns | | Clock rise time | tTLH | – | – | 10 | ns | | Clock low time | tTHL | – | – | 10 | ns | | Inputs: CMD, DAT (referenced to CLK) | | Input setup time | tISU | 5 | – | – | ns | | Input hold time | tIH | 5 | – | – | ns | | Outputs: CMD, DAT (referenced to CLK) | | Output delay time – Data Transfer mode | tODLY | 0 | – | 14 | ns | | Output delay time – Identification mode | tODLY | 0 | – | 50 | ns | ^1. Timing is based on CL 40 pF load on CMD and Data.

Document Number: 002-15051 Rev. *O Page 102 of 121

^2. Min (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.

18.2 SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 32 and Table 54.

Figure 32. SDIO Bus Timing (High-Speed Mode)

Table 54. SDIO Bus Timing1 Parameters (High-Speed Mode)

| Parameter | Symbol | Minimum | Typical | Maximum | Unit | |--------------------------------------------------------------------|--------|---------|---------|---------|------|--|--|--|--| | SDIO CLK (all values are referred to minimum VIH and maximum VIL2) | | Frequency – Data Transfer Mode | fPP | 0 | – | 50 | MHz | | Frequency – Identification Mode | fOD | 0 | – | 400 | kHz | | Clock low time | tWL | 7 | – | – | ns | | Clock high time | tWH | 7 | – | – | ns | | Clock rise time | tTLH | – | – | 3 | ns | | Clock low time | tTHL | – | – | 3 | ns | | Inputs: CMD, DAT (referenced to CLK) | – | – | – | – | – | | Input setup Time | tISU | 6 | – | – | ns | | Input hold Time | tIH | 2 | – | – | ns | | Outputs: CMD, DAT (referenced to CLK) | – | – | – | – | – | | Output delay time – Data Transfer Mode | tODLY | – | – | 14 | ns | | Output hold time | tOH | 2.5 | – | – | ns | | Total system capacitance (each line) | CL | – | – | 40 | pF | ^1. Timing is based on CL 40 pF load on CMD and Data.

Document Number: 002-15051 Rev. *O Page 103 of 121

^2. Min (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.

18.2.1 SDIO Bus Timing Specifications in SDR Modes

Clock Timing

Figure 33. SDIO Clock Timing (SDR Modes)

Table 55. SDIO Bus Clock Timing Parameters (SDR Modes)

Parameter	Symbol	Minimum	Maximum	Unit	Comments
–	tCLK	40	–	ns	SDR12 mode
		20	–	ns	SDR25 mode
		10	–	ns	SDR50 mode
		4.8	–	ns	SDR104 mode
–	tCR, tCF	–	0.2 × tCLK	ns	tCR, tCF < 2.00 ns (max) @ 100 MHz, CCARD = 10 pF
					tCR, tCF < 0.96 ns (max) @ 208 MHz, CCARD = 10 pF
Clock duty cycle	–	30	70	%	–

Card Input Timing

Figure 34. SDIO Bus Input Timing (SDR Modes)

Table 56. SDIO Bus Input Timing Parameters (SDR Modes)

Symbol	Minimum	Maximum	Unit	Comments
SDR104 Mode
tIS	1.4	–	ns	CCARD = 10 pF, VCT = 0.975V
tIH	0.8	–	ns	CCARD = 5 pF, VCT = 0.975V
SDR50 Mode
tIS	3.00	–	ns	CCARD = 10 pF, VCT = 0.975V
tIH	0.8	–	ns	CCARD = 5 pF, VCT = 0.975V

Card Output Timing

Figure 35. SDIO Bus Output Timing (SDR Modes up to 100 MHz)

Table 57. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)

Symbol	Minimum	Maximum	Unit	Comments
tODLY	–	7.5	ns	tCLK ≥ 10 ns CL= 30 pF using driver type B for SDR50
tODLY	–	14.0	ns	tCLK ≥ 20 ns CL= 40 pF using for SDR12, SDR25
tOH	1.5	–	ns	Hold time at the tODLY (min) CL= 15 pF

Figure 36. SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)

Document Number: 002-15051 Rev. *O Page 106 of 121

Table 58. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz)

Symbol	Minimum	Maximum	Unit	Comments
tOP	0	2	UI	Card output phase
ΔtOP	–350	+1550	ps	Delay variation due to temp change after tuning
tODW	0.60	–	UI	tODW = 2.88 ns @ 208 MHz

• ΔtOP = +1550 ps for junction temperature of ΔtOP = 90°C during operation.
• ΔtOP = –350 ps for junction temperature of ΔtOP = –20°C during operation.
• ΔtOP = +2600 ps for junction temperature of ΔtOP = –20°C to +125°C during operation.

Figure 37. ΔtOP Consideration for Variable Data Window (SDR 104 Mode)

18.2.2 SDIO Bus Timing Specifications in DDR50 Mode

Figure 38. SDIO Clock Timing (DDR50 Mode)

Document Number: 002-15051 Rev. *O Page 107 of 121

Table 59. SDIO Bus Clock Timing Parameters (DDR50 Mode)

Parameter	Symbol	Minimum	Maximum	Unit	Comments
–	tCLK	20	–	ns	DDR50 mode
–	tCR,tCF	–	0.2 × tCLK	ns	tCR, tCF < 4.00 ns (max) @50 MHz, CCARD = 10 pF
Clock duty cycle	–	45	55	%	–

Data Timing

Figure 39. SDIO Data Timing (DDR50 Mode)

Table 60. SDIO Bus Timing Parameters (DDR50 Mode)

| Parameter | Symbol | Minimum | Maximum | Unit | Comments | |-------------------|---------|---------|---------|------|------------------------|--| | Input CMD | | Input setup time | tISU | 6 | – | ns | CCARD < 10 pF (1 Card) | | Input hold time | tIH | 0.8 | – | ns | CCARD < 10 pF (1 Card) | | Output CMD | | Output delay time | tODLY | – | 13.7 | ns | CCARD < 30 pF (1 Card) | | Output hold time | tOH | 1.5 | – | ns | CCARD < 15 pF (1 Card) | | Input DAT | | Input setup time | tISU2x | 3 | – | ns | CCARD < 10 pF (1 Card) | | Input hold time | tIH2x | 0.8 | – | ns | CCARD < 10 pF (1 Card) | | Output DAT | | Output delay time | tODLY2x | – | 7.5 | ns | CCARD < 25 pF (1 Card) | | Output hold time | tODLY2x | 1.5 | – | ns | CCARD < 15 pF (1 Card) | Document Number: 002-15051 Rev. *O Page 108 of 121

18.3 PCI Express Interface Parameters

Note: The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Table 61. PCI Express Interface Parameters

Parameter	Symbol	Comments	Minimum	Typical	Maximum	Unit
General
Baud rate	BPS	–	–	5	–	Gbaud
Reference clock amplitude	Vref	LVPECL, AC coupled	1	–	–	V
Receiver
Differential termination	ZRX-DIFF-DC	Differential termination	80	100	120	Ω
DC impedance	ZRX-DC	DC common-mode impedance	40	50	60	Ω
Powered down termination (POS)	ZRX-HIGH-IMP-DC-POS Power-down or RESET	high impedance	100k	–	–	Ω
Powered down termination (NEG)	ZRX-HIGH-IMP-DC-NE G	Power-down or RESET high impedance	1k	–	–	Ω
Input voltage	VRX-DIFFp-p	AC coupled, differential p-p	175	–	–	mV
Jitter tolerance	TRX-EYE	Minimum receiver eye width	0.4	–	–	UI
Differential return loss	RLRX-DIFF	Differential return loss	10	–	–	dB
Common-mode return loss	RLRX-CM	Common-mode return loss	6	–	–	dB
Unexpected electrical idle enter detect threshold integration time	TRX-IDEL-DET-DIFF-EN TERTIME	An unexpected electrical idle must be recognized no longer than this time to signal an unexpected idle condition.	–	–	10	ms
Signal detect threshold	VRX-IDLE-DET-DIFFp-p	Electrical idle detect threshold	65	–	175	mV
Transmitter
Output voltage	VTX-DIFFp-p	Differential p-p, program mable in 16 steps	0.8	–	1200	mV
Output voltage rise time	VTX-RISE	20% to 80%	0.125 (2.5 GT/s)	–	–	UI
			0.15 (5 GT/s)
Output voltage fall time	VTX-FALL	80% to 20%	0.125 (2.5 GT/s) 0.15 (5 GT/s)	–	–	UI
RX detection voltage swing	VTX-RCV-DETECT	The amount of voltage change allowed during receiver detection.	–	–	600	mV
TX AC peak common-mode voltage (5 GT/s)	VTX-CM-AC-PP	TX AC common mode voltage (5 GT/s)	–	–	100	mV
TX AC peak common-mode voltage (2.5 GT/s)	VTX-CM-AC-P	TX AC common mode voltage (2.5 GT/s)	–	–	20	mV

Document Number: 002-15051 Rev. *O Page 109 of 121

Table 61. PCI Express Interface Parameters (continued)

Parameter	Symbol	Comments	Minimum	Typical	Maximum	Unit
Absolute delta of DC common-model voltage during L0 and electrical idle	VTX-CM-DC-ACTIVE-ID LE-DELTA	Absolute delta of DC common-model voltage during L0 and electrical idle.	0	–	100	mV
Absolute delta of DC common-model voltage between D+ and D	VTX-CM-DC-LINE-DELT A	DC offset between D+ and D	0	–	25	mV
Electrical idle differential peak output voltage	VTX-IDLE-DIFF-AC-p	Peak-to-peak voltage	0	–	20	mV
TX short circuit current	ITX-SHORT	Current limit when TX output is shorted to ground.	–	–	90	mA
DC differential TX termi nation	ZTX-DIFF-DC	Low impedance defined during signaling (parameter is captured for 5.0 GHz by RLTX-DIFF)	80	–	120	Ω
Differential return loss	RLTX-DIFF	Differential return loss	10 (min.) for 0.05: 1.25 GHz	–	–	dB
			8 (min.) for 1.25: 2.5 GHz
Common-mode return loss	RLTX-CM	Common-mode return loss	6	–	–	dB
TX eye width	TTX-EYE	Minimum TX eye width	0.75	–	–	UI

18.4 JTAG Timing

Table 62. JTAG Timing Characteristics

Signal Name	Period	Output Maximum	Output Minimum	Setup	Hold
TCK	125 ns	–	–	–	–
TDI	–	–	–	20 ns	0 ns
TMS	–	–	–	20 ns	0 ns
TDO	–	100 ns	0 ns	–	–
JTAG_TRST	250 ns	–	–	–	–

18.5 SWD Timing

The probe outputs data to SWDIO on the falling edge of SWDCLK and captures data from SWDIO on the rising edge of SWDCLK. The target outputs data to SWDIO on the rising edge of SWDCLK and captures data from SWDIO on the rising edge of SWDCLK. SWD timing is defined through the combination of Figure 40 and Table 63.

Figure 40. SWD Read and Write Timing

Table 63. SWD Read and Write Timing Parameters

Parameter	Description	Min.	Max.	Units
Tcyc	SWDCLK cycle time	125	-	ns
Thigh	SWDCLK high period	50	_	ns
Tlow	SWDCLK low period	50	_	ns
T os	SWDIO output skew to the falling edge of SWDCLK	-5	5	ns
T is	Input setup time between SWDIO and the rising edge of SWDCLK	20	_	ns
T ih	Input hold time between SWDIO and the rising edge of SWDCLK	0	100	ns

19. Power-Up Sequence and Timing

19.1 Sequencing of Reset and Regulator Control Signals

The CYW43455 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 41, Figure 42, and Figure 43 and Figure 44). The timing values indicated are minimum required values; longer delays are also acceptable.

19.1.1 Description of Control Signals

• WL_REG_ON: Used by the PMU to power-up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal CYW43455 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled.
• BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power-up the internal CYW43455 regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT section is in reset.

Note: For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start.

Note: The CYW43455 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least 150 ms after VDDC and VDDIO are available before initiating PCIe7 accesses.

Note: VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

19.1.2 Control Signal Timing Diagrams

Figure 41. WLAN = ON, Bluetooth = ON

Document Number: 002-15051 Rev. *O Page 112 of 121

^7. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.

Figure 43. WLAN = ON, Bluetooth = OFF

Figure 44. WLAN = OFF, Bluetooth = ON

20. Package Information

20.1 Package Thermal Characteristics

Table 64. Package Thermal Characteristics¹

Characteristic	WLBGA
JA (°C/W) (value in still air)	38.73
JB (°C/W)	1.97
JC (°C/W)	3.16
JT (°C/W)	9.3
JB (°C/W)	16.21
Maximum Junction Temperature Tj (°C)	123.6
Maximum Power Dissipation (W)	1.38

^1. No heat sink, TA = 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm × 101.6 mm × 1.6 mm) and P = 1.119W continuous dissipation.

20.2 Junction Temperature Estimation and PSIJT Versus THETAJC

Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is:

$$T_J = T_T + P \times \mathcal{\Psi}_{JT}$$

Where:

• TJ = Junction temperature at steady-state condition (°C)
• TT = Package case top center temperature at steady-state condition (°C)
• P = Device power dissipation (Watts)
• JT = Package thermal characteristics; no airflow (°C/W)

20.3 Environmental Characteristics

For environmental characteristics data, see Table 26.

21. Mechanical Information

Figure 45. 140-Ball WLBGA Package Mechanical Information

4345XCT DS1X15 f 055 1

Keep out # Horizental (mm) vertical (mm) 0.11 0.11 0.09 0.09 0.12 0.12 0.08 0.08 0.08 0.08 0.20 0.20 0.15 0.15 0.14 0.14 0.17 0.14 0.05 0.05 0.15 0.15 0.27 0.27 0.16 0.16 0.15 0.15 0.18 0.18 0.13 0.10 0.13 0.13 0.13 0.13 0.18 0.18 0.08 0.08 0.14 0.18 0.10 0.10 0.07 0.07 0.07 0.07

Figure 46. 140-Balls WLBGA Keep-out Areas for PCB Layout—Top View with Balls Facing Down

Note: No top-layer metal is allowed in keep-out areas.

Note: A DXF file for the WLBGA keep-out area is available for importation into a layout program. Contact Cypress for more information.

22. Ordering Information

Table 65. Part Ordering Information

Part Number	Package	Description	Operating Ambient Tem perature
CYW43455XKUBG	140-ball WLBGA (4.47 mm × 5.27 mm, 0.4 mm pitch)	Dual-band 2.4 GHz and 5 GHz WLAN+ BT 4.1	–30°C to +85°C

23. Additional Information

23.1 Acronyms and Abbreviations

In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used in Cypress documents, go to: http://www.cypress.com/glossary.

23.2 References

The references in this section may be used in conjunction with this document.

Note: Cypress provides customer access to technical documentation and software through its Customer Support Portal and Downloads & Support site (see IoT Resources).

For Cypress documents, replace the "xx" in the document number with the largest number available in the repository to ensure that you have the most current version of the document.

Document (or Item) Name	Number	Source
Bluetooth MWS Coexistence 2-wire Transport Interface Specification –		www.bluetooth.com
PCI Bus Local Bus Specification, Revision 2.3	–	www.pcisig.com
PCIe Base Specification Version 1.1	–	www.pcisig.com

23.3 IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website (https://community.cypress.com/)

Document Number: 002-15051 Rev. *O Page 117 of 121

Document History Page

Revision	ECN	Orig. of Change	Submission Date	Description of Change
**	–	–	10/27/2014	43455-DS100-R
				Initial release.
*A	–	–	11/06/2014	43455-DS101-R See the pertinent document for the revision history.
*B	–	–	11/20/2014	43455-DS102-R See the pertinent document for the revision history.
*C	–	–	02/04/2015	43455-DS103-R See the pertinent document for the revision history.
*D	–	–	03/31/2015	43455-DS104-R
				See the pertinent document for the revision history.
*E	–	–	04/06/2015	43455-DS105-R See the pertinent document for the revision history.
*F	–	–	07/09/2015	43455-DS106-R See the pertinent document for the revision history.
*G	–	–	07/29/2015	43455-DS107-R
				See the pertinent document for the revision history.
*H	–	–	09/25/2015	43455-DS108-R
				See the pertinent document for the revision history.
*I	–	–	11/05/2015	43455-DS109-R
				• Table 35. WLAN 2.4 GHz Transmitter Performance Specifications. • Table 37. WLAN 5 GHz Transmitter Performance Specifications. • Table 51. 5 GHz Mode WLAN Power Consumption.
*J	–	–	01/04/2016	43455-DS110-R
				Updated:
				• Table 52. Bluetooth and BLE Current Consumption
*K	5450777	UTSV	10/5/2016	43455-DS111-R
				Updated:
				• Table 18. WLBGA Pin List by Pin Number.
				• Table 19. WLBGA Pin List by Pin Name. • Table 20. Signal Descriptions.
				Updated in Cypress template.
				Added Cypress Part Numbering Scheme.
*L	5675342	UTSV	03/28/2016	Updated with new logo.
				FM related sections are removed from this document.
*M	5770411	TLAU	05/22/2017	Updated Title Bluetooth 4.1 to 4.2 throughout the Datasheet.
				Added:
				LE Data Packet Length Extension
				LE Secure Connections to "Bluetooth 4.2 Features" on page 20.
				Changed Table 20:
				VDDIO Description to VDDIO can be 1.8V and 3.3V.
*N	5947698	UTSV	11/02/2017	Removed the Empty box in the Figure 2.
				Updated contents in the "External 32.768 kHz Low-Power Oscillator" on page 15.
				Replaced "LPO/Ext LPO/RCAL" to "Ext LPO/RCAL" in the Figure 27.
				Updated Table 22 on page 64.

Document Number: 002-15051 Rev. *O Page 119 of 121

| | Document Title: CYW43455 Single-Chip 5G WiFi IEEE 802.11n/ac MAC/Baseband/ Radio with Integrated Bluetooth 5.0
Document Number: 002-15051 | |----|----------------------------------------------------------------------------------------------------------------------------------------------|------|------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--| | *O | 6440968 | UTSV | 03/22/2019 | Updated the title as "Single-Chip 5G WiFi IEEE 802.11n/ac MAC/Baseband/ Radio with
Integrated Bluetooth 5.0 ". | | | | | | Added footnote for references of PCIe as "The PCIe interface is not brought up on
CYW43455 and Cypress's firmware and drivers do not support this interface". | | | | | | Changed Bluetooth 4.2 to "Bluetooth 5.0" throughout the document. | | | | | | Updated Bluetooth Key Features. | | | | | | Added "Bluetooth 5.0 compliant" in Standards Compliance section. | | | | | | Added Bluetooth 5.0 section. | | | | | | Added Note "The PCIe interface is not brought up on CYW43455 and Cypress's
firmware and drivers do not support this interface" in the following sections: | | | | | | PCI Express Interface, Pin Descriptions (Table 20), PCI Express Interface Parameters. | Document Number: 002-15051 Rev. *O Page 120 of 121

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Document Number: 002-15051 Rev. *O Page 121 of 121