C69336

Part: STM32F446xC/E — STMicroelectronics

Type: ARM Cortex-M4 Microcontroller

Description: 32-bit ARM Cortex-M4 MCU with FPU, operating at up to 180 MHz, featuring up to 512 KB Flash, 128 KB SRAM, USB OTG HS/FS, 17 timers, 3 ADCs, and 20 communication interfaces.

Operating Conditions:

• Supply voltage: 1.7 V to 3.6 V
• Operating temperature: -40 to +125 °C
• Max CPU frequency: 180 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max junction/storage temperature: 150 °C

Key Specs:

• CPU: ARM 32-bit Cortex-M4 with FPU
• Max CPU frequency: 180 MHz
• Flash memory: Up to 512 KB
• SRAM: 128 KB
• ADC resolution: 12-bit, 2.4 MSPS (up to 7.2 MSPS in triple interleaved mode)
• DAC resolution: 12-bit
• I/O ports: Up to 114 with interrupt capability, up to 112 5 V-tolerant
• DMIPS: 225 DMIPS (Dhrystone 2.1)

Features:

• Adaptive real-time accelerator (ART Accelerator™) for 0-wait state execution from Flash
• Flexible external memory controller (SRAM, PSRAM, SDRAM/LPSDR SDRAM, Flash NOR/NAND)
• Dual mode Quad SPI interface
• USB 2.0 full-speed/high-speed device/host/OTG controller with dedicated DMA
• Up to 4 I2C, 4 USARTs/2 UARTs, 4 SPIs, 2 SAI, 2 CAN interfaces
• 8- to 14-bit parallel camera interface
• Low-power modes: Sleep, Stop, Standby
• RTC with subsecond accuracy and hardware calendar

Applications:

Package:

• LQFP64
• LQFP100
• LQFP144
• UFBGA144 (7 x 7mm)
• UFBGA144 (10 x 10mm)
• WLCSP81

• Core: ARM ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Fl ash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -512 kB of Flash memory
• -128 KB of SRAM
• -Flexible external memory controller with up to 16-bit data bus: SRAM,PSRAM,SDRAM/LPSDR SDRAM, Flash NOR/NAND memories
• -Dual mode Quad SPI interface
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
• -1.7 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4-to-26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC (1% accuracy)
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Low power
• -Sleep, Stop and Standby modes
• -VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: 2x watchdog, 1x SysTick timer and up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter
• Debug mode
• -SWD & JTAG interfaces
• -Cortex ® -M4 Trace Macrocell™

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Figure 10. STM32F446xC/xE LQFP64 pinout

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Figure 11. STM32F446xC/xE LQFP100 pinout

1. The above figure shows the package top view.

Figure 12. STM32F446xC LQFP144 pinout

Figure 12. STM32F446xC LQFP144 pinout

1. The above figure shows the package top view.

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Figure 13. STM32F446xC/xE WLCSP81 ballout

Figure 14. STM32F446xC/xE UFBGA144 ballout

1. The above picture shows the package top view.

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Table 9. Legend/abbreviations used in the pinout table

Table 10. STM32F446xx pin and ball descriptions

Table 10. STM32F446xx pin and ball descriptions

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

The definition and values of input/output AC characteristics are given in Figure 32 and Table 58 , respectively.

Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 16 .

Table 58. I/O AC characteristics (1)(2)

Table 58. I/O AC characteristics (1)(2)

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Table 58. I/O AC characteristics (1)(2) (continued)

Table 58. I/O AC characteristics (1)(2) (continued)

1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 32 .
4. For maximum frequencies above 50 MHz and V DD > 2.4 V, the compensation cell should be used.

Figure 32. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics , Table 14: Current characteristics , and Table 15: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 13. Voltage characteristics

Table 14. Current characteristics

Table 14. Current characteristics

1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
2. A positive injection is induced by V IN >V DDA while a negative injection is induced by V IN <V SS . IINJ(PIN) must never be exceeded. Refer to Table 13 for the maximum allowed input voltage value.
3. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 15. Thermal characteristics

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The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.