AT24C256

Part: Atmel AT24C256C

Type: I2C-Compatible (2-Wire) Serial EEPROM

Key Specs:

• Supply Voltage: 1.7V to 5.5V
• Memory Organization: 32,768 x 8 bits (256 Kbit)
• Interface Speed: 400kHz (at 1.7V), 1MHz (at 2.5V, 2.7V, 5.0V)
• Write Endurance: 1,000,000 Write Cycles
• Data Retention: 40 Years
• Operating Temperature: -40°C to +85°C

Features:

• Low-voltage and Standard-voltage Operation
• Internally Organized as 32,768 x 8
• 2-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility
• Write Protect Pin for Hardware Protection
• 64-byte Page Write Mode
• Partial Page Writes Allowed
• Self-timed Write Cycle (5ms Max)
• High Reliability
• Endurance: 1,000,000 Write Cycles
• Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• Green Package Options (Pb/Halide-free/RoHS Compliant)
• 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 8-ball VFBGA Packages
• Die Sale Options: Wafer Form, Waffle Pack, and Bumped Wafers

Applications:

• Industrial applications
• Commercial applications

Package:

• 8-lead JEDEC SOIC: null
• 8-lead TSSOP: null
• 8-pad UDFN: null
• 8-ball VFBGA: null

• Low-voltage and Standard-voltage Operation
  • ̶ VCC = 1.7V to 5.5V
• Internally Organized as 32,768 x 8
• 2-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility
• Write Protect Pin for Hardware Protection
• 64-byte Page Write Mode
  • ̶ Partial Page Writes Allowed
• Self-timed Write Cycle (5ms Max)
• High Reliability
  • ̶ Endurance: 1,000,000 Write Cycles
  • ̶ Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• Green Package Options (Pb/Halide-free/RoHS Compliant)
  • ̶ 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 8-ball VFBGA Packages
• Die Sale Options: Wafer Form, Waffle Pack, and Bumped Wafers

Table 1-1. Pin Configuration

2. Absolute Maximum Ratings*

*Notice: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

3. Block Diagram

4. Pin Descriptions

Serial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negativeedge clock data out of each device.

Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.

Device Addresses (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hard wired (directly to GND or to VCC) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight 256K devices may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7. "Device Addressing" on page 9). A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less.

Write Protect (WP): The Write Protect input, when connected to GND, allows normal write operations. When WP is connected directly to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less.

Table 4-1. Write Protect

5. Memory Organization

AT24C256C, 256K Serial EEPROM: The 256K is internally organized as 512 pages of 64-bytes each. Random word addressing requires a 15-bit data word address.

5.1 Pin Capacitance

Table 5-1. Pin Capacitance(1)

Applicable over recommended operating range from: TA = 25°C, f = 1.0MHz, VCC = 1.7V to 5.5V.

Note: 1. This parameter is characterized and is not 100% tested.

5.2 DC Characteristics

Table 5-2. DC Characteristics

Applicable over recommended operating range from: TAI = - 40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted).

Note: 1. VIL min and VIH max are reference only and are not tested.

5.3 AC Characteristics

Table 5-3. AC Characteristics (Industrial Temperature)

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = 1.7V to 5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.

| | | | 1.7V | | 2.5V, 5.0V | |--------------|---------------------------------------------------------------------|------|------|--------------|------------|-------| | Symbol | Parameter | Min | Max | Min | Max | Units | | fSCL | Clock Frequency, SCL | | 400 | | 1000 | kHz | | tLOW | Clock Pulse Width Low | 1300 | | 400 | | ns | | tHIGH | Clock Pulse Width High | 600 | | 400 | | ns | | tI | Noise Suppression Time(1) | | 100 | | 50 | ns | | tAA | Clock Low to Data Out Valid | 50 | 900 | 50 | 550 | ns | | tBUF | Time the bus must be free before a new transmission
can start(1) | 1300 | | 500 | | ns | | tHD.STA | Start Hold Time | 600 | | 250 | | ns | | tSU.STA | Start Set-up Time | 600 | | 250 | | ns | | tHD.DAT | Data In Hold Time | 0 | | 0 | | ns | | tSU.DAT | Data In Set-up Time | 100 | | 100 | | ns | | tR | Inputs Rise Time(1) | | 300 | | 300 | ns | | tF | Inputs Fall Time(1) | | 300 | | 100 | ns | | tSU.STO | Stop Set-up Time | 600 | | 250 | | ns | | tDH | Data Out Hold Time | 50 | | 50 | | ns | | tWR | Write Cycle Time | | 5 | | 5 | ms | | Endurance(1) | 25°C, Page Mode, 3.3V
1,000,000 | | | Write Cycles | Notes: 1. This parameter is ensured by characterization and is not 100% tested.

• 1. AC measurement conditions:
  • RL (connects to VCC): 1.3kΩ (2.5V, 5.5V), 10kΩ (1.7V)
  • Input pulse voltages: 0.3VCC to 0.7VCC
  • Input rise and fall times: ≤ 50ns
  • Input and output timing reference voltages: 0.5 x VCC

6. Device Operation

Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a start or stop condition as defined below.

Figure 6-1. Data Validity

Start Condition: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command.

Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode.

Figure 6-2. Start and Stop Definition

Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.

Figure 6-3. Output Acknowledge

Standby Mode: AT24C256C features a low-power standby mode that is enabled upon power-up and after the receipt of the Stop condition and the completion of any internal operations.

Software Reset: After an interruption in protocol, power-loss or system reset, any 2-wire part can be protocol reset by following these steps:

• 1. Create a Start condition (if possible).
• 1. Clock nine cycles.
• 1. Create another Start condition followed by Stop condition as shown below.

The device should be ready for the next communication after above steps have been completed. In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset the device.

Figure 6-4. Software Reset

Figure 6-5. Bus Timing

Figure 6-6. Write Cycle Timing

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

7. Device Addressing

The 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices.

Figure 7-1. Device Addressing

The next three bits are the A2, A1, and A0 device address bits to allow as many as eight devices on the same bus. These bits must compare to their corresponding hard wired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high, and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state.

Data Security: The AT24C256C has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at VCC.

8. Write Operations

Byte Write: A Write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero, and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, must then terminate the write sequence with a Stop condition. At this time, the EEPROM enters an internally-timed write cycle, $t_{WR}$ , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete.

Figure 8-1. Byte Write

Note: * = Don't care bit

Page Write: The 256K EEPROM is capable of 64-byte page writes.

A Page Write is initiated the same way as a Byte Write, but the microcontroller does not send a Stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a Stop condition.

Figure 8-2. Page Write

Note: * = Don't care bit

The data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will roll-over and the previous data will be overwritten. The address roll-over during write is from the last byte of the current page to the first byte of the same page.

Acknowledge Polling: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.

9. Read Operations

Read operations are initiated the same way as write operations with the exception that the Read/Write select bit in the device address word is set to one. There are three read operations:

• Current Address Read
• Random Address Read
• Sequential Read

Current Address Read: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll-over during read is from the last byte of the last memory page, to the first byte of the first page.

Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition.

Figure 9-1. Current Address Read

Random Read: A Random Read requires a dummy byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a Current Address Read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following Stop condition.

Figure 9-2. Random Read

Note: * = Don't care bit

Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll-over, and the Sequential Read will continue. The Sequential Read operation is terminated when the microcontroller does not respond with a zero but does generate a following Stop condition.

Figure 9-3. Sequential Read

Note: * = Don't care bit

10. Ordering Code Detail

Table 5-2. DC Characteristics

Applicable over recommended operating range from: TAI = - 40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted).

Note: 1. VIL min and VIH max are reference only and are not tested.

*Notice: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.