ADRV9009-W/PCBZ

Part: ADRV9009, Analog Devices

Type: RF Agile Transceiver

Key Specs:

• Maximum receiver bandwidth: 200 MHz
• Maximum tunable transmitter synthesis bandwidth: 450 MHz
• Maximum observation receiver bandwidth: 450 MHz
• Tuning range (center frequency): 75 MHz to 6000 MHz
• Core power supply: 1.3 V, 1.8 V
• JESD204B lane rates: up to 12.288 Gbps

Features:

• Dual transmitters
• Dual receivers
• Dual input shared observation receiver
• Fully integrated fractional-N RF synthesizers
• Fully integrated clock synthesizer
• Multichip phase synchronization for RF LO and baseband clocks
• JESD204B datapath interface
• Automatic and manual attenuation control
• DC offset correction
• Quadrature error correction (QEC)
• Digital filtering
• Integrated auxiliary ADCs, DACs, and GPIOs
• Automatic gain control (AGC)
• Flexible external gain control modes
• Direct conversion architecture
• Integrated PLL for RF frequency synthesis
• Integrated VCOs and loop filter components
• Fixed and floating point data formats for JESD204B
• Comprehensive power-down modes
• Controlled via a standard 4-wire serial port

Applications:

• 3G, 4G, and 5G TDD macrocell base stations
• TDD active antenna systems
• Massive multiple input, multiple output (MIMO)
• Phased array radar
• Electronic warfare
• Military communications
• Portable test equipment

Package:

• 196-ball chip scale ball grid array (CSP_BGA): 12 mm × 12 mm

Dual transmitters Dual receivers Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz

APPLICATIONS

3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

GENERAL DESCRIPTION

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.

The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-toanalog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.

In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.

The received signals are digitized with a set of four high dynamic range, continuous time Σ-Δ ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.

The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.

The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.

The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.

The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.

The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

ADRV9009

Figure 6. Pin Configuration

Table 5. Pin Function Descriptions

Table 3.

¹ VDDA1P3 refers to all analog 1.3 V supplies.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

The ADRV9009 is a high power device that can dissipate over 3 W depending on the user application and configuration. Because of the power dissipation, the ADRV9009 uses an exposed die package to provide the customer with the most effective method of controlling the die temperature. The exposed die allows cooling of the die directly. Figure 5 shows the profile view of the device mounted to a user printed circuit board (PCB) and a heat sink (typically the aluminum case) to keep the junction (exposed die) below the maximum TJ detailed in Table 3. The device is designed for a lifetime of 10 years when operating at the maximum TJ.