ADAU1701CAN
SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
Audio Processor with Integrated ADCs and DACsThe ADAU1701CAN is a audio processor with integrated adcs and dacs from Analog Devices Inc.. SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs. View the full ADAU1701CAN datasheet below including key specifications, absolute maximum ratings.
Manufacturer
Analog Devices Inc.
Category
Integrated CircuitsKey Specifications
| Parameter | Value |
|---|---|
| Clock Rate | 50MHz |
| Interface | I2C, SPI |
| Mounting Type | Surface Mount |
| On-Chip RAM | 12kB |
| Operating Temperature | 0°C ~ 70°C (TA) |
| Package / Case | 48-LQFP |
| Supplier Device Package | 48-LQFP (7x7) |
| Type | Sigma |
| Voltage - Core | 1.80V |
| Voltage - I/O | 3.30V |
Overview
Part: ADAU1701, Analog Devices
Type: Audio Processor with Integrated ADCs and DACs
Description: A complete single-chip 28-/56-bit, 50 MIPS digital audio processor with two 100 dB SNR ADCs and four 104 dB SNR DACs, supporting sampling rates up to 192 kHz and self-boot from serial EEPROM.
Operating Conditions:
- Supply voltage: AVDD: 2.97–3.63 V, DVDD: 1.62–1.98 V, IOVDD: 2.97–3.63 V
- Operating temperature: 0 to +70 °C ambient
- Max sampling rate: 192 kHz
- DSP speed: 50 MIPS
Absolute Maximum Ratings:
- Max supply voltage (AVDD/IOVDD to GND): 4.0 V
- Max junction temperature: 135 °C
Key Specs:
- ADC Signal-to-Noise Ratio (A-Weighted): 100 dB (Typ)
- ADC Total Harmonic Distortion + Noise: -83 dB (Typ, at -3 dB full-scale)
- DAC Signal-to-Noise Ratio (A-Weighted): 104 dB (Typ)
- DAC Total Harmonic Distortion + Noise: -90 dB (Typ, at -1 dB full-scale)
- Analog Supply Current (AVDD and PVDD): 50 mA (Typ), 85 mA (Max)
- Digital Supply Current (DVDD): 40 mA (Typ), 60 mA (Max)
- Auxiliary ADC Full-Scale Analog Input: 3.0 V (Typ)
Features:
- 28-/56-bit, 50 MIPS digital audio processor
- 2 ADCs: SNR of 100 dB, THD + N of -83 dB
- 4 DACs: SNR of 104 dB, THD + N of -90 dB
- Complete standalone operation, self-boot from serial EEPROM
- Auxiliary ADC with 4-input mux for analog control
- Fully programmable with SigmaStudio graphical tool
- Sampling rates of up to 192 kHz are supported
- On-chip voltage regulator for compatibility with 3.3V systems
Applications:
- Multimedia speaker systems
- MP3 player speaker docks
- Automotive head units
- Minicomponent stereos
- Digital televisions
- Studio monitors
- Speaker crossovers
- Musical instrument effects processors
- In-seat sound systems (aircraft/motor coaches)
Package:
- 48-Lead LQFP
Features
28-/56-bit, 50 MIPS digital audio processor 2 ADCs: SNR of 100 dB, THD + N of -83 dB 4 DACs: SNR of 104 dB, THD + N of -90 dB
Complete standalone operation Self-boot from serial EEPROM
Auxiliary ADC with 4-input mux for analog control
GPIOs for digital controls and outputs
Fully programmable with SigmaStudio graphical tool 28-bit × 28-bit multiplier with 56-bit accumulator for full double-precision processing
Clock oscillator for generating a master clock from crystal PLL for generating master clock from 64 × fS, 256 × fS, 384 × fS, or 512 × fS clocks
Flexible serial data input/output ports with I2S-compatible, left-justified, right-justified, and TDM modes Sampling rates of up to 192 kHz are supported On-chip voltage regulator for compatibility with 3.3V systems 48-lead, plastic LQFP
Applications
Multimedia speaker systems MP3 player speaker docks Automotive head units Minicomponent stereos Digital televisions Studio monitors Speaker crossovers Musical instrument effects processors In-seat sound systems (aircraft/motor coaches)
Pin Configuration
Figure 7. 48-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
| Pin No. | Mnemonic | Type1 | Description |
|---|---|---|---|
| 1, 37, 42 | AGND | PWR | Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. Decouple AGND to an AVDD pin with a 100 nF capacitor. |
| 2 | ADC0 | A_IN | Analog Audio Input 0. Full-scale 100 μA rms input. Current input allows input voltage level to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input. See the Audio ADCs section for details. |
| 3 | ADC_RES | A_IN | ADC Reference Current. Set the full-scale current of the ADCs with an external 18 kΩ resistor connected between this pin and ground. See the Audio ADCs section for details. |
| 4 | ADC1 | A_IN | Analog Audio Input 1. Full-scale 100 μA rms input. Current input allows the input voltage level to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input. |
| 5 | RESET | D_IN | Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1701 exits reset on a low-to-high edge. For more information about initialization, see the Power-Up Sequence section for details. |
| 6 | SELFBOOT | D_IN | Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting this pin high initiates a self-boot operation when the ADAU1701 is brought out of a reset. This pin can be tied directly to the control voltage or pulled up/down with a resistor. See the Self-Boot section for details. |
| 7 | ADDR0 | D_IN | I2C and SPI Address 0. In combination with ADDR1 function on Pin 20, this pin allows up to four ADAU1701 devices to be used on the same I2C bus and up to two ICs to be used with a common SPI CLATCH signal. See the I2C Port section for details. |
| 8 | MP4 | D_IO | Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK). See the Multipurpose Pins section for more details. |
| 9 | MP5 | D_IO | Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK). See the Multipurpose Pins section for more details. |
| 10 | MP1 | D_IO | Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0). See the Multipurpose Pins section for more details. |
| 11 | MP0 | D_IO | Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1). See the Multipurpose Pins section for more details. |
| 12, 25 | DGND | PWR | Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. Decouple DGND to a DVDD pin with a 100 nF capacitor. |
| 13, 24 | DVDD | PWR | 1.8 V Digital Supply. This can be supplied either externally or generated from a 3.3 V supply with the on-board 1.8 V regulator. Decouple DVDD to DGND with a 100 nF capacitor. |
| Pin No. | Mnemonic | Type1 | Description |
| --- | --- | --- | --- |
| 14 | MP7 | D_IO | Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1). See the Multipurpose Pins section for more details. |
| 15 | MP6 | D_IO | Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output (SDATA_OUT0). See the Multipurpose Pins section for more details. |
| 16 | MP10 | D_IO | Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK). See the Multipurpose Pins section for more details. |
| 17 | VDRIVE | A_OUT | Drive for 1.8 V Regulator. The base of the voltage regulator external PNP transistor is driven from VDRIVE. See the Voltage Regulator section for details. |
| 18 | IOVDD | PWR | Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage that should be seen on the digital input pins. This pin is also the supply for the digital output signals on the control port and MP pins. Always set IOVDD to 3.3 V. The current draw of this pin is variable because it is dependent on the loads of the digital outputs. |
| 19 | MP11 | D_IO | Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). See the Multipurpose Pins section for more details. |
| 20 | ADDR1/CDATA/WB | D_IN | I²C Address 1/SPI Data Input/EEPROM Write Back Trigger. This is a multifunction pin as follows: |
| ADDR1: I²C Address 1. In combination with ADDR0, this sets the I²C address of the IC so that four ADAU1701 devices can be used on the same I²C bus. See the I²C Port section for details. | |||
| CDATA: SPI Data Input. See the SPI Port section for details. | |||
| WB: EEPROM Writeback Trigger. A rising (default) or falling (if set in the EEPROM messages) edge on this pin triggers a writeback of the interface registers to the external EEPROM. This function can be used to save parameter data on power-down. See the Self-Boot section for details. | |||
| 21 | CLATCH/WP | D_IO | SPI Latch Signal/Self-Boot EEPROM Write Protect. This is a multifunction pin as follows: |
| CLATCH: SPI Latch Signal. Must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction can take a different number of cycles on the CCLK pin to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. See the SPI Port section for details. | |||
| WP: Self-Boot EEPROM Write Protect. This pin is an open-collector output when in self-boot mode. The ADAU1701 pulls this low to enable writes to an external EEPROM. This pin should be pulled high to 3.3 V. See the Self-Boot section for details. | |||
| 22 | SDA/COUT | D_IO | I²C Data/SPI Data Output. This is a multifunction pin, as follows: |
| SDA: I²C Data. This pin is a bidirectional open-collector. The line connected to this pin should have a 2.2 kΩ pull-up resistor. See the I²C Port section for details. | |||
| COUT: This SPI data output is used for reading back registers and memory locations. It is three-state when an SPI read is not active. See the SPI Port section for details. | |||
| 23 | SCL/CCLK | D_IO | I²C Clock/SPI Clock. This is a dual function pin, as follows: |
| SCL: I²C Clock. This pin is always an open-collector input when in I²C control mode. In self-boot mode, this pin is an open-collector output (I²C master). The line connected to this pin should have a 2.2 kΩ pull-up resistor. See the I²C Port section for details. | |||
| CCLK: SPI Clock. This pin can either run continuously or be gated off between SPI transactions. See the SPI Port section for details. | |||
| 26 | MP9 | D_IO/A_IO | Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3 |
| 33 | PGND | PWR | PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. Decouple PGND to PVDD by using a 100 nF capacitor. |
| 34 | PVDD | PWR | 3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. Decouple this pin to PGND by using a 100 nF capacitor. |
| 35 | PLL_LF | A_OUT | PLL Loop Filter Connection. Two capacitors and a resistor need to be connected to this pin, as shown |
| Pin No. | Mnemonic | Type1 | Description |
| --- | --- | --- | --- |
| 33 | PGND | PWR | PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. Decouple PGND to PVDD by using a 100 nF capacitor. |
| 34 | PVDD | PWR | 3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. Decouple this pin to PGND by using a 100 nF capacitor. |
| 35 | PLL_LF | A_OUT | PLL Loop Filter Connection. Two capacitors and a resistor need to be connected to this pin, as shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details. |
| 36, 48 | AVDD | PWR | 3.3 V Analog Supply. Decouple this pin to AGND by using a 100 nF capacitor. |
| 38, 39 | PLL_MODE0, PLL_MODE1 | D_IN | PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency of the master clock PLL. See the Setting Master Clock/PLL Mode section for more details. |
| 40 | CM | A_OUT | 1.5 V Common-Mode Reference. Connect a 47 μF decoupling capacitor between this pin and ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is not critical. This pin can be used to bias external analog circuits, as long as those circuits are not drawing current from the pin (such as when CM is connected to the noninverting input of an op amp). |
| 41 | FILTD | A_OUT | DAC Filter Decoupling Pin. Connect a 10 μF capacitor between this pin and ground. The capacitor material is not critical. The voltage on this pin is 1.5 V. |
| 43 to 46 | VOUT3 | A_OUT | VOUT DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with either an active or passive output reconstruction filter. See the Audio DACs section for details. |
| 44 | VOUT2 | A_OUT | VOUT2 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with either an active or passive output reconstruction filter. See the Audio DACs section for details. |
| 45 | VOUT1 | A_OUT | VOUT1 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with either an active or passive output reconstruction filter. See the Audio DACs section for details. |
| 46 | VOUT0 | A_OUT | VOUT0 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with either an active or passive output reconstruction filter. See the Audio DACs section for details. |
| 47 | FILTA | A_OUT | ADC Filter Decoupling Pin. A 10 μF capacitor should be connected between this pin and ground. The capacitor material is not critical. The voltage on this pin is 1.5 V. |
1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog input/output.
Absolute Maximum Ratings
Table 8.
| Parameter | Rating |
|---|---|
| DVDD to GND | 0 V to 2.2 V |
| AVDD to GND | 0 V to 4.0 V |
| IOVDD to GND | 0 V to 4.0 V |
| Digital Inputs | DGND - 0.3 V, IOVDD + 0.3 V |
| Maximum Junction Temperature | 135°C |
| Temperature Range | |
| Storage | -65°C to +150°C |
| Operating | 0°C to +70°C |
| Soldering (10 sec) | 300°C |
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
Table 9. Thermal Resistance
| Package Type | θJA | θJC | Unit |
|---|---|---|---|
| 48-Lead LQFP | 72 | 19.5 | °C/W |
ESD CAUTION
Thermal Information
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
Table 9. Thermal Resistance
| Package Type | θJA | θJC | Unit |
|---|---|---|---|
| 48-Lead LQFP | 72 | 19.5 | °C/W |
Typical Application
SELF-BOOT MODE
Figure 37. Self-Boot Mode Schematic
I 2 C CONTROL
Figure 38. I 2C Control Schematic
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| ADAU1701 | Analog Devices Inc. | — |
| ADAU1701A | Analog Devices Inc. | — |
| ADAU1701C | Analog Devices Inc. | — |
| ADAU1701D | Analog Devices Inc. | — |
| ADAU1701H | Analog Devices Inc. | — |
| ADAU1701JSTZ | Analog Devices Inc. | 48-LQFP |
| ADAU1701JSTZ-RL | Analog Devices Inc. | — |
| ADAU1701M | Analog Devices Inc. | — |
| ADAU1701R | Analog Devices Inc. | — |
| ADAU1701S | Analog Devices Inc. | — |
| ADAU1701T | Analog Devices Inc. | — |
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