ADAU1701CAN
Audio Processor with Integrated ADCs and DACsThe ADAU1701CAN is a audio processor with integrated adcs and dacs from Analog Devices. View the full ADAU1701CAN datasheet below including key specifications, absolute maximum ratings.
ADAU1701CAN shares its datasheet with ADAU1701, whose page lists every part number it covers.
Official ADAU1701CAN datasheet (PDF) — the source this page was extracted from.
ADAU1701CAN Key Specifications
| Parameter | Value |
|---|---|
| Clock Rate | 50MHz |
| Interface | I2C, SPI |
| Mounting Type | Surface Mount |
| On-Chip RAM | 12kB |
| Operating Temperature | 0°C ~ 70°C (TA) |
| Package / Case | 48-LQFP |
| Supplier Device Package | 48-LQFP (7x7) |
| Type | Sigma |
| Voltage - Core | 1.80V |
| Voltage - I/O | 3.30V |
ADAU1701CAN Overview
Part: ADAU1701 — Analog Devices
Type: Audio DSP with Integrated ADCs and DACs
Description: 28-/56-bit 50 MIPS digital audio processor featuring two 24-bit ADCs (100 dB SNR), four 24-bit DACs (104 dB SNR), self-boot capability, and up to 192 kHz sample rate support.
Operating Conditions:
- Supply voltage: 3.3 V (AVDD, PVDD, IOVDD), 1.8 V (DVDD)
- Operating temperature: 0 to 70 °C
- Master clock frequency: 12.288 MHz nominal (PLL supports 64 × fS, 256 × fS, 384 × fS, 512 × fS)
Absolute Maximum Ratings:
- Max supply voltage: 2.2 V (DVDD to GND), 4.0 V (AVDD to GND), 4.0 V (IOVDD to GND)
- Max junction/storage temperature: 135 °C junction, -65 °C to +150 °C storage
Key Specs:
- ADC Dynamic Range: 100 dB A-weighted (at -60 dB relative to full-scale)
- ADC THD + N: -83 dB (-3 dB relative to full-scale analog input)
- DAC Dynamic Range: 104 dB A-weighted (at -60 dB relative to full-scale)
- DAC THD + N: -90 dB (-1 dB relative to full-scale analog output)
- DAC Full-Scale Output: 0.9 V rms (2.5 V p-p)
- Operating Supply Current (AVDD + PVDD): 50 mA typ, 85 mA max
- Operating Supply Current (DVDD): 40 mA typ, 60 mA max
- Active Power Dissipation: 286.5 mW typ (AVDD, DVDD, PVDD)
Features:
- 28-/56-bit, 50 MIPS digital audio processor
- 2 Σ-Δ ADCs and 4 Σ-Δ DACs with 98.5 dB analog input-to-output dynamic range
- Self-boot mechanism from external serial EEPROM
- Auxiliary ADC with 4-input multiplexer for analog control
- Multipurpose GPIO pins for digital control and interfacing
- Programmable via SigmaStudio graphical software tool
- Flexible serial data I/O ports supporting I2S, left-justified, right-justified, and TDM modes
- Integrated on-chip voltage regulator for 3.3 V single-supply systems
Applications:
- Multimedia speaker systems
- MP3 player speaker docks
- Automotive head units
- Minicomponent stereos
- Digital televisions
- Studio monitors
- Speaker crossovers
- Musical instrument effects processors
- In-seat sound systems (aircraft/motor coaches)
Package:
- 48-lead LQFP
ADAU1701CAN Features
28-/56-bit, 50 MIPS digital audio processor 2 ADCs: SNR of 100 dB, THD + N of -83 dB 4 DACs: SNR of 104 dB, THD + N of -90 dB Complete standalone operation Self-boot from serial EEPROM Auxiliary ADC with 4-input mux for analog control GPIOs for digital controls and outputs Fully programmable with SigmaStudio graphical tool 28-bit × 28-bit multiplier with 56-bit accumulator for full
double-precision processing Clock oscillator for generating a master clock from crystal PLL for generating master clock from 64 × fS, 256 × fS,
384 × fS, or 512 × fS clocks Flexible serial data input/output ports with I 2 S-compatible,
left-justified, right-justified, and TDM modes Sampling rates of up to 192 kHz are supported On-chip voltage regulator for compatibility with 3.3 V systems 48-lead, plastic LQFP
ADAU1701CAN Applications
Multimedia speaker systems MP3 player speaker docks Automotive head units Minicomponent stereos Digital televisions Studio monitors Speaker crossovers Musical instrument effects processors
In-seat sound systems (aircraft/motor coaches)
ADAU1701CAN Pin Configuration
Figure 7. 48-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
| Pin No. | Mnemonic | Type 1 | Description |
|---|---|---|---|
| 1, 37, 42 | AGND | PWR | Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. Decouple AGND to an AVDDpin with a 100 nF capacitor. |
| 2 | ADC0 | A_IN | Analog Audio Input 0. Full-scale 100 μA rms input. Current input allows input voltage level to be scaled with an external resistor. An 18 kΩ resistor gives a 2V rms full-scale input. See the Audio ADCs section for details. |
| 3 | ADC_RES | A_IN | ADCReference Current. Set the full-scale current of the ADCs with an external 18 kΩ resistor connected between this pin and ground. See the Audio ADCs section for details. |
| 4 | ADC1 | A_IN | Analog Audio Input 1. Full-scale 100 μA rms input. Current input allows the input voltage level to be scaled with an external resistor. An 18 kΩ resistor gives a 2V rms full-scale input. |
| 5 | RESET | D_IN | Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1701 exits reset on a low-to-high edge. For more information about initialization, see the Power-Up Sequence section for details. |
| 6 | SELFBOOT | D_IN | Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting this pin high initiates aself-boot operationwhentheADAU1701is brought out of a reset. This pin can be tied directly to the control voltage or pulled up/down with a resistor. See the Self-Boot section for details. |
| 7 | ADDR0 | D_IN | I 2 C and SPI Address 0. In combination with ADDR1 function on Pin 20, this pin allows up to four ADAU1701 devices to be used on the same I 2 C bus and up to two ICs to be used with a common SPI CLATCH signal. See the I 2 C Port section for details. |
| 8 | MP4 | D_IO | Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK). See the Multipurpose Pins section for more details. |
| 9 | MP5 | D_IO | Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK). See the Multipurpose Pins section for more details. |
| 10 | MP1 | D_IO | Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0). See the Multipurpose Pins section for more details. |
| 11 | MP0 | D_IO | Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1). See the Multipurpose Pins section for more details. |
| 12, 25 | DGND | PWR | Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. Decouple DGNDtoaDVDDpin with a 100 nF capacitor. |
| 13, 24 | DVDD | PWR | 1.8V Digital Supply. This can be supplied either externally or generated from a 3.3V supply with the on-board 1.8V regulator. Decouple DVDDto DGNDwith a 100 nF capacitor. |
| Pin No. | Mnemonic | Type 1 | Description |
|---|---|---|---|
| 14 | MP7 | D_IO | Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1). See the Multipurpose Pins section for more details. |
| 15 | MP6 | D_IO | Multipurpose GPIO, Serial Output Port Data 0, orTDMData Output (SDATA_OUT0). See the Multipurpose Pins section for more details. |
| 16 | MP10 | D_IO | Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK). See the Multipurpose Pins section for more details. |
| 17 | VDRIVE | A_OUT | Drive for 1.8V Regulator. The base of the voltage regulator external PNP transistor is driven from VDRIVE. See theVoltage Regulator section for details. |
| 18 | IOVDD | PWR | Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage that should be seen on the digital input pins. This pin is also the supply for the digital output signals on the control port and MPpins. Always set IOVDD to 3.3 V. The current draw of this pin is variable because it is dependent on the loads of the digital outputs. |
| 19 | MP11 | D_IO | Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). See the Multipurpose Pins section for more details. |
| 20 | ADDR1/CDATA/WB | D_IN | I 2 C Address 1/SPI Data Input/EEPROM Write Back Trigger. This is a multifunction pin as follows: ADDR1: I 2 C Address 1. In combination with ADDR0, this sets the I 2 C address of the IC so that four ADAU1701 devices can be used on the same I 2 C bus. See the I 2 C Port section for details. CDATA: SPI Data Input. See the SPI Port section for details. WB: EEPROMWritebackTrigger.A rising (default) or falling (if set in the EEPROM messages) edge on this pin triggers a writeback of the interface registers to the external EEPROM. This function can be used to save parameter data on power-down. See the Self-Boot section for |
| 21 | CLATCH/WP | D_IO | details. SPI Latch Signal/Self-Boot EEPROMWrite Protect. This is a multifunction pin as follows: CLATCH: SPI Latch Signal. Must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction can take a different number of cycles on the CCLK pin to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. See the SPI Port section for details. WP: Self-Boot EEPROMWrite Protect. This pin is an open-collector output when in self-boot mode. The ADAU1701 pulls this low to enable writes to an external EEPROM. This pin |
| 22 | SDA/COUT | D_IO | should be pulled high to 3.3 V. See the Self-Boot section for details. I 2 C Data/SPI Data Output. This is a multifunction pin, as follows: SDA: I 2 C Data. This pin is a bidirectional open-collector. The line connected to this pin should have a 2.2 kΩ pull-up resistor. See the I 2 C Port section for details. COUT: This SPI data output is used for reading back registers and memory locations. It is three-stated when an SPI read is not active. See the SPI Port section for details. |
| 23 | SCL/CCLK | D_IO | I 2 C Clock/SPI Clock. This is a dual function pin, as follows: SCL: I 2 C Clock. This pin is always an open-collector input when in I 2 C control mode. In self- boot mode, this pin is an open-collector output (I 2 C master).The line connected to this pin should have a 2.2 kΩ pull-up resistor. See the I 2 C Port section for details. CCLK: SPI Clock. This pin can either run continuously or be gated off between SPI |
| 26 | MP9 | D_IO/A_IO | Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary ADC Input 0. See the Multipurpose Pins section for more details. |
| 27 | MP8 | D_IO/A_IO | Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary ADC Input 3. See the Multipurpose Pins section for more details. |
| 28 | MP3 | D_IO/A_IO | Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary ADC Input 2. See the Multipurpose Pins section for more details. |
| 29 | MP2 | D_IO/A_IO | Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary ADC Input 1. See the Multipurpose Pins section for more details. |
| 30 | RSVD | Reserved. Tie to ground, either directly or through a pull-down resistor. | |
| 31 | OSCO | D_OUT | Crystal Oscillator Circuit Output. Connect a 100 Ωdamping resistor between this pin and the crystal. Do not use this output to directly drive a clock to another IC. If the crystal oscillator is not used, this pin can be left disconnected. See the Using the Oscillator section for details. |
| 32 | MCLKI | D_IN | Master Clock Input. MCLKI can either be connected to a 3.3V clock signal or be the input from the crystal oscillator circuit. See the Setting Master Clock/PLL Mode section for details. |
| Pin No. | Mnemonic | Type 1 | Description |
|---|---|---|---|
| 33 | PGND | PWR | PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. Decouple PGND to PVDD by using a 100 nF capacitor. |
| 34 | PVDD | PWR | 3.3V Power Supply for the PLL and the Auxiliary ADC Analog Section. Decouple this pin to PGND by using a 100 nF capacitor. |
| 35 | PLL_LF | A_OUT | PLL LoopFilter Connection.Two capacitors andaresistorneedtobe connectedto this pin, as shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details. |
| 36, 48 | AVDD | PWR | 3.3V Analog Supply. Decouple thispintoAGNDbyusinga100nFcapacitor. |
| 38, 39 | PLL_MODE0, PLL_MODE1 | D_IN | PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency of the master clock PLL. See the Setting Master Clock/PLL Mode section for more details. |
| 40 | CM | A_OUT | 1.5V Common-Mode Reference. Connect a 47 μF decoupling capacitor betweenthispinand groundtoreduce crosstalkbetweentheADCsand DACs.The material of the capacitors is not critical. This pin can be used to bias external analog circuits, as long as those circuits are not drawing current from the pin (such as when CMis connected to the noninverting input of an op amp). |
| 41 | FILTD | A_OUT | DAC Filter Decoupling Pin. Connect a 10 μF capacitor between this pin and ground. The capacitor material is not critical.The voltage on this pin is 1.5 V. |
| 43 to 46 | VOUT3 | A_OUT | VOUT DAC Output. The full-scale output voltage is 0.9V rms. This output can be used with either anactive or passive output reconstruction filter. See the Audio DACssection for details. |
| 44 | VOUT2 | A_OUT | VOUT2 DAC Output. The full-scale output voltage is 0.9V rms. This output can be used with either anactive or passive output reconstruction filter. See the Audio DACssection for details. |
| 45 | VOUT1 | A_OUT | VOUT1 DAC Output. The full-scale output voltage is 0.9V rms. This output can be used with either anactive or passive output reconstruction filter. See the Audio DACssection for details. |
| 46 | VOUT0 | A_OUT | VOUT0 DAC Output. The full-scale output voltage is 0.9V rms. This output can be used with either anactive or passive output reconstruction filter. See the Audio DACssection for details. |
| 47 | FILTA | A_OUT | ADC Filter Decoupling Pin. A10 μF capacitor should be connected between this pin and ground. The capacitor material is not critical. The voltage on this pin is 1.5 V. |
ADAU1701CAN Absolute Maximum Ratings
Table 8.
| Parameter | Rating |
|---|---|
| DVDD toGND | 0V to 2.2V |
| AVDD toGND | 0V to 4.0V |
| IOVDDtoGND | 0V to 4.0V |
| Digital Inputs | DGND-0.3V, IOVDD + 0.3V |
| Maximum Junction Temperature | 135°C |
| Temperature Range | |
| Storage | -65°C to +150°C |
| Operating | 0°C to +70°C |
| Soldering (10 sec) | 300°C |
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
ADAU1701CAN Thermal Information
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
ADAU1701CAN Typical Application
Figure 37. Self-Boot Mode Schematic
06412-036
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| ADAU1701 | Analog Devices | — |
| ADAU1701A | Analog Devices | LQFP-48 |
| ADAU1701C | Analog Devices | LQFP-48 |
| ADAU1701D | Analog Devices | LQFP-48 |
| ADAU1701H | Analog Devices | LQFP-48 |
| ADAU1701JSTZ | Analog Devices | 48-LQFP |
| ADAU1701JSTZ-RL | Analog Devices | — |
| ADAU1701M | Analog Devices | LQFP-48 |
| ADAU1701R | Analog Devices | LQFP-48 |
| ADAU1701S | Analog Devices | LQFP-48 |
| ADAU1701T | Analog Devices | LQFP-48 |
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