The ADAU1462/ADAU1466 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP® devices. They are pin and register compatible with each other, as well as with the ADAU1450/ADAU1451/ADAU1452 SigmaDSP processors. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms support a seamless combination of stream processing (sample by sample), multirate processing, and block processing paradigms. The SigmaStudio™ graphical programming tool enables the creation of signal processing flows that are interactive, intuitive, and powerful. The enhanced digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.

The 1.2 V , 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 SIMD instructions per sample at the standard sample rate of 48 kHz. Powerful clock generator hardware, including a flexible phase-locked loop (PLL) with multiple fractional integer outputs, supports all industry standard audio sample rates. Nonstandard rates over a wide range can generate up to 15 sample rates simultaneously. These clock generators, along with the on board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1462/ADAU1466 ideal audio hubs that greatly simplify the design of complex multirate audio systems.

The ADAU1462/ADAU1466 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry with highly configurable serial ports, I 2 C, serial peripheral interface (SPI), Sony/Philips Digital Interconnect Format (S/PDIF) interfaces, and multipurpose input/output (I/O) pins.

Dedicated decimation filters can decode the pulse code modulation (PDM) output of up to four MEMS microphones.

Independent slave and master I 2 C/SPI control ports allow the ADAU1462/ADAU1466 to be programmed and controlled by an external master device such as a microcontroller, and to program and control slave peripherals directly. Self boot functionality and the master control port enable complex standalone systems.

The power efficient DSP core can execute at high computational loads while consuming only a few hundred milliwatts (mW) in typical conditions. This relatively low power consumption and small footprint make the ADAU1462/ADAU1466 ideal replacements for large, general-purpose DSPs that consume more power at the same processing load.

Note that throughout this data sheet, multifunction pins, such as SS_M/MP0, are referred to either by the entire pin name or by a single function of the pin, for example, MP0, when only that function is relevant.

Qualified for automotive applications

Fully programmable audio DSP for enhanced sound processing

Features SigmaStudio, a proprietary graphical programming tool for the development of custom signal flows

Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V

Up to 24 kWords of program memory

Up to 80 kWords of parameter/data RAM

Up to 6144 SIMD instructions per sample at 48 kHz

Up to 1600 ms digital audio delay pool at 48 kHz

Audio I/O and routing

4 serial input ports, 4 serial output ports

48-channel, 32-bit digital I/O up to a sample rate of 192 kHz

Flexible configuration for TDM, I 2 S, left and right justified formats, and PCM

Up to 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB dynamic range

Stereo S/PDIF input and output at 192 kHz

Four PDM microphone input channels

Multichannel, byte addressable TDM serial ports

Automotive audio processing

Head units

Distributed amplifiers

Rear seat entertainment systems

Trunk amplifiers

Commercial and professional audio processing

ADAU1466WBCPZ300 Pinout

Package: 72-VFQFN Exposed Pad

Pin	Name	Type	Description
1	DGND	P	Digital Ground
2	IOVDD	P	I/O Supply Voltage
3	VDRIVE	I	Drive Voltage Reference
4	SPDIFIN	I	S/PDIF Input
5	SPDIFOUT	O	S/PDIF Output
6	AGND	P	Analog Ground
7	AVDD	P	Analog Supply Voltage
8	AUXADC0	I	Auxiliary ADC Input 0
9	AUXADC1	I	Auxiliary ADC Input 1
10	AUXADC2	I	Auxiliary ADC Input 2
11	AUXADC3	I	Auxiliary ADC Input 3
12	AUXADC4	I	Auxiliary ADC Input 4
13	AUXADC5	I	Auxiliary ADC Input 5
14	POIN	I	Parallel Output Input
15	PVDD	P	PLL Supply Voltage
16	PLLFILTER	I	PLL Filter
17	DGND	P	Digital Ground
18	IOVDD	P	I/O Supply Voltage
19	DGND	P	Digital Ground
20	DVDD	P	Digital Supply Voltage
21	SCLK	I	Serial Clock
22	LRCLK	I	Left/Right Clock
23	SDATA_OUT	O	Serial Data Output
24	XTAL_OUT	O	Crystal Oscillator Output
25	RESET	I	Reset Input
26	DGND	P	Digital Ground
27	SS_MMP1	I/O	SigmaDSP Serial Port MMP1
28	SS_MMP2	I/O	SigmaDSP Serial Port MMP2
29	MOSI_MMP1	I/O	SigmaDSP Serial Port MOSI MMP1
30	MOSI_MMP2	I/O	SigmaDSP Serial Port MOSI MMP2
31	MISO_SCL_MOSI_MMP3	I/O	SigmaDSP Serial Port MISO/SCL/MOSI MMP3
32	SCL_MOSI_MMP4	I/O	SigmaDSP Serial Port SCL/MOSI MMP4
33	SDA_MISO_SCL	I/O	SigmaDSP Serial Port SDA/MISO/SCL
34	SDATA_IN	I	Serial Data Input
35	DGND	P	Digital Ground
36	DGND	P	Digital Ground
37	IOVDD	P	I/O Supply Voltage
38	IOVDD	P	I/O Supply Voltage
39	LRCLK_OUT/MP4	O	Left/Right Clock Output / Multipurpose Pin 4
40	BCLK_OUT0	O	Bit Clock Output 0
41	SDATA_OUT0	O	Serial Data Output 0
42	LRCLK_OUT1/MP5	O	Left/Right Clock Output 1 / Multipurpose Pin 5
43	BCLK_OUT1	O	Bit Clock Output 1
44	SDATA_OUT1	O	Serial Data Output 1
45	MP6	I/O	Multipurpose Pin 6
46	MP7	I/O	Multipurpose Pin 7
47	LRCLK_OUT2/MP8	O	Left/Right Clock Output 2 / Multipurpose Pin 8
48	BCLK_OUT2	O	Bit Clock Output 2
49	SDATA_OUT2	O	Serial Data Output 2
50	LRCLK_OUT3/MP9	O	Left/Right Clock Output 3 / Multipurpose Pin 9
51	BCLK_OUT3	O	Bit Clock Output 3
52	SDATA_OUT3	O	Serial Data Output 3
53	DVDD	P	Digital Supply Voltage
54	DGND	P	Digital Ground
55	DGND	P	Digital Ground
56	IOVDD	P	I/O Supply Voltage
57	SCLK_IN	I	Serial Clock Input
58	LRCLK_IN	I	Left/Right Clock Input
59	SDATA_IN	I	Serial Data Input
60	BCLK_IN	I	Bit Clock Input
61	SDATA_IN	I	Serial Data Input
62	BCLK_IN	I	Bit Clock Input
63	SDATA_IN	I	Serial Data Input
64	BCLK_IN	I	Bit Clock Input
65	SDATA_IN	I	Serial Data Input
66	BCLK_IN	I	Bit Clock Input
67	SDATA_IN	I	Serial Data Input
68	BCLK_IN	I	Bit Clock Input
69	SDATA_IN	I	Serial Data Input
70	BCLK_IN	I	Bit Clock Input
71	DVDD	P	Digital Supply Voltage
72	DGND	P	Digital Ground
EP	Exposed Pad	P	Thermal/Ground Pad (connect to DGND)

Notes

• Pin names with "/" indicate alternate functions (e.g., LRCLK_OUT1/MP5 can function as either LRCLK_OUT1 or MP5 depending on configuration).
• Multiple pins share the same name (e.g., SDATA_IN, BCLK_IN, DGND, IOVDD, DVDD) indicating multiple instances of these signals throughout the device.
• The exposed pad (EP) should be connected to digital ground (DGND) for proper thermal and electrical performance.
• This pinout is specific to the ADAU1466WBCPZ300 variant in 72-VFQFN package.

Digital Input/Output

Table 4.

Parameter	Min	Typ	Max	Unit	Test Conditions/Comments
DIGITAL INPUT
Input Voltage					Excluding SPDIFIN, which is not a standard digital input
IOVDD = 3.3V
High Level (V IH )	1.71		3.3	V
Low Level (V IL )	0		1.71	V
IOVDD = 1.8V
High Level (V IH )	0.92		1.8	V
Low Level (V IL )	0		0.89	V
Input Leakage
High Level (I IH )			2	μA	Digital input pins with pull-up resistor
			14	μA	Digital input pins with pull-down resistor
			2	μA	Digital input pins with no pull resistor
			8	μA	MCLK
			120	μA	SPDIFIN
Low Level (I IL ) at 0V	-14			μA	Digital input pins with pull-up resistor
	-2			μA	Digital input pins with pull-down resistor
	-2			μA	Digital input pins with no pull resistor
	-8			μA	MCLK
	-120			μA	SPDIFIN
Input Capacitance (C I )		2		pF	Guaranteed by design
DIGITAL OUTPUT
Output Voltage
IOVDD = 3.3V High Level (V OH )	3.09		3.3	V	I OH =1mA
Low Level (V OL )	0		0.26	V	I OL =1mA
IOVDD = 1.8V
High Level (V OH )	1.45		1.8
Low Level (V OL )	0		0.33
Digital Output Pins, Output Drive					Thedigital output pins are driving low impedance PCBtraces to a
IOVDD=1.8V
Drive Strength Setting Lowest			1	mA	The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly
Low			2	mA	The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly
High			3	mA	The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly
Highest			5	mA	The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly
IOVDD= 3.3V
Drive Strength Setting
Lowest			2	mA	The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly
Low			5	mA	The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly
High			10	mA	The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly
Highest			15	mA	The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly

Table 16.

Parameter	Rating
DVDD to Ground	0V to 1.4V
AVDD to Ground	0V to 4.0V
IOVDD to Ground	0V to 4.0V
PVDD to Ground	0V to 4.0V
Digital Inputs	DGND-0.3V to IOVDD + 0.3V
MaximumAmbientTemperatureRange	-40°C to +105°C
MaximumJunctionTemperature	125°C
Storage Temperature Range	-65°C to +150°C
Soldering (10 sec)	300°C

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

The capabilities of the ADAU1462/ADAU1466 are such that it is possible to configure the device in a mode where its power dissipation can risk exceeding the absolute maximum junction temperature. The junction temperature reached in a device is influenced by several factors, for example, the power dissipated in the device; the thermal efficiency of the printed circuit board (PCB) design; the maximum ambient temperature supported in the application.

To ensure that the ADAU1462/ADAU1466 does not exceed its absolute maximum junction temperature in an application, thermal considerations must be taken from the start of the design (for example: likely modes of operation, thermal considerations in the PCB design (see the AN-772 Application Note), and thermal simulations) to its finish (qualification at the maximum ambient temperature supported in the application).

While all of the following thermal coefficients can be used to analyze the thermal performance of ADAU1462/ADAU1466, ψJT is the most reflective of real-world applications and is recommended as the primary approach for thermal qualification.

Table 17. Thermal Coefficients for ADAU1462/ADAU1466

Thermal Coefficient	Value	Unit
ψ JT 1	0.15	°C/W
θ JA 1	29.15	°C/W
θ JB 2	10.59	°C/W
θ JCT 3	0.04	°C/W
θ JCB 4	3.39	°C/W

• 1 Based on simulation using a JEDEC 2s2p thermal test PCB with 25 thermal vias in a JEDEC natural convection environment, as per JESD51.
• 2 Based on simulation using a JEDEC 2s2p thermal test PCB with 25 thermal vias in a JEDEC Junction to Board environment, as per JESD51.

3 Based on simulation using a cold plate attached directly to exposed paddle.

To employ the ψJT-based approach to thermal analysis,

1. Configure the ADAU1462/ADAU1466 in the highest power mode of operation to be used in the application and record the power dissipated in the device.
2. Compute the maximum allowable surface temperature, TS_MAX:

TS_MAX = TJ_MAX - ( Power × ψJT )

1. Measure the case temperature at the center of the ADAU1462/ADAU1466 package (TS) at the maximum ambient temperature supported in the application and compare to TS_MAX.
2. For safe operation, use TS < TS_MAX in the highest power mode of operation in the application.

For more information, see the PCB Design Considerations section and the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) .

Figure 90. Automotive Infotainment Amplifier Block Diagram

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