A4988
Stepper Motor Driver ModuleThe A4988 is a stepper motor driver module from Allegro MicroSystems. View the full A4988 datasheet below including pinout.
Manufacturer
Allegro MicroSystems
Category
Motor DriversOverview
Part: Allegro A4988 Stepper Motor Driver (Handson Technology Module SKU: DRV1000)
Type: Microstepping Bipolar Stepper Motor Driver
Description: A breakout board for Allegro's A4988 microstepping bipolar stepper motor driver, operating from 8–35V, delivering up to 2A per phase with sufficient cooling, and featuring adjustable current limiting and five micro-step resolutions.
Operating Conditions:
- Supply voltage: 8–35V
- Logic voltage: 3–5.5V
Absolute Maximum Ratings:
- Max operating voltage: 35V
- Max continuous current: 2A (with heatsink)
- Max junction/storage temperature: null
Key Specs:
- Minimum operating voltage: 8V
- Maximum operating voltage: 35V
- Continuous current per phase: 1A (without heatsink)
- Maximum current per phase: 2A (with heatsink)
- Minimum logic voltage: 3V
- Maximum logic voltage: 5.5V
- Micro-step Resolutions: 1, 1/2, 1/4, 1/8, 1/16
Features:
- Adjustable current limiting
- Overcurrent protection
- Over-temperature protection
- Five different micro-step resolutions (down to 1/16-step)
Applications:
- null
Package:
- Module size: 0.6″ × 0.8″
Pin Configuration
A4988 Pinout
Package: 28-contact QFN with exposed thermal pad (5 mm × 5 mm × 0.90 mm, ET package)
| Pin # | Pin Name | Type | Description |
|---|---|---|---|
| 1 | GND | P | Ground |
| 2 | SLEEP | I | Sleep mode control (active low) |
| 3 | GND | P | Ground (internally fused for thermal dissipation) |
| 4 | STEP | I | Step input (rising edge advances motor one microstep) |
| 5 | MS1 | I | Microstep select 1 (100 kΩ pull-down) |
| 6 | MS2 | I | Microstep select 2 (50 kΩ pull-down) |
| 7 | MS3 | I | Microstep select 3 (100 kΩ pull-down) |
| 8 | DIR | I | Direction control (sets motor rotation direction) |
| 9 | ENABLE | I | Output enable (active low; high disables FET outputs) |
| 10 | RESET | I | Reset input (active low; sets translator to home state) |
| 11 | VREF | I | Reference voltage input for current regulation (0–4 V) |
| 12 | GND | P | Ground |
| 13 | SENSE1 | I | Current sense input for phase 1 (−0.5 to +0.5 V) |
| 14 | OUT1B | O | Phase 1 output B (motor winding connection) |
| 15 | OUT1A | O | Phase 1 output A (motor winding connection) |
| 16 | VBB2 | P | Motor supply voltage (8–35 V) |
| 17 | VBB1 | P | Motor supply voltage (8–35 V) |
| 18 | GND | P | Ground (internally fused for thermal dissipation) |
| 19 | VCP | P | Charge pump supply (0.1 µF capacitor to GND required) |
| 20 | CP2 | P | Charge pump output (0.1 µF capacitor to CP1 required) |
| 21 | CP1 | P | Charge pump input (0.1 µF capacitor to CP2 required) |
| 22 | ROSC | I | Off-time resistor/configuration pin (determines PWM off-time and decay mode) |
| 23 | VREG | O | Internal 7 V regulator output (0.22 µF capacitor to GND required) |
| 24 | VDD | P | Logic supply voltage (3–5.5 V) |
| 25 | GND | P | Ground |
| 26 | SENSE2 | I | Current sense input for phase 2 (−0.5 to +0.5 V) |
| 27 | OUT2B | O | Phase 2 output B (motor winding connection) |
| 28 | OUT2A | O | Phase 2 output A (motor winding connection) |
| — | Exposed Pad | P | Thermal pad (internally connected to GND; solder directly to PCB for heat dissipation) |
Notes
- Pins 3 and 18 are internally fused and provide enhanced thermal dissipation paths; solder directly to exposed PCB surface with thermal vias.
- SENSE1 and SENSE2 pins must not exceed ±0.5 V; use low-impedance traces directly to sense resistors and star ground.
- MS1, MS2, MS3 pins have internal pull-down resistances (100 kΩ, 50 kΩ, 100 kΩ respectively); combined state determines microstep resolution (full, 1/2, 1/4, 1/8, 1/16 step).
- ROSC pin configuration determines fixed off-time and decay mode: tied to VDD (30 µs, auto-mixed), tied to GND (30 µs, mixed always), or through resistor (formula-based, auto-mixed except full-step).
- VCP and VREG require 0.1 µF and 0.22 µF ceramic capacitors respectively (Class 2 dielectric, ±15% tolerance).
- CP1 and CP2 require 0.1 µF ceramic capacitor between them for charge pump operation.
- VBB1 and VBB2 should be decoupled with bulk and ceramic capacitors placed close to device.
- Logic inputs (STEP, DIR, MS1–MS3, ENABLE, RESET, SLEEP) are 3.3 V and 5 V compatible.
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