nRF52805-CAAA-R

Part: nRF52805-CAAA-R — Nordic Semiconductor

Type: Bluetooth 5.0 / proprietary 2.4 GHz SoC with Arm Cortex-M4

Description: Arm Cortex-M4 SoC at 64 MHz with a 2.4 GHz Bluetooth 5.0 transceiver (-97 dBm sensitivity at 1 Mbps BLE), 192 kB flash, 24 kB RAM and a 1.7–3.6 V supply range.

Operating Conditions:

• Supply voltage: 1.7–3.6 V (nominal 3.0 V)
• Operating temperature: -40 to +85 °C
• Supply rise time (0 V to 1.7 V): 60 ms max

Absolute Maximum Ratings:

• Max supply voltage (VDD): 3.9 V
• I/O pin voltage: -0.3 V to VDD + 0.3 V (VDD ≤ 3.6 V); -0.3 V to 3.9 V (VDD > 3.6 V)
• Storage temperature: -40 to +125 °C

Key Specs:

• Supply voltage range: 1.7–3.6 V
• Operating temperature: -40 to +85 °C
• Receiver sensitivity: -97 dBm (1 Mbps BLE)
• TX power: -20 to +4 dBm, configurable in 4 dB steps
• Peak current: 4.6 mA in TX (0 dBm), 4.6 mA in RX
• CPU efficiency: 34.4 μA/MHz running CoreMark from flash; 32.8 μA/MHz from RAM
• System OFF current at 3 V: 0.3 μA with no RAM retention, 0.5 μA with full 24 kB RAM retention
• System ON current at 3 V (wake on RTC from LFXO): 1.1 μA with full 24 kB RAM retention, 1.0 μA with no RAM retention
• ESD: HBM 3 kV (Class 2), CDM 1 kV
• Flash endurance: 10,000 write/erase cycles; retention 10 years at 85 °C

Features:

• Bluetooth 5.0, 2.4 GHz transceiver (2 Mbps and 1 Mbps) plus proprietary 2.4 GHz modes
• On-air compatible with nRF52, nRF51, nRF24L and nRF24AP Series
• Single-ended antenna output (on-chip balun)
• Arm Cortex-M4 32-bit processor at 64 MHz, 144 EEMBC CoreMark score
• 192 kB flash and 24 kB RAM
• On-chip DC/DC and LDO regulators with automated low-current modes
• Single crystal operation
• Serial wire debug (SWD)
• Programmable peripheral interconnect (PPI) and EasyDMA
• 10 general purpose I/O pins
• 12-bit, 200 ksps ADC with 2 configurable channels
• 3x 32-bit timers, 2x RTC
• SPI master/slave, I2C compatible two-wire master/slave, UART (CTS/RTS)
• Quadrature decoder (QDEC)
• AES hardware encryption
• Temperature sensor
• Nordic SoftDevice ready with concurrent multiprotocol support

Applications:

• Proprietary protocol devices
• Network processor
• Beacons
• Smart home sensors
• Presenters/Stylus
• Health monitoring
• Drug delivery
• Asset tags
• Toys
• Retail tags and labels

Package:

• WLCSP, 2.482 x 2.464 mm

• Bluetooth ® 5.0, 2.4 GHz transceiver
• -97 dBm sensitivity in 1 Mbps Bluetooth ® Low Energy mode
• -20 to +4 dBm TX power, configurable in 4 dB steps
• On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series
• Supported data rates:
• Bluetooth ® 5.0 - 2 Mbps, 1 Mbps
• Proprietary 2.4 GHz - 2 Mbps, 1 Mbps
• Single-ended antenna output (on-chip balun)
• 4.6 mA peak current in TX (0 dBm)
• 4.6 mA peak current in RX
• RSSI (1 dB resolution)
• Arm ® Cortex ® -M4 32-bit processor, 64 MHz
• 144 EEMBC CoreMark ® score running from flash memory
• 34.4 μA/MHz running CoreMark from flash memory
• 32.8 μA/MHz running CoreMark from RAM
• Serial wire debug (SWD)
• Flexible power management
• 1.7 V to 3.6 V supply voltage range
• On-chip DC/DC and LDO regulators with automated low current modes
• Fast wake-up using 64 MHz internal oscillator
• 0.3 μA at 3 V in System OFF mode, no RAM retention
• 0.5 μA at 3 V in System OFF mode with full 24 kB RAM retention
• 1.1 μA at 3 V in System ON mode, with full 24 kB RAM retention, wake on RTC (running from LFXO clock)
• 1.0 μA at 3 V in System ON mode, no RAM retention, wake on RTC (running from LFXO clock)

• Proprietary protocol devices
• Network processor
• Beacons
• Smart Home sensors
• Presenters/Stylus
• 192 kB flash and 24 kB RAM
• Advanced on-chip interfaces
• Programmable peripheral interconnect (PPI)
• 10 general purpose I/O pins
• EasyDMA automated data transfer between memory and peripherals
• Nordic SoftDevice ready with support for concurrent multiprotocol
• Temperature sensor
• 12-bit, 200 ksps ADC - 2 configurable channels with programmable gain
• 3x 32-bit timer with Counter mode
• SPI master/slave with EasyDMA
• I 2 C compatible two-wire master/slave
• UART (CTS/RTS) with EasyDMA
• Quadrature decoder (QDEC)
• AES HW encryption with EasyDMA
• 2x real-time counter (RTC)
• Single crystal operation
• Package variants
• WLCSP package, 2.482 x 2.464 mm
• Health monitoring
• Drug delivery
• Asset tags
• Toys
• Retail tags and labels

Pins can be individually configured through the SENSE field in the PIN_CNF[n] register to detect either a high or low level input.

When the correct level is detected on a configured pin, the sense mechanism will set the DETECT signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register, combines all DETECT signals from the pins in the GPIO port into one common DETECT signal and routes it through the system to be utilized by other peripherals. This mechanism is functional in both System ON and System OFF mode. See GPIO port and the GPIO pin details on page 107.

The following figure illustrates the GPIO port containing 32 individual pins, where PIN0 is shown in more detail for reference. All signals on the left side of the illustration are used by other peripherals in the system and therefore not directly available to the CPU.

Figure 35: GPIO port and the GPIO pin details

Pins should be in a level that cannot trigger the sense mechanism before being enabled. If the SENSE condition configured in the PIN_CNF registers is met when the sense mechanism is enabled, the DETECT signal will immediately go high. A PORT event is triggered if the DETECT signal was low before enabling the sense mechanism. See GPIOTE - GPIO tasks and events on page 113.

See the following peripherals for more information about how the DETECT signal is used:

• POWER - Power supply on page 49 - uses the DETECT signal to exit from System OFF mode.
• GPIOTE - GPIO tasks and events on page 113 - uses the DETECT signal to generate the PORT event.

When a pin's PINx.DETECT signal goes high, a flag is set in the LATCH register. For example, when the PIN0.DETECT signal goes high, bit 0 in the LATCH register is set to 1 . If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by writing a 1 to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT signal being set low.

The LDETECT signal will be set high when one or more bits in the LATCH register are 1 . The LDETECT signal will be set low when all bits in the LATCH register are successfully cleared to 0 .

If one or more bits in the LATCH register are 1 after the CPU has performed a clear operation on the LATCH register, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal behavior on page 108.

Note: The CPU can read the LATCH register at any time to check if a SENSE condition has been met on any of the GPIO pins. This is still valid if that condition is no longer met at the time the CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as the DETECT signal.

The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE register. It is possible to change from default behavior to the DETECT signal that is derived directly from the LDETECT signal. See GPIO port and the GPIO pin details on page 107. The following figure illustrates the DETECT signal behavior for these two alternatives.

Figure 36: DETECT signal behavior

A GPIO pin input buffer can be disconnected from the pin to enable power savings when the pin is not used as an input, see GPIO port and the GPIO pin details on page 107. Input buffers must be connected to get a valid input value in the IN register, and for the sense mechanism to get access to the pin.

Other peripherals in the system can connect to GPIO pins and override their output value and configuration, or read their analog or digital input value. See GPIO port and the GPIO pin details on page 107.

Selected pins also support analog input signals, see ANAIN in GPIO port and the GPIO pin details on page 107. The assignment of the analog pins can be found in Pin assignments on page 346.

Note: When a pin is configured as digital input, increased current consumption occurs when the input voltage is between VIL and VIH. It is good practice to ensure that the external circuitry does not drive that pin to levels between VIL and VIH for a long period of time.

Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the device. 35

Table 111: Absolute maximum ratings

The operating conditions are the physical parameters that the chip can operate within.

Table 110: Recommended operating conditions

Important: The on-chip power-on reset circuitry may not function properly for rise times longer than the specified maximum.