ZD25WQ16CEIGR

Part: ZD25WQ16B

Type: Serial Multi I/O Flash Memory

Key Specs:

• Memory Size: 16M-bit
• Supply Voltage Range: 1.65V to 3.6V
• Read Current: 2.5mA
• Program/Erase Current: 2.5mA
• Deep Power Down Current: 0.1uA
• Standby Current: 12uA
• Program/Erase Cycles: 100,000 cycles
• Data Retention: 20 years
• Operating Temperature Range: -40°C to 85°C
• Chip Erase Time: 10ms
• Page Program Time: 1.3ms
• 4K-byte Sector Erase Time: 10ms
• 32K/64K-byte Block Erase Time: 10ms

Features:

• X1, X2, X4 Multi I/O Support
• SPI Compatible (Mode 0 and Mode 3)
• Page, Sector, Block, and Full Chip Erase
• One Time Programmable (OTP) Security Register (3x512-Byte)
• Software Protection Mode (BlockProtect bits)
• Hardware Protection Mode (WP Pin)
• 128-bit Unique ID
• Program/Erase Suspend and Resume
• JEDEC Standard Manufacturer and Device ID Read
• Burst Read (8/16/32/64 byte Wrap-Around)

Applications:

• High-volume consumer applications
• Program code shadowing from Flash memory into embedded or external RAM
• Data storage

Package:

• 8-Lead SOP: 150mil, 208mil
• 8-Lead TSSOP: 173mil
• 8-Land USON: 3x2mm
• 8-Land WSON: 6x5mm
• WLCSP
• KGD for SiP

• One Time Programmable (OTP) Security Register
  • 3*512-Byte Security Registers With OTP Lock
• Software Protection Mode
  • TheBlockProtect(BP4,BP3,BP2,BP1,andBP0)bits definethesection ofthememoryarray that canbe read but not change.
• 128 bit unique ID for each device
• Program/Erase Suspend and Program/Erase Resume
• JEDEC Standard Manufacturer and Device ID Read Methodology

8-PIN SOP (150mil/200mil) andTSSOP

4.1.Absolute Maximum Ratings

NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Figure 4-1 Maximum Overshoot Waveform

Maxinum Negative Overshoot Waveform Maxinum Positive Overshoot Waveform

Table 4-1 Pin Capacitance [1]

Note:

Test Conditions: T^A = 25°C, F = 1MHz, Vcc = 3.0V.

Figure 4-2 Input Test Waveforms and Measurement Level

Figure 4-3 Output Loading

4.2.DC Characteristics

Table 4-2 DC parameters

Note

1. Typical values measured at 1.8V @ 25°C for the1.65V to 3.6V range.2. Typical values measured at 3.0V @ 25°C for the2.3V to 3.6V range.

4.3.AC Characteristics

Table 4-3 AC parameters

4.4.AC Characteristics for Program and Erase

Table 4-4 AC parameters fro program and erase

Note

1. tCH + tCL must be greater than or equal to 1/ Frequency.

2. Typical values givenfor TA=25°C. Not 100% tested.

3. Only applicable as a constraint for a WRSR instruction.

4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be observed before issuing the next program suspend command. However, in order for an Program operation to make progress, tPRS ≥ 100us must be included in resume-to-suspend loop(s). Not 100% tested.

5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be observed before issuing the next erase suspend command. However, in order for an Erase operation to make progress, tERS ≥ 200us must be included in resume-to-suspend loop(s). Notes. Not 100% tested.

6. Latency time is required to complete Erase/Program Suspend operation.

7. The value guaranteed by characterization, not 100% tested in production.

Figure 4-4 Serial Input Timing

Figure 4-5 Output Timing

Figure 4-6 Hold Timing

Figure 4-7 WP Timing

4.5.Operation Conditions

At Device Power-Up and Power-Down

AC timing illustrated in "Figure AC Timing at Device Power-Up" and "Figure Power-Down Sequence" are for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operatecorrectly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 4-8 AC Timing at Device Power-Up

Figure 4-9 Power-Up Timing

Power Up/Down and Voltage Drop

For Power-down to Power-up operation, the VCC of flash device must below VPWD for atleast tPWD timing. Please check the table below formore detail.

Figure 4-10 Power down-up Timing

5. Commands

5.1.Commands listing

Figure 5-1 Command set

Command set (Cont'd)

1. Dual Output data IO0 = (D6, D4, D2,D0) IO1 = (D7, D5, D3,D1)

2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2,A0, M6, M4, M2, M0 IO1

= A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3,A1, M7, M5, M3, M1

1. Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3,…..)

2. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3

3. Fast Read Quad I/O Data

IO0 = (x, x, x, x,D4, D0,…) IO1 = (x, x, x, x,D5, D1,…) IO2 = (x, x, x, x,D6, D2,…) IO3 = (x, x, x, x,D7, D3,…)

1. Security Registers Address:

Security Register1: A23-A16=00H, A15-A9=0001000, A8-A0= Byte Address; Security Register2: A23-A16=00H, A15-A9=0010000, A8-A0= Byte Address; Security Register3: A23-A16=00H, A15-A9=0011000, A8-A0= Byte Address;

5.2.Write Enable (WREN)

high.

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,DPP,QPP, PE,SE, BE32K,BE, CE, and WRSR,ERSCUR, PRSCUR which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes

5.3.Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.

The WEL bit is reset by following situations:

• Power-up
• Write Disable (WRDI) instructioncompletion
• Write Status Register (WRSR) instruction completion
• Page Program (PP) instructioncompletion
• Dual Input Page Program (DPP) instructioncompletion
• Quod Page Program (QPP) instructioncompletion
• Page Erase (PE) instructioncompletion
• Sector Erase (SE) instructioncompletion
• Block Erase (BE32K,BE) instructioncompletion
• Chip Erase (CE) instructioncompletion
• Erase Security Register (ERSCUR) instruction completion
• Program Security Register (PRSCUR) instruction completion
• Reset (RST) instructioncompletion

Figure 5-3 Write Disable (WRDI) Sequence (Command 04)

5.4.Write Enable for Volatile Status Register

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles oraffecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values.

The sequence of issuing Write Enable for Volatile Status Register instruction is: CS# goes low→ sending Write Enable for Volatile Status Register instruction code→ CS# goes high.

Figure 5-4 Write Enable for Volatile Status Register Sequence (Command 50)

5.5.Read Status Register(RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. For command code "05H", the SO will output Status Register bits S7S0. The command code "35H", theSO will output Status Register bits S15S8.

The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out onSO.

The SIO[3:1] are "don't care".

Figure 5-5 Read Status Register (RDSR) Sequence (Command 05 or 35)

5.6.Read Configure Register (RDCR)

The RDCR instruction is for reading Configure Register Bits. The Read Configure Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configure Register data out onSO.

The SIO[3:1] are "don't care".

Figure 5-6 Read Configure Register (RDCR) Sequence (Command 15)

5.7.Active Status Interrupt (ASI)

To simplify the readout of the WIP bit, the Active Status Interrupt command (25h) may be used.It is then not necessary to continuously read the status register, it is sufficientto monitor the value of the SO line. If the SO line isconnected to an interrupt line on the host controller, the host controller may be in sleep mode until the SO line indicates that the device is ready for the next command.

The WIP bit can be read at any time, including during an internally self-timed program or erase operation. To enable the Active Status Interrupt command, the CS pin must first be asserted and the opcode of 25h must be clocked into the device. For SPI Mode0 and Mode3, at least one dummy bit has to be clocked into the device after the last bit of the opcode has been clocked in. (In mostcases, this is most easily done by sending a dummy byte to the device.) The value of the SI line after the opcode is clocked in isof no significance to the operation.

The value of WIP is then output on the SO line, and is continuously updated by the device for as long as the CS pin remains asserted. Additional clocks on the SCLK pin are not required. For SPI Mode3, SCLK must keep low. If the WIP bit changes from ¹ to ⁰ while the CS pin isasserted, the SO line will change from ¹ to 0.(The WIP bit cannot change from ⁰ to ¹ during an operation, so if the SO line already is 0, it will not change.)

Deasserting the CS pin will terminate the Active Status Interrupt operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

The sequence of issuing ASI instruction is: CS# goes low→ sending ASI instruction code→ WIP data out on SO.

Figure 5-7 Active Status Interrupt (ASI) Sequence (Command 25)

5.8.Write Status Register(WRSR)

The Write Status Register (WRSR) command allows new values to be written to the Status Register.Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. If CS# isdriven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will not change. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle isin progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is

completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goeshigh.

The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW)is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle isin progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Figure 5-8 Write Status Register (WRSR) Sequence (Command 01)

5.9.Write Configure Register (WRCR)

The Write Configure Register (WRCR) command allows new values to be written to the Configure Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The sequence of issuing WRCR instruction is: CS# goes low→ sending WRCR instruction code→ Configure Register data on SI→CS# goeshigh.

The CS# must go high exactly at the 8 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Configure Register Cycle is completed, and the Write Enable Latch (WEL) bit isreset.

Figure 5-9 Write Configure Register (WRCR) Sequence (Command 01)

5.10. Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out.

5.11. Read Data Bytes at Higher Speed(FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read outat a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 5-11 Read at Higher Speed (FAST_READ) Sequence (Command 0B)

5.12. Dual Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data isshifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 5-12 Dual Read Mode Sequence (Command 3B)

5.13. 2 X IO Read Mode(2READ)

The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached.

Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 8-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 5-13 2 X IO Read Mode Sequence (Command BB M5-4 ≠ (1,0))

5.14. 2 X IO Read Performer Enhance Mode

"BBh" command supports 2 X IO Performance Enhance Mode which can further reduce command overhead through setting the "Continuous Read Mode" bits (M7-0) after the input 3-byte address (A23-A0). If the "Continuous Read Mode" bits (M5-4) = (1, 0), then the next 2 X IO Read command (after CS# is raised and then lowered) does not require the BBH command code.

If the "Continuous Read Mode" bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. A "Continuous Read Mode" Reset command can be used to reset (M5-4) before issuing normal command.

Note: 2 X IO Read Performance Enhance Mode, if M5-4 = 1, 0. If not using performance enhance recommend to set M5-4 ≠ 1,0.

5.15. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial NOR Flash in read mode.A Quad Enable (QE) bit of status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data isshifted out, so the whole memory can be read outat a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction isrejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 5-15 Quad Read Mode Sequence (Command 6B)

5.16. 4 X IO Read Mode(4READ)

The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data isshifted out, so the whole memory can be read outat a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0 - to end 4READ operation can use CS# to high at any time during data out.

Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→ sending 4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 → "Continuous Read Mode" byte M[7:0]→ 4 dummy cycles →data out still CS# goes high →CS# goes low(reduce 4Readinstruction)

→24-bit random access address.

In the performance-enhancing mode, the "Continuous Read Mode" bits M[5:4] = (1,0) can make this mode continue and reduce the next 4READ instruction. Once M[5:4 ] ≠ (1,0) and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. A "Continuous Read Mode" Reset command can be used to reset (M5-4) before issuing normal command

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 5-16 4 X IO Read Mode Sequence (Command EB M5-4 ≠ (1,0))

Note:

• 1. Hi-impedance is inhibited for the two clock cycles.
• 1. M[5-4] = (1,0) is inhibited.

5.17. 4 X IO Read PerformanceEnhance

"EBh" command supports 4 X IO Performance Enhance Mode which can further reduce command overhead through setting the "Continuous Read Mode" bits (M7-0) after the input 3-byte address (A23-A0). If the "Continuous Read Mode" bits (M5-4) = (1, 0), then the next 4 X IO Read command (after CS# is raised and then lowered) does not require the EBH command code.

If the "Continuous Read Mode" bits (M5-4) do not equal (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A "Continuous Read Mode" Reset command can be used to reset (M5-4) before issuing normal command.

Note: 1. 4 X IO Read Performance Enhance Mode, if M5-4 = 1, 0. If not using performance enhance

5.18. Burst Read

The Set Burst with Wrap command is used in conjunction with "4 X IO Read" command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode.

The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command → Send 24 dummy bits→ Send 8 bits "Wrap bits" → CS# goes high.

5.19. Page Erase (PE)

The Page Erase (PE) instruction isfor erasing the data of the chosen Page to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Erase (PE).

Toperform a Page Erase with the standard page size (256 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of 2 page address bytes that specify the page in the main memory to be erased, and 1 dummy byte.

The sequence of issuing PE instruction is: CS# goes low → sending PE instruction code→ 3-byte address on SI → CS# goes high

Figure 5-19 Page Erase Sequence (Command 81)

5.20. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI → CS# goes high.

The SIO[3:1] are don't care.

Figure 5-20 Sector Erase (SE) Sequence (Command 20)

5.21. Block Erase (BE32K)

The Block Erase (BE32K) instruction isfor erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte address on SI → CS# goes high.

The SIO[3:1] are don't care.

The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle isin progress. The WIP sets during the tBE32K timing, and clears when Block Erase Cycle iscompleted, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP4, BP3, BP2, BP1,BP0 bits, the array data willbe protected (no change) and the WELbitstill be reset.

5.22. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→CS# goes high.

The SIO[3:1] are "don't care".

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bitstill can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP4, BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block.

Figure 5-22 Block Erase (BE) Sequence (Command D8)

5.23. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high.

The SIO[3:1] are "don't care".

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If

the chip is protected by BP4,BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when all Block Protect(BP4, BP3, BP2, BP1, BP0) are set to "None protected".

5.24. Page Program (PP)

The Page Program (PP) instruction isfor programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0.If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all0). Ifmore than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at

the requested address of the page without effect on other address of the samepage.The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high.

The CS# must be kept low duringthe whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bitstill can be checked during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP4, BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

The SIO[3:1] are "don't care".

5.25. Dual Input Page Program(DPP)

The Dual Input Page Program (DPP) instruction is similarto the standard Page Program command and can be used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations. The Dual-Input Page Program command allows two bits of data to be clocked into the device on every clock cycle rather than justone.

A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Dual Input Page Program (DPP). The Dual Input Page Programming takes two pins: SIO0, SIO1 as data input, which can improve programmer performance and the effectiveness of application. The other function descriptions are as same as standard page program.

The sequence of issuing DPP instruction is: CS# goes low→ sending DPP instruction code→ 3-byte address on SI→at least 1-byte on data on SIO[1:0]→ CS# goes high.

Figure 5-25 Page Program (DPP) Sequence (Command A2)

5.26. Quad Page Program (QPP)

The Quad Page Program (QPP) instruction is for programming the memory to be "0".A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (QPP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as data input, which can improve programmer performance and the effectiveness of application. The QPP operation frequency supports as fast as fQPP. The other function descriptions are as same as standard pageprogram.

The sequence of issuing QPP instructions:CS# goes low → sending QPP instruction code→ 3-byte address on SI→at least 1-byte on data on SIO[1:0]→ CS# goes high.

Figure 5-26 Page Program (QPP) Sequence (Command 32)

5.27. Erase Security Registers (ERSCUR)

The product provides three512-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array.

The Erase Security Registers command is similarto Sector/Block Erase command, the instruction isused for 512-byte erase operation. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)bit.

The Erase Security Registers command sequence: CS# goes low → sending ERSCUR instruction → sending 24 bit address → CS# goes high.

CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration istSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is0 when itis completed. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will

Figure 5-27 Erase Security Registers (ERSCUR) Sequence (Command 44)

5.28. Program Security Registers (PRSCUR)

The Program Security Registers command is similarto the Page Program command. It allows from 1 to 512bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command.

The Program Security Registers command sequence: CS# goes low → sending PRSCUR instruction → sending 24 bit address → sending at least one byte data → CS# goes high.

As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration istPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when itis completed.

If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored.

Figure 5-28 Program Security Registers (PRSCUR) Sequence (Command 42)

5.29. Read Security Registers (RDSCUR)

The Read Security Registers command issimilarto Fast Read command. The command isfollowed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A8-A0 address reaches the last byte of the register (Byte 1FFH), it will reset to 000H, the command iscompleted by driving CS# high.

The sequence of issuing RDSCUR instruction is : CS# goes low → sending RDSCUR instruction → sending 24

bit address → 8 bit dummy byte → Security Register data out on SO → CS# goes high.

5.30. Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep

Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode.

The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.

Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out).

When Power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# musOnce the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out).

t go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);otherwise, the instruction will not be executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.

Figure 5-30 Deep Power-down (DP) Sequence (Command B9)

5.31. Release form Deep Power-Down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven high, the device isput in the Stand-by Powermode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Powermode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max). Once in the

Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

RES instruction isfor reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction.Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device isin progress ofprogram/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress.

The RES instruction isended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# isat low. If the device was not previously in Deep Power-down mode, the device transition to standby mode isimmediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2 (max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.

The RDP instruction is for releasing from Deep Power-Down Mode.

Figure 5-31 Read Electronic Signature (RES) Sequence (Command AB)

Figure 5-32 Release from Deep Power-down (RDP) Sequence (Command AB)

5.32. Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values are listed in "Table ID Definitions".

The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Zetta and the device ID are shifted out on the falling edge of SCLK withthe most significant bit (MSB) first. If the least significant bit (LSB) of the address byte is0b, the manufacturer ID will be output first,followed by the device ID. If the least significant bit (LSB) ofthe address byte is 1b, then the device ID will be output first,followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 5-32 Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)

5.33. Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS)

The DREMS instruction issimilarto the REMS command and returns the JEDEC assigned manufacturer ID which takes two pins:SIO0,SIO1 as address input and ID output I/O

The instruction is initiated by driving the CS# pin low and shift the instruction code "92h" followed by two dummy bytes and one bytes address (A7~A0)., 8-bit "Continuous Read Mode" bits (M7-0).After which, the Manufacturer ID for Zetta and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the least significant bit (LSB) of the one-byte address is initially set to 1b, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 5-33 DUAL I/O Read Electronic Manufacturer & Device ID (DREMS) Sequence (Command 92)

5.34. Quad I/O Read Electronic Manufacturer ID & Device ID (QREMS)

The QREMS instruction is similarto the REMS command and returns the JEDEC assigned manufacturer ID which takes four pins: SIO0, SIO1,SIO2,SIO3 as address input and ID output I/O

The instruction isinitiated by driving the CS# pin low and shift the instruction code "94h" followed by two dummy bytes and one bytes address (A7~A0).8-bit "Continuous Read Mode" bits (M7-0)and then two dummy bytes. After which, the Manufacturer ID for Zetta and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the least significant bit (LSB) ofthe one-byte address is initially set to 1b, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 5-34 QUAD I/O Read Electronic Manufacturer & Device ID (QREMS) Sequence (Command 94)

5.35. Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Zetta Manufacturer ID and Device ID are list as "as "Table . ID Definitions".

The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code →24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out.

While Program/Erase operation isin progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

Figure 5-35 Read Identification(RDID) Sequence (Command 9F)

Table ID Definitions

5.36. Program/Erase Suspend/Resume

The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to the memory array. After the program or erase operation has entered the suspended state, the memory array can be read except for the page being programmed or the sector orblock being erased.

Readable Area of Memory While a Program or Erase Operation is Suspended

When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL before the Write Enable Latch (WEL) bit clears to "0" and the SUS2 or SUS1 sets to "1", after which the device isready to accept one of the commands listed in "Table Acceptable Commands During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to " AC Characteristics" for tPSL and tESL timings. "Table Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the Suspend instruction.

Status Register bit 15 (SUS2) and bit 10 (SUS1) can be read to check the suspend status. The SUS2 (Program Suspend Bit) sets to "1" when a program operation is suspended. The SUS1 (Erase Suspend Bit) sets to "1" when an erase operation is suspended. The SUS2 or SUS1 clears to "0" when the program or erase operation is resumed.

Acceptable Commands During Program/Erase Suspend after tPSL/tESL

Acceptable Commands During Suspend(tPSL/tESL not required)

Figure 5-36 Resume to Suspend Latency

5.37. Erase Suspend toProgram

The "Erase Suspend to Program" feature allows Page Programming while an erase operation is suspended. Page Programming is permitted in any unprotected memory except within the sector ofa suspended Sector Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be issued before any Page Program instruction.

A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to finish before the suspended erase can be resumed. The Status Register can be polled to determine the status of the Page Program operation. The WEL and WIP bits of the Status Register will remain "1" while the Page Program operation is in progress and will both clear to "0" when the Page Program operation completes.

Figure 5-37 Suspend to Read/Program Latency

Notes:

• 1. Please note that Program only available after the Erase-Suspend operation
• 1. To check suspend ready information, please read status register bit15 (SUS2) and bit10(SUS1)

5.38. Program Resume and EraseResume

The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program operation in progress.

Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to "1"and the SUS2 or SUS1 is cleared to "0". The program or erase operation will continue until finished ("Resume to Read Latency") or untilanother Suspend instruction is received.A resume-to-suspend latency of tPRS or tERS must be observed before issuing another Suspend instruction ("Resume to Suspend Latency").

Figure 5-38 Resume to Read Latency

5.39. No Operation (NOP)

The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command.

The SIO[3:1] are don't care.

5.40. Software Reset (RSTEN/RST)

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST) command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on.

To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the

Reset-Enable will be invalid. The SIO[3:1] are "don't care".

If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged orlost.

Figure 5-40a Software Reset Recovery

Figure 5-40b Reset

5.41. Read Unique ID (RUID)

The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each ZD25Qxx device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.

The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command →Dummy Byte1 →Dummy Byte2 →Dummy Byte3 → Dummy Byte4 → 128bit Unique ID Out → CS# goes high.

The command sequence is show below.

Figure 5-41 Read Unique ID (RUID) Sequence (Command 4B)

5.42. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similarto the one found in the Introduction of JEDEC Standard, JESD68 on CFI.

The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→ send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→ send 1 dummy byte on SI pin→ read SFDP code on SO→ to end RDSFDP operation can use CS# to high at any time during data out. The lower byte (A7~A0) of the address is the valid address which is corresponded to the Add in the Figure 5-42.

SFDP is a JEDEC Standard, JESD216B.

Figure 5-42 SerialFlash Discoverable Parameter (SFDP) Table

Table Signature and Parameter Identification Data Values

Table Parameter Table (0): JEDEC Flash Parameter Tables

Table Parameter Table (1): Zetta Flash Parameter Tables

6. Ordering Information

• Product serial
• 25WD: 1.653.6V Dual SPI NOR
  25WQ: 1.653.6V Quad SPI NOR
• Memory density
• 20: 2Mbit
• 40: 4Mbit
• 80: 8Mbit
• 16: 16Mbit
• Generation
• B: B version
• Package type
• T: 150mil SOP8
• O: 173mil TSSOP8
• U: USON8 (3*2mm)
• Temperature Range
• I: Industrial(-40°C~85°C)
• E: Extended(-25°C~85°C )
• Green Code
• G: Low-halogen, Lead (Pb)-free
• P: Lead (Pb) - free
• Packaging Type
• T: Tube
• R: Tape & Reel
• Y: Tray

7. Package Information

Dimensions

• Unit
• mm
• Inch

7.2-Lead SOP(208mil) θ 8 5 E1 E L L1 1 4 C D A3 A e Dimensions A1 b SEATING PLANE 0.10 Symbol A A1 A2 A3 b C D E E1 e L L1 θ Unit mm Min 1.75 0.05 1.70 0.55 0.38 0.203 REF 5.13 7.70 5.18 1.27 REF 0.50 1.21 0 Nom 1.9 0.1 1.80 0.60 0.43 5.23 7.90 5.28 0.65 1.31 - Max 2.05 0.15 1.90 0.65 0.48 5.33 8.10 5.38 0.80 1.41 8 Inch Min 0.069 0.002 0.067 0.022 0.015 0.008 REF 0.202 0.303 0.204 0.050 REF 0.020 0.048 0 Nom 0.075 0.004 0.071 0.024 0.017 0.206 0.311 0.208 0.026 0.052 - Max 0.081 0.006 0.075 0.026 0.019 0.210 0.319 0.212 0.031 0.056 8 A2

7.3-Lead TSSOP(173mil)

• Unit
• Min
• Nom
• Max
• Min
• Nom
• Max

7.5-Land WSON(6x5mm)

• Unit
• mm
• Inch
• TITLE

• DFN8
  (0506X0.75-1.27)

69

8. Revision History

• Rev. Date Description
• 1.0 2020-01-02 Initial
  Release
• 1.1 2020-05-10 Modify
  Package
  Information

NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Figure 4-1 Maximum Overshoot Waveform

Maxinum Negative Overshoot Waveform Maxinum Positive Overshoot Waveform

Table 4-1 Pin Capacitance [1]

Note:

Test Conditions: T^A = 25°C, F = 1MHz, Vcc = 3.0V.

Figure 4-2 Input Test Waveforms and Measurement Level

Figure 4-3 Output Loading