XC7S25-1CSGA225C

Part: 7 series FPGAs — Xilinx

Type: Field-Programmable Gate Array (FPGA)

Description: Xilinx 7 series FPGAs are built on a 28 nm, high-k metal gate (HKMG) process technology, offering up to 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP performance.

Operating Conditions:

• Supply voltage: 1.0V core, 0.9V core option, 1.2V-3.3V I/O
• Max logic cells: 1,955K (Virtex-7)
• Max DSP performance: 5,335 GMAC/s (Virtex-7)
• Max serial transceiver speed: 28.05 Gb/s (Virtex-7)

Key Specs:

• Process technology: 28 nm, HPL, HKMG
• Max Logic Cells: 1,955K
• Max Block RAM: 68 Mb
• Max DSP Slices: 3,600
• Max DSP Performance: 5,335 GMAC/s
• Max Transceiver Speed: 28.05 Gb/s
• Max DDR3 Interface Speed: 1,866 Mb/s
• Analog-to-Digital Converters: Dual 12-bit 1MSPS

Features:

• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.
• 36 Kb dual-port block RAM with built-in FIFO logic.
• High-performance SelectIO™ technology with support for DDR3 interfaces.
• High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s up to 28.05 Gb/s.
• User configurable analog interface (XADC) with on-chip thermal and supply sensors.
• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder.
• Powerful clock management tiles (CMT), combining PLL and MMCM blocks.
• Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.
• Configuration options including 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.

Package:

• Low-Cost, Wire-Bond
• Bare-Die Flip-Chip
• High-Performance Flip-Chip
• CPGA196 (8 x 8 mm)
• CSGA225 (13 x 13 mm)
• CSGA324 (15 x 15 mm)
• FTGB196 (15 x 15 mm)
• FGGA484 (23 x 23 mm)
• FGGA676 (27 x 27 mm)
• CPG236 (10 x 10 mm)
• CPG238 (10 x 10 mm)
• CSG324 (15 x 15 mm)
• CSG325 (15 x 15 mm)
• FTG256 (17 x 17 mm)
• SBG484 (19 x 19 mm)
• FBG484 (23 x 23 mm)
• FBG676 (27 x 27 mm)
• FFG1156 (35 x 35 mm)
• FBG900 (31 x 31 mm)
• FFG900 (31 x 31 mm)
• FFG901 (31 x 31 mm)
• FFG1157 (35 x 35 mm)
• FFG1761 (42.5 x 42.5 mm)
• FHG1761 (42.5 x 42.5 mm)
• FLG1925 (45 x 45 mm)

• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.
• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
• High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.
• High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.
• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.
• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.

Table 1: 7 Series Families Comparison

1. Additional memory available in the form of distributed RAM.

2. Peak DSP performance numbers are based on symmetrical filter implementation.

3. Peak MicroBlaze CPU performance numbers based on microcontroller preset.

© Copyright 2010-2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, UltraScale, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

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AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.

Single-ended outputs use a conventional CMOS push/pull output structure driving High towards V CCO or Low towards ground, and can be put into a high-Z state. The system designer can specify the slew rate and the output strength. The input is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pulldown resistor.

Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin pairs can optionally be terminated with a 100 internal resistor. All 7 series devices support differential standards beyond LVDS: RSDS, BLVDS, differential SSTL, and differential HSTL.

Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well as single-ended SSTL and differential SSTL. The SSTL I/O standard can support data rates of up to 1,866 Mb/s for DDR3 interfacing applications.