W25Q64JV-IQ/JQ

Part: Not specified in the provided text.

Type: Serial Flash Memory

Description: 64M-bit serial flash memory with 3V nominal operation, supporting Standard, Dual, and Quad SPI interfaces.

Operating Conditions:

• Supply voltage: 3V nominal
• Interface: Standard SPI, Dual SPI, Quad SPI

Absolute Maximum Ratings:

Key Specs:

• Memory Size: 64M-bit
• Interface Modes: Standard SPI, Dual SPI, Quad SPI
• Operating Voltage: 3V
• Erase/Program Suspend and Resume functionality
• Multiple Write Protection features (Block Protect, Top/Bottom Protect, Sector/Block Protect, Complement Protect, Status Register Protect)
• Security Register Lock Bits (Volatile/Non-Volatile OTP Writable)
• Output Driver Strength control (DRV1, DRV0)
• Quad Enable (QE) bit for Quad SPI operation

Features:

Applications:

Package:

• SOIC 208-mil
• WSON 6x5-mm
• WSON 8x6-mm
• XSON 4x4-mm
• SOIC 300-mil
• TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
• WLCSP

• New Family of SpiFlash Memories Advanced Security Features
• W25Q64JV: 64M-bit / 8M-byte
• Standard SPI: CLK, /CS, DI, DO
• Dual SPI: CLK, /CS, IO0, IO1
• Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
• Software & Hardware Reset (1)
• Highest Performance Serial Flash
• 133MHz Single, Dual/Quad SPI clocks
• 266/532MHz equivalent Dual/Quad SPI
• Min. 100K Program-Erase cycles per sector
• More than 20-year data retention
• Low Power, Wide Temperature Range
• Single 2.7 to 3.6V supply
• <1μA Power-down (typ.)
• -40°C to +85°C operating range
• -40°C to +105°C operating range
• Flexible Architecture with 4KB sectors
• Uniform Sector/Block Erase (4K/32K/64K-Byte)
• Program 1 to 256 byte per programmable page
• Erase/Program Suspend & Resume

Note: 1. Hardware /RESET pin is only available on TFBGA or SOIC16 packages

• Software and Hardware Write-Protect
• Special OTP protection
• Top/Bottom, Complement array protection
• Individual Block/Sector array protection
• 64-Bit Unique ID for each device
• Discoverable Parameters (SFDP) Register
• 3X256-Bytes Security Registers
• Volatile & Non-volatile Status Register Bits
• Space Efficient Packaging
• 8-pin SOIC 208-mil
• 8-pad WSON 6x5-mm/8x6-mm
• 16-pin SOIC 300-mil
• 8-pad XSON 4x4-mm
• 24-ball TFBGA 8x6-mm (6x4 ball array)
• 24-ball TFBGA 8x6-mm (6x4/5x5 ball array)
• 12-ball WLCSP
• Contact Winbond for KGD and other options

W25Q64JV-IQ/JQ Pinout

8-pin SOIC 208-mil (Package Code SS)

Notes

• IO0 and IO1 are used for Standard and Dual SPI instructions.
• IO0–IO3 are used for Quad SPI instructions; /HOLD (or /RESET) function is only available for Standard/Dual SPI.
• The W25Q64JV-IQ/JQ suffix indicates the 8-pin SOIC 208-mil package (SS). Other package variants (WSON, XSON, SOIC 300-mil, TFBGA, WLCSP) have different pin counts and configurations and are not included in this extraction.

1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V.

2. Checker Board Pattern.

• 61 - Revision J

1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).