USB3300-EZK
Hi-Speed USB PHYThe USB3300-EZK is a hi-speed usb phy from SMSC. View the full USB3300-EZK datasheet below including electrical characteristics.
Manufacturer
SMSC
Category
Hi-Speed USB PHY
Package
32 pin, QFN Lead-Free RoHS Compliant
Overview
Part: USB3300 — SMSC Type: Hi-Speed USB Host, Device or OTG PHY Description: Industrial temperature Hi-Speed USB Physical Layer Transceiver (PHY) with a low pin count ULPI interface, supporting host, device, or OTG operation, and integrated 1.8V regulators.
Operating Conditions:
- Supply voltage: 3.3 V
- Operating temperature: -40 to +85 °C
Absolute Maximum Ratings:
Key Specs:
- Unconfigured current: 54.7 mA (typical)
- Suspend current: 83 μA (typical)
- ESD protection (HBM): ±8 kV
- ESD protection (IEC61000-4-2 contact): ±8 kV
- ESD protection (IEC61000-4-2 air): ±15 kV
- ULPI interface clock: 60 MHz
- Internal regulator output voltage: 1.8 V
Features:
- USB-IF Hi-Speed certified to USB Specification Rev 2.0
- ULPI Specification revision 1.1 compliant in 8-bit mode
- Converts 54 UTMI+ signals into a standard 12 pin Link controller interface
- Integrated 1.8 volt regulators for single 3.3 volt supply operation
- Integrated 24MHz Crystal Oscillator or external 24MHz clock input
- Internal PLL for 480MHz Hi-Speed USB operation
- Full support for On-The-Go (OTG) protocol (HNP and SRP)
- Integrated pull-up resistor on STP for interface protection
- Internal short circuit protection of ID, DP and DM lines to VBUS or ground
Applications:
- Cell Phones
- PDAs
- MP3 Players
- Scanners
- External Hard Drives
- Digital Still and Video Cameras
- Portable Media Players
- Printers
Package:
- 32 pin QFN (5 x 5 x 0.90 mm height)
Features
- USB-IF Hi-Speed certified to the Universal Serial Bus Specification Rev 2.0
- Interface compliant with the ULPI Specification revision 1.1 in 8-bit mode
- Industry standard UTMI+ Low Pin Interface (ULPI) Converts 54 UTMI+ signals into a standard 12 pin Link controller interface
- 54.7mA Unconfigured Current (typical) - ideal for bus powered applications
- 83μA suspend current (typical) - ideal for battery powered applications
- Latch-Up performance exceeds 150 mA per EIA/JESD 78, Class II
- ESD protection levels of ± 8kV HBM without external protection devices
- Integrated protection to withstand IEC61000-4-2 ESD tests ( ± 8kV contact and ± 15kV air) per 3rd party test facility
- Supports FS pre-amble for FS hubs with a LS device attached (UTMI+ Level 3)
- Supports HS SOF and LS keep-alive pulse
- Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Revision 1.0a specification
- Supports the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
- Allows host to turn VBUS off to conserve battery power in OTG applications
- Supports OTG monitoring of VBUS levels with internal comparators. Includes support for an external VBUS or fault monitor.
Applications
The USB3300 is the ideal companion to any ASIC, SoC or FPGA solution designed with a ULPI Hi-Speed USB host, peripheral or OTG core.
The USB3300 is well suited for:
- Cell Phones
- PDAs
- MP3 Players
- Scanners
- External Hard Drives
- Digital Still and Video Cameras
- Portable Media Players
- Printers
Pin Configuration
| PIN | NAME | DIRECTION, TYPE | ACTIVE LEVEL | DESCRIPTION |
|---|---|---|---|---|
| 1 | GND | Ground | N/A | Ground |
| 2 | GND | Ground | N/A | Ground |
| 3 | CPEN | Output, CMOS | High | External 5 volt supply enable. This pin is used to enable the external Vbus power supply. The CPEN pin is low on POR. |
Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package
Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued)
| PIN | NAME | DIRECTION, TYPE | ACTIVE LEVEL | DESCRIPTION |
|---|---|---|---|---|
| 4 | VBUS | I/O, Analog | N/A | VBUS pin of the USB cable. The USB3300 uses this pin for the Vbus comparator inputs and for Vbus pulsing during session request protocol. |
| 5 | ID | Input, Analog | N/A | ID pin of the USB cable. For non-OTG applications this pin can be floated. For an A-Device ID = 0. For a B-Device ID = 1. |
| 6 | VDD3.3 | Power | N/A | 3.3V Supply. A 0.1μF bypass capacitor should be connected between this pin and the ground plane on the PCB. |
| 7 | DP | I/O, Analog | N/A | D+ pin of the USB cable. |
| 8 | DM | I/O, Analog | N/A | D- pin of the USB cable. |
| 9 | RESET | Input, CMOS | High | Optional active high transceiver reset. This is the same as a write to the ULPI Reset , address 04h, bit 5. This does not reset the ULPI register set. This pin includes an integrated pull-down resistor to ground. If not used, this pin can be floated or connected to ground (recommended). See Section 6.1.11, "Reset Pin" for details. |
| 10 | EXTVBUS | Input, CMOS | High | External Vbus Detect. Connect to fault output of an external USB power switch or an external Vbus Valid comparator. See Section 6.5.4, "External Vbus Indicator," on page 44 for details. This pin has a pull down resistor to prevent it from floating when the ULPI bit UseExternalVbusIndicator is set to 0. |
| 11 | NXT | Output, CMOS | High | The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. |
| 12 | DIR | Output, CMOS | N/A | Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The PHY will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL start- up. |
| 13 | STP | Input, CMOS | High | The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. The STP pin also includes the interface protection detailed in Section 6.1.9.3, "Interface Protection," on page 36 . |
| 14 | CLKOUT | Output, CMOS | N/A | 60MHz reference clock output. All ULPI signals are driven synchronous to the rising edge of this clock. |
| 15 | VDD1.8 | Power | N/A | 1.8V for digital circuitry on chip. Supplied by On-Chip Regulator when REG_EN is active. Place a 0.1μF capacitor near this pin and connect the capacitor from this pin to ground. Connect pin 15 to pin 26. |
Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued)
Electrical Characteristics
Table 5.1 Electrical Characteristics: Supply Pins
| PARAMETER | SYMBOL | CONDITIONS | TYP | MAX | UNITS |
|---|---|---|---|---|---|
| Unconfigured Current | I AVG(UCFG) | Device Unconfigured | Same as Idle | Same as Idle | mA |
| FS Idle 3.3V Current | I AVG(FS33) | FS idle not data transfer | 18.8 | 21.9 | mA |
| FS Idle 1.8V Current | I AVG(FS18) | FS idle not data transfer | 36.4 | 43.2 | mA |
| FS Transmit 3.3V Current | I AVG(FSTX33) | FS current during data transmit | 36.0 | 41.6 | mA |
| FS Transmit 1.8V Current | I AVG(FSTX18) | FS current during data transmit | 36.8 | 43.2 | mA |
| FS Receive 3.3V Current | I AVG(FSRX33) | FS current during data receive | 22.5 | 27.0 | mA |
| FS Receive 1.8V Current | I AVG(FSRX18) | FS current during data receive | 36.7 | 43.4 | mA |
| HS Idle 3.3V Current | I AVG(HS33) | HS idle not data transfer | 22.1 | 25.4 | mA |
| HS Idle 1.8V Current | I AVG(HS18) | HS idle not data transfer | 38.7 | 45.6 | mA |
| HS Transmit 3.3V Current | I AVG(HSTX33) | HS current during data transmit | 25.4 | 29.0 | mA |
| HS Transmit 1.8V Current | I AVG(HSTX18) | HS current during data transmit | 39.1 | 46.2 | mA |
| HS Receive 3.3V Current | I AVG(HSRX33) | HS current during data receive | 23.0 | 26.6 | mA |
| HS Receive 1.8V Current | I AVG(HSRX18) | HS current during data receive | 39.6 | 46.8 | mA |
| Low Power Mode 3.3V Current | I DD(LPM33) | VBUS 15k Ω pull-down and 1.5k Ω pull-up resistor currents not included. | 59.4 | μA | |
| Low Power Mode 1.8V Current | I DD(LPM18) | VBUS 15k Ω pull-down and 1.5k Ω pull-up resistor currents not included. | 25.5 | μA |
Typical Application
Figure 7.1 USB3300 Application Diagram (Peripheral)
Figure 7.1 USB3300 Application Diagram (Peripheral)
Figure 7.2 USB3300 Application Diagram (Host or OTG)
Figure 7.2 USB3300 Application Diagram (Host or OTG)
Figure 7.3 USB3300 Application Diagram (Peripheral with Over Voltage Protection)
Figure 7.3 USB3300 Application Diagram (Peripheral with Over Voltage Protection)
Package Information
The USB3300 is offered in a compact 32 pin lead-free QFN package.
Figure 8.1 USB3300-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free)
Table 8.1 32 Terminal QFN Package Parameters
| MIN | NOMINAL | MAX | REMARKS | |
|---|---|---|---|---|
| A | 0.70 | ~ | 1.00 | Overall Package Height |
| A1 | 0 | 0.02 | 0.05 | Standoff |
| A2 | ~ | ~ | 0.90 | Mold Thickness |
| A3 | 0.20 REF | 0.20 REF | 0.20 REF | Copper Lead-frame Substrate |
| D | 4.85 | 5.0 | 5.15 | X Overall Size |
| D1 | 4.55 | ~ | 4.95 | X Mold Cap Size |
| D2 | 3.15 | 3.3 | 3.45 | X exposed Pad Size |
| E | 4.85 | 5.0 | 5.15 | Y Overall Size |
| E1 | 4.55 | ~ | 4.95 | Y Mold Cap Size |
| E2 | 3.15 | 3.3 | 3.45 | Y exposed Pad Size |
| L | 0.30 | ~ | 0.50 | Terminal Length |
| e | 0.50 BSC | 0.50 BSC | 0.50 BSC | Terminal Pitch |
| b | 0.18 | 0.25 | 0.30 | Terminal Width |
| ccc | ~ | ~ | 0.08 | Coplanarity |
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| USB3300 | SMSC | — |
| USB3300-EZK-TR | SMSC | QFN- |
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