UCC28781
ZVS Flyback Controller with SR DriveThe UCC28781 is a zvs flyback controller with sr drive from Texas Instruments. View the full UCC28781 datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
Official UCC28781 datasheet (PDF) — the source this page was extracted from.
UCC28781 Key Specifications
| Parameter | Value |
|---|---|
| Standby Power | < 45 mW |
| Peak Efficiency | > 93 % |
| Package Dimensions | 4.00 mm x 4.00 mm, 24-pin WQFN, 0.5 mm pitch, 0.8 mm max height |
| Switching Frequency | > 500 kHz |
| FB Pin Output Voltage | 4.25 V |
| FLT Pin Current Source | 50 µA |
| Reference Output (REF) | 5 V |
| Fault Pin Thresholds (FLT) | above 4.5 V or below 0.5 V |
UCC28781 Overview
Part: UCC28781 — Texas Instruments
Type: Zero-Voltage-Switching (ZVS) Flyback Controller with Synchronous Rectifier Gate-Drive
Description: ZVS flyback controller with switching frequency above 500 kHz, direct synchronous rectifier control, adaptive dead-time control, and programmable adaptive burst mode, enabling peak efficiency above 93% and standby power below 45 mW.
Operating Conditions:
- Supply voltage (VDD bias): 14–34 V
- Operating junction temperature: -40 to 140 °C
- Switching frequency: > 500 kHz
- Recommended capacitors: CVDD ≥ 10 μF, CP13 ≥ 1 μF, CREF ≥ 0.22 μF
Absolute Maximum Ratings:
- VDD: 38 V
- SWS: -6 to 38 V
- VDD-SWS: -20 to 38 V
- XCD: -0.3 to 30 V
- P13, S13, PWML: -0.3 to 20 V
- Operating junction temperature: -40 to 150 °C
- Storage temperature: -65 to 150 °C
Key Specs:
- Bias supply operating range: 14–34 V
- Operating junction temperature: -40 to 140 °C
- P13 regulated bias: 13 V
- REF output: 5 V
- PWML gate-drive capability: -0.5 A / +1.9 A
- XCD maximum discharge current: 2 mA
- FLT pin current source: 50 μA
- S13 power-good threshold: 10 V
Features:
- Switching frequency above 500 kHz
- Peak efficiency above 93%
- Standby power below 45 mW
- Adaptive control for ZVS and dead-time optimization
- EMI frequency dithering without trade-offs on transient response or audible noise
- Programmable adaptive burst mode (ABM) with internal compensation
- X-capacitor discharge capability
- Over-temperature, overvoltage, output short-circuit, overcurrent, over-power, and pin-fault protections
- Auto-recovery fault responses
- Configurable for GaN or Si primary-side FETs (SET pin)
Applications:
- Soundbar
- Smart speaker
- Merchant network and server PSU
- Appliances battery charger
- Merchant battery charger
- Industrial AC-DC
Package:
- WQFN (RTW), 24-pin, 4.00 mm × 4.00 mm
UCC28781 Features
- Switching frequency: > 500 kHz
- Enables peak efficiency > 93 %
- Enables < 45 mW stand-by power
- Adaptive control for zero-voltage-switching (ZVS) and dead-time optimization
- EMI frequency-dithering without trade-offs on transient response or audible noise
- Programmable adaptive burst mode (ABM) with internal compensation
- X-capacitor discharge capability
- Over-temperature, overvoltage, output shortcircuit, overcurrent, over-power, and pin-fault protections
- Auto-recovery fault-responses
- 4 mm × 4 mm, 24-pin, QFN package
UCC28781 Applications
UCC28781 Pin Configuration
Figure 5-1. RTW Package, 24-Pin WQFN (Top View)
Table 5-1. Pin Functions
| PIN - NAME | PIN - NO. | TYPE | DESCRIPTION |
|---|---|---|---|
| FLT | 1 | I | The controller enters into the fault state if the FLT-pin voltage is pulled above 4.5 V or below 0.5 V. A 50-μA current source interfaces directly with an external NTC (negative temperature coefficient) thermistor to AGND pin for remote temperature sensing. The current source is active during the run state and inactive during the wait state. A 50-μs fault delay allows a filter capacitor to be placed on the FLT pin without false triggering the 0.5-V OTP fault when the controller enters into a run state from a wait state. Alternatively, a high-resistance voltage divider can be used to sense the bulk input capacitor voltage for line-OVP detection, and a 750-μs fault delay helps to prevent false triggering the 4.5-V input line-OVP from a short-duration bulk capacitor voltage overshoot during line surge and ESD strike events. When FLT-pin voltage is used for line-OVP detection, the external OTP can be implemented on CS pin. |
| RTZ | 2 | I | A resistor between this pin and AGND pin programs an adaptive delay for transition to zero voltage from the turn-off edge of the PWMH signal to the turn-on edge of the PWML signal. Parasitic capacitance between this pin and any other net, including AGND, must be minimized to avoid noise coupling and its effect on the dead-time calculation. |
| RDM | 3 | I | A resistor between this pin and AGND pin programs a synthesized demagnetization time used to control the on-time of the PWMH signal to achieve zero voltage switching on the primary switch. The controller applies a voltage on this pin that varies with the output voltage derived from the VS pin signal. Parasitic capacitance between this pin and any other net, including AGND, must be minimized to avoid noise coupling and its effect on the internal PWMH on-time calculation. |
| IPC | 4 | I | This pin is an intelligent power control (IPC) pin to optimize the converter efficiency. A 50-μA current source directly interfaces with a resistor (R IPC ) to AGND pin to program an increase in the peak current level at very light load; the burst frequency can be further reduced, helping to achieve low standby power and tiny-load power. If the IPC pin is connected to AGND without R IPC , the peak current level in very light load is set to a minimum level for the output ripple or audible noise sensitive designs. R IPC can also be connected between this pin and the CS pin or IPC pin can be directly connected to CS pin, so the 50-μA IPC current can create an output voltage dependent offset voltage on the CS pin for reducing output ripple in adaptive burst mode and improving light-load efficiency at lower output voltage level of a wide output voltage range design. |
| BUR | 5 | I | This pin is used to program the burst threshold of the converter at light load. A resistor divider between REF and AGND is used to set a voltage at BUR to determine the peak current level when the converter enters adaptive burst mode (ABM). In addition, the Thevenin resistance on BUR is used to activate offset voltages for smooth mode transitions. A 2.7-μA pull up current increases the peak current threshold when the converter enters low-power mode (LPM) from ABM. A 5-μA pull down current reduces the peak current threshold when the converter enters into high-power mode (adaptive amplitude modulation, AAM) from ABM. |
Table 5-1. Pin Functions
UCC28781 Electrical Characteristics
Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V, VSWS = 0 V, I FB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 μF, CP13 = 1 μF, and -40⁰C < TJ = TA < 125⁰C
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| VDD INPUT | VDD INPUT | VDD INPUT | VDD INPUT | VDD INPUT | VDD INPUT | VDD INPUT |
| I RUN(STOP) | Supply current, run state | No switching | 0.88 | 2.2 | 2.66 | mA |
| I RUN(SW) | Supply current, run state | Switching, I VSL = 0 μA | 2.45 | 3 | 3.55 | mA |
| I WAIT | Supply current, wait state | I FB = -85 μA, I VDD only | 465 | 540 | 658 | μA |
| I START | Supply current, start state | V VDD = V VDD(ON) - 100 mV, V VS = 0 V | 150 | 235 | 301 | μA |
| I FAULT | Supply current, fault state | fault state | 500 | 630 | μA | |
| I VDD(LIMIT) | VDD startup current limit during startup | V VDD increasing, V SWS - V VDD = 1 V, V VDD = 16.5 V | 1.2 | 2 | 2.53 | mA |
| V VDD(ON) | VDD turnon threshold | V VDD increasing | 16.2 | 17 | 17.91 | V |
| V VDD(OFF) | VDD turnoff threshold | V VDD decreasing | 9.94 | 10.6 | 11.17 | V |
| V VDD(PCT) | Offset to power cycle for long output voltage overshoot | Offset above V VDD(OFF) , I FB = -85 μA | 1.54 | 2.2 | 2.98 | V |
| P13 OUTPUT | P13 OUTPUT | P13 OUTPUT | P13 OUTPUT | P13 OUTPUT | P13 OUTPUT | P13 OUTPUT |
| V P13 | P13 voltage level including load regulation | 0 mA to 60 mA out of P13, run state, V VDD = 20 V | 12.0 | 12.8 | 13.6 | V |
| I P13(START) | Max sink current of P13 pin during startup | V P13 = 14 V | 1.53 | 2.2 | 3.04 | mA |
| I P13(MAX) | Current sourcing limit of P13 pin | P13 shorted to AGND, V VDD = 20 V | 103.3 | 133 | 160 | mA |
| VR13 (LINE) | Line regulation of V P13 | V VDD = 15 V to 35 V | -6 | 2 | 8.7 | mV |
| V P13(OV) | Over voltage fault threshold above V P13 | 1.35 | 2 | 2.54 | V |
Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V, VSWS = 0 V, I FB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 μF, CP13 = 1 μF, and -40⁰C < TJ = TA < 125⁰C
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| R P13 | Dropout resistance of P13 regulator switch between VDD and P13 pins | (V VDD - V P13 ) / 30 mA, V VDD = 11 V, 30 mA out of P13 | 8.5 | 13 | 22.7 | Ω |
| S13 OUTPUT | S13 OUTPUT | S13 OUTPUT | S13 OUTPUT | S13 OUTPUT | S13 OUTPUT | S13 OUTPUT |
| R S13 | R DS(on) of internal disconnect switch between P13 and S13 pins | (V P13 - V S13 ) / 30 mA, V VDD = 11 V, 30 mA out of S13 | 2.1 | 2.8 | 3.82 | Ω |
| V S13_OK | S13_OK threshold to enable switching | V RUN = 5 V | 9.63 | 10.2 | 10.7 | V |
| I S13(MAX) | Current sourcing limit of S13 pin | S13 shorted to AGND, V VDD = 20 V | 260.7 | 350 | 452.5 | mA |
| REF OUTPUT | REF OUTPUT | REF OUTPUT | REF OUTPUT | REF OUTPUT | REF OUTPUT | REF OUTPUT |
| V REF | REF voltage level | I REF = 0 A | 4.9 | 5 | 5.13 | V |
| I REF(MAX) | Current sourcing limit of REF pin | REF shorted to AGND, V VDD = 20 V | 14.3 | 17 | 20.3 | mA |
| VR5 (LINE) | Line regulation of V REF | V VDD = 12 V to 35 V | -7 | -3 | 1 | mV |
| VR5 (LOAD) | Load regulation of V REF | 0 mA to 1 mA out of REF, Change in V REF | -16 | 0.1 | 25 | mV |
| VS INPUT | VS INPUT | VS INPUT | VS INPUT | VS INPUT | VS INPUT | VS INPUT |
| V VSNC | Negative clamp level | I VSL = -1.25 mA, voltage below ground | 221 | 287 | 344 | mV |
| V ZCD | Zero-crossing detection (ZCD) level | V VS decreasing | 12.4 | 35 | 67.2 | mV |
| I VSB | Input bias current | V VS = 4 V | -0.23 | 0 | 0.31 | μA |
| V VS(SM1) | VS threshold voltage in SM1 startup mode | 242.4 | 282 | 318.3 | mV | |
| V VS(SM2) | VS threshold voltage in SM2 startup mode | 458.3 | 500 | 543 | mV | |
| V VSLV(UP) | VS upper threshold out of low output voltage mode (LV mode) | V VS increasing | 2.41 | 2.49 | 2.6 | V |
| V VSLV(LR) | VS lower threshold into low output voltage mode (LV mode) | V VS decreasing | 2.3 | 2.39 | 2.49 | V |
| t ZC | Zero-crossing timeout delay | 1.95 | 2.3 | 2.73 | μs | |
| t D(ZCD) | Propagation delay from ZCD high to PWML 10% high | V VS step from 4 V to -0.1 V | 23 | 50 | 81 | ns |
| CS INPUT | CS INPUT | CS INPUT | CS INPUT | CS INPUT | CS INPUT | CS INPUT |
| V CST(MAX) | Peak-power threshold on CS pin out of LV mode | I VSL = 0 μA, V VS ≥ V VSLV(UP) | 767.4 | 801 | 836.4 | mV |
| V CST(MAX) | Peak-power threshold on CS pin out of LV mode | I VSL = -333 μA, V VS ≥ V VSLV(UP) | 650 | 727 | 788.7 | mV |
| V CST(MAX) | Peak-power threshold on CS pin out of LV mode | I VSL = -666 μA, V VS ≥ V VSLV(UP) | 570 | 600 | 651.8 | mV |
| V CST(MAX) | Peak-power threshold on CS pin out of LV mode | I VSL = -1.25 mA, V VS ≥ V VSLV(UP) | 537.2 | 570 | 612 | mV |
| V CST(MAX)_LV | Peak-power threshold on | I VSL = 0 mA, V VS ≤ V VSLV(LR) | 593.7 | 628 | 663.9 | mV |
| V CST(MAX)_LV | CS pin in LV mode | I VSL = -666 μA, V VS ≤ V VSLV(LR) | 540 | 570 | 609.5 | mV |
| V CST(MAX)_LV | Peak-power threshold on | I VSL = -1.25 mA, V VS ≤ V VSLV(LR) | 511.2 | 540 | 584.7 | mV |
| V CST(MIN) | Minimum CS threshold voltage | V CS increasing, I FB = -85 μA | 120.7 | 153 | 200.1 | mV |
| K LC | Line-compensation current ratio | I VSL = -1.25 mA, I VSL / current out of CS pin | 21.6 | 25 | 29 | A/A |
| V CST(EMI) (1) (2) | EMI dithering magnitude on CS pin out of LV mode | (V BUR / K BUR-CST ) < V CST < V CST(MAX) , I VSL > -646 μA, V VS ≥ V VSLV(UP) | 78.4 | 96 | 113.6 | mV |
Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V, VSWS = 0 V, I FB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 μF, CP13 = 1 μF, and -40⁰C < TJ = TA < 125⁰C
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| V CST(EMI)_LV (1) (2) | EMI dithering magnitude on CS pin in LV mode | (V BUR / K BUR-CST ) < V CST < V CST(MAX) , I VSL > -646 μA, V VS ≤ V VSLV(LR) | 29.3 | 36 | 42.7 | mV |
| V CST(SM1) | CS threshold voltage in SM1 startup mode | V VS < V VS(SM1) | 177.5 | 200 | 222.9 | mV |
| V CST(SM2) | CS threshold voltage in SM2 startup mode | V VS < V VS(SM2) | 470.4 | 500 | 531.4 | mV |
| t CSLEB | Leading-edge-blanking time | V SET = 5 V, V CS = 1 V | 171.2 | 190 | 216.1 | ns |
| Propagation delay of CS | V SET = 0 V, V CS = 1 V | 94.4 | 108 | 125 | ns | |
| t D(CS) | comparator high to PWML 90 %low | V CS step from 0 V to 1 V | 10 | 26 | 37 | ns |
| f DITHER (1) (2) | EMI dithering frequency on CS pin | (V BUR / K BUR-CST ) < V CST < V CST(OPP) , I VSL > -646 μA | 20 | 23 | 27 | kHz |
| BUR INPUT and Low-power MODE | BUR INPUT and Low-power MODE | BUR INPUT and Low-power MODE | BUR INPUT and Low-power MODE | BUR INPUT and Low-power MODE | BUR INPUT and Low-power MODE | BUR INPUT and Low-power MODE |
| K BUR-CST | Ratio of V BUR to V CST | V BUR between 0.7 V and 2.4 V | 3.82 | 3.98 | 4.09 | V/V |
| I BUR(LPM) | Bias source current of V BUR offset in LPM | 2.09 | 2.65 | 3.16 | μA | |
| I BUR(AAM) | Bias sink current of V BUR offset in AAM | V CST > V BUR / K BUR-CST | 3.76 | 4.85 | 5.81 | μA |
| f BUR(UP1) | First upper threshold of burst frequency in ABM | 30.7 | 34.4 | 38.5 | kHz | |
| f BUR(UP2) | Second upper threshold of burst frequency in ABM | V VS = 2.2 V | 41.8 | 51.2 | 58.9 | kHz |
| f BUR(LR) | Lower threshold of burst frequency in ABM | 21.3 | 24.5 | 28.1 | kHz | |
| f LPM | Burst frequency in low- power mode | 23.3 | 25 | 26.9 | kHz | |
| IPC INPUT and SBP2 MODE | IPC INPUT and SBP2 MODE | IPC INPUT and SBP2 MODE | IPC INPUT and SBP2 MODE | IPC INPUT and SBP2 MODE | IPC INPUT and SBP2 MODE | IPC INPUT and SBP2 MODE |
| V CST_IPC(UP) | Highest programmable V CST range of SBP2 by IPC pin | V IPC = 5 V | 373.8 | 405 | 438.5 | mV |
| K IPC | Ratio of the programmable IPC voltage to V CST | V IPC between 1.8 V and 3.8 V | 59.3 | 64 | 68.4 | mV/V |
| V CST_IPC(LR) | Lowest programmable V CST range of SBP2 by IPC pin | V IPC = 1 V | 247.5 | 273 | 307.7 | mV |
| V CST_IPC(MIN) | Minimum V CST of SBP2 by grounding IPC pin | V IPC = 0 V | 128.1 | 154 | 191.5 | mV |
| I IPC(SBP2) | Bias source current of V IPC offset in SBP2 | I FB = -85 μA | 40.7 | 49 | 55.7 | μA |
| f SBP2(UP) | Upper threshold of burst frequency in SBP2 | 6 | 8.5 | 13.4 | kHz | |
| f SBP2(LR) | Lower threshold of burst frequency in SBP2 | V IPC = 2 V | 1 | 1.7 | 2 | kHz |
| RUN | RUN | RUN | RUN | RUN | RUN | RUN |
| V RUNH | RUN pin high-level | I RUN = -0.2 mA | 4.6 | 4.78 | 5 | V |
| V RUNL | RUN pin low-level | I RUN = 1 mA | 0.1 | 0.25 | 0.3 | V |
| RUN peak source current | V RUN = 2.3 V | 33 | 44 | 52 | mA | |
| I SRC(RUN) | V RUN = 3 V | 14 | 20 | 25 | mA | |
| t R(RUN) | Turn-on rise time of RUN pin, from 0 V to 2.5 V | C LOAD = 22 nF, V RUN from 0 V to 2.5 V | 0.2 | 0.79 | 1 | μs |
Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V, VSWS = 0 V, I FB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 μF, CP13 = 1 μF, and -40⁰C < TJ = TA < 125⁰C
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| t F(RUN) | Turn-off fall time of RUN pin, 90 %to 10% | C LOAD = 10 pF | 20 | 32 | ns | |
| PWML | ||||||
| V PWMLH | PWML pin high-level | I PWML = -1 mA | 12.1 | 12.85 | 13.6 | V |
| V PWMLL | PWML pin low-level | I PWML = 1 mA | 0.002 | 0.1 | V | |
| I SRC(PWML) (1) | PWML peak source current | V PWML = 0 V | 0.25 | 0.5 | 0.8 | A |
| I SNK(PWML) (1) | PWML peak sink current | V PWML = 13 V | 1.2 | 1.9 | 2.8 | A |
| R SRC(PWML) | PWML pull-up resistance | I PWML = -20 mA | 3.1 | 4.3 | 6.1 | Ω |
| R SNK(PWML) | PWML pull-down resistance | I PWML = 20 mA | 0.5 | 1.1 | 1.9 | Ω |
| t R(PWML) | Turn-on rise time of PWML pin, 10 %to 90% | C LOAD = 1.5 nF | 30 | 53 | ns | |
| t F(PWML) | Turn-off fall time of PWML pin, 90 %to 10% | C LOAD = 1.5 nF | 9 | 20 | ns | |
| t D(RUN-PWML) | Delay from RUN high to PWML high | V S13 > 11 V | 1.92 | 4.7 | 7.43 | μs |
| t ON(MIN) | Minimum on-time of PWML in LPM | V SET = 5 V, I FB = -85 μA, V CS = 1 V | 68 | 105 | 180 | ns |
| PWMH | ||||||
| V PWMHH | PWMH pin high-level | I PWMH = -1 mA | 4.39 | 4.66 | 4.83 | V |
| V PWMHL | PWMH pin low-level | I PWMH = 1 mA | 0.1 | 0.198 | 0.21 | V |
| V PWMH = 2.5 V | 16.5 | 21 | 26.2 | mA | ||
| I SRC(PWMH) | PWMH peak source current | V PWMH = 3.5 V | 3.8 | 6 | 7.6 | mA |
| t R(PWMH) | Turn-on rise time of PWMH pin, 10 %to 90% | C LOAD = 10 pF | 8 | 24 | ns | |
| t F(PWMH) | Turn-off fall time of PWMH pin, 90 %to 10% | C LOAD = 10 pF | 22 | 29 | ns | |
| t D(VS-PWMH) | Dead time between VS high and PWMH 10 %high | 10 | 18 | 28 | ns | |
| PROTECTION | ||||||
| V OVP | Over-voltage threshold | V VS increasing | 4.4 | 4.55 | 4.67 | V |
| V OCP | Over-current threshold | V CS increasing | 1.14 | 1.22 | 1.27 | V |
| K OPP-PPL | Ratio of over-power threshold to peak-power threshold | V CST(OPP) / V CST(MAX) , and V CST(OPP)_LV / V CST(MAX)_LV | 0.72 | 0.75 | 0.78 | V/V |
| I VSL(RUN) | VS line-sense run current | Current out of VS pin increasing | 313 | 365 | 408.6 | μA |
| I VSL(STOP) | VS line-sense stop current | Current out of VS pin decreasing | 255 | 305 | 336.4 | μA |
| K VSL | VS line sense ratio | I VSL(STOP) / I VSL(RUN) | 0.72 | 0.836 | 0.9 | A/A |
| R RDM(TH) | R RDM threshold for CS pin fault | 35 | 55 | 70 | kΩ | |
| T J(STOP) (1) | Thermal-shutdown temperature | Internal junction temperature | 125 | 162 | °C | |
| t OPP (3) | OPP fault timer | I FB = 0 A | 130 | 164 | 210 | ms |
| t BO | Brown-out detection delay time | I VSL < I VSL(STOP) | 28.8 | 55 | 85.2 | ms |
| t CSF1 | Maximum PWML on-time for detecting CS pin fault | V SET = 5 V | 1.6 | 2.05 | 2.5 | μs |
| t CSF0 | Maximum PWML on-time for detecting CS pin fault | R RDM < R RDM(TH) for V SET = 0 V | 0.85 | 1.05 | 1.27 | μs |
| t FDR (3) | Fault reset delay timer | OCP, OPP, OVP, SCP or CS pin fault | 1.2 | 1.5 | 2.4 | s |
Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V, VSWS = 0 V, I FB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 μF, CP13 = 1 μF, and -40⁰C < TJ = TA < 125⁰C
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| FLT INPUT | FLT INPUT | FLT INPUT | FLT INPUT | FLT INPUT | FLT INPUT | FLT INPUT |
| V NTCTH | NTC shut-down voltage | FLT voltage decreasing | 0.47 | 0.5 | 0.52 | V |
| R NTCTH | NTC shut-down resistance | R NTC decreasing | 8.9 | 9.91 | 11.18 | kΩ |
| R NTCR | NTC recovery resistance | R NTC increasing | 21.2 | 23 | 26.4 | kΩ |
| I FLT | Input bias current for V FLT at V IOVPTH | V FLT = 4.5 V | -0.1 | 0 | 0.1 | μA |
| V IOVPTH | Shut-down voltage of input OVP | FLT voltage increasing | 4.3 | 4.5 | 4.67 | V |
| V IOVPR | Hysteresis of input OVP | FLT voltage decreasing | 57.7 | 74 | 87 | mV |
| t FLT(NTC) | Delay time of NTC fault | 14 | 50 | 100 | μs | |
| t FLT(IOVP) | Delay time of input OVP fault | 555 | 750 | 917 | μs | |
| V FLTZ | Clamp voltage of FLT pin | I FLT = 150 μA | 5.08 | 5.5 | 5.61 | V |
| RTZ INPUT | RTZ INPUT | RTZ INPUT | RTZ INPUT | RTZ INPUT | RTZ INPUT | RTZ INPUT |
| K TZ | t Z compensation ratio | ratio of t Z at I VSL = -200 μA to t Z at I VSL = -733 μA | 1.27 | 1.41 | 1.54 | s/s |
| t Z(MAX) | Maximum programmable dead time from PWMH low to PWML high | R RTZ = 280 kΩ, I VSL = -1 mA, V SET = 5 V | 397.8 | 478 | 592.8 | ns |
| t Z(MIN) | Minimum programmable dead time from PWMH low to PWML high | R RTZ = 78.4 kΩ, I VSL = -1 mA, V SET = 0 V | 56.1 | 70 | 89.1 | ns |
| t Z | Dead time from PWMH low to PWML high | I VSL = -200 μA | 152.2 | 175 | 212.7 | ns |
| I VSL = -450 μA | 129.2 | 150 | 190 | ns | ||
| I VSL = -733 μA | 109.7 | 125 | 147.2 | ns | ||
| SWS INPUT | SWS INPUT | SWS INPUT | SWS INPUT | SWS INPUT | SWS INPUT | SWS INPUT |
| V | SWS zero voltage threshold | V SET = 5 V | 8.1 | 8.5 | 9.1 | V |
| TH(SWS) | V SET = 0 V | 3.7 | 4.04 | 4.4 | V | |
| t D(SWS-PWML) | Time between SWS low to PWML 10 %high | V SWS step from 5 V to 0 V | 11.4 | 17 | 26 | ns |
| FB INPUT | FB INPUT | FB INPUT | FB INPUT | FB INPUT | FB INPUT | FB INPUT |
| I FB(SBP) | Maximum control FB current | I FB increasing | 64.2 | 75 | 87.1 | μA |
| V FB(REG) | Regulated FB voltage level | 4.02 | 4.25 | 4.53 | V | |
| R FBI | FB input resistance | 7.4 | 8.3 | 9.6 | kΩ | |
| dI COMP /dt (1) | Slope of internal ramp compensation current | 0.192 | 0.214 | 0.236 | A/s | |
| I COMP | Magnitude of internal ramp compensation current | 4 | 6.75 | 8 | μA | |
| RDM INPUT | RDM INPUT | RDM INPUT | RDM INPUT | RDM INPUT | RDM INPUT | RDM INPUT |
| t DM(MAX) | Maximum PWMH width with maximum tuning | V SWS = 12 V | 6.0 | 6.95 | 7.53 | μs |
| t DM(MIN) | Minimum PWMH width with minimum tuning | V SWS = 0 V | 3.0 | 3.43 | 3.77 | μs |
| XCD INPUT | XCD INPUT | XCD INPUT | XCD INPUT | XCD INPUT | XCD INPUT | XCD INPUT |
| V XCD(LR) | XCD lower zero-crossing threshold | 5.9 | 6.62 | 7.2 | V | |
| V XCD(UP) | XCD upper zero-crossing threshold | 6.8 | 7.5 | 7.9 | V |
Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V, VSWS = 0 V, I FB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 μF, CP13 = 1 μF, and -40⁰C < TJ = TA < 125⁰C
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| I XCD(0) | Leakage current in XCD wait state | V XCD = 15 V | 0.3 | 1.7 | μA | |
| I XCD(1) | First-step XCD sense current | V XCD = 15 V | 0.32 | 0.4 | 0.46 | mA |
| I XCD(2) | Second-step XCD sense current | V XCD = 15 V | 0.61 | 0.775 | 0.91 | mA |
| I XCD(3) | Third-step XCD sense current | V XCD = 15 V | 0.73 | 1.15 | 1.6 | mA |
| I XCD(4) | Fourth-step XCD sense current | V XCD = 15 V | 1.2 | 1.53 | 1.81 | mA |
| I XCD(MAX) | Maximum XCD discharge current | V XCD = 15 V | 1.65 | 2 | 2.5 | mA |
| V XCD(OVP) | Clamp voltage of XCD OVP | I XCD = 20 mA | 23 | 26 | 30 | V |
| t XCD(STEP) | Dwell time for each XCD sense step | 9 | 12 | 14.6 | ms | |
| t XCD(MAX) | Maximum XCD discharge time | 230.4 | 300 | 373.3 | ms | |
| t XCD(WAIT) | XCD wait time | 700 | 1071 | ms |
UCC28781 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VDD | 38 | V | ||
| SWS | -6 | 38 | V | |
| SWS (transient, negative pulse width of 20 ns max., duty cycle ≤ 1%) | -10 | 38 | V | |
| VDD-SWS | -20 | 38 | V | |
| CS | -0.3 | 3.6 | V | |
| VS | -0.75 | 7 | V | |
| VS (transient, 100 ns max.) | -1 | 7 | V | |
| PGND | -1 | 4 | V | |
| PGND (transient, 25 ns max.) | 5 | V | ||
| RTZ, BUR, SET, RDM, IPC, FLT, FB | -0.3 | 7 | V | |
| XCD | -0.3 | 30 | V | |
| REF, PWMH, RUN | -0.3 | 7 | V | |
| P13, S13, PWML | -0.3 | 20 | V | |
| REF, P13, RTZ, RDM, IPC | Self-limiting | mA | ||
| S13 (average) | 15 | mA | ||
| VS | 2 | mA | ||
| VS (transient, 100 ns max.) | 2.5 | mA | ||
| FB | 1 | mA | ||
| RUN (continuous) | 5 | mA | ||
| PWML (continuous) | 50 | mA | ||
| PWMH (continuous) | 10 | mA | ||
| CS (transient, 30 ns max.) | 1 | mA | ||
| RUN (continuous) | 8 | mA | ||
| PWML (continuous) | 50 | mA | ||
| PWMH (continuous) | 10 | mA | ||
| SWS | Self-limiting | mA | ||
| XCD | 25 | mA | ||
| FLT | 0.3 | mA | ||
| Operating junction temperature, T J | Operating junction temperature, T J | -40 | 150 | °C |
| Storage temperature, T stg | Storage temperature, T stg | -65 | 150 | °C |
UCC28781 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| V VDD | Bias supply operating voltage | 14 | 34 | V | |
| C VDD | VDD capacitor | 10 | μF | ||
| C P13 | P13 bypass capacitor | 1 | μF | ||
| C REF | REF bypass capacitor | 0.22 | μF | ||
| T J | Operating junction temperature | -40 | 140 | °C |
UCC28781 Thermal Information
| THERMAL METRIC (1) | THERMAL METRIC (1) | UCC28781 RTW (WQFN) 24 PINS | UNIT |
|---|---|---|---|
| R θJA | Junction-to-ambient thermal resistance | 43.1 | °C/W |
| R θJC(top) | Junction-to-case (top) thermal resistance | 31.6 | °C/W |
| R θJB | Junction-to-board thermal resistance | 20.3 | °C/W |
| Ψ JT | Junction-to-top characterization parameter | 0.5 | °C/W |
| Ψ JB | Junction-to-board characterization parameter | 20.3 | °C/W |
| R θJC(bot) | Junction-to-case (bottom) thermal resistance | 5.7 | °C/W |
UCC28781 Typical Application
A typical application of a high-frequency zero-voltage switching flyback (ZVSF) converter, using the UCC28781 controller, is to enable high-density DC-to-DC or AC-to-DC power supply design which complies with stringent global and application-specific efficiency standards and high-density power packaging. Both Silicon (Si) and Gallium Nitride (GaN) power MOSFETs may be used, with appropriate gate drivers for either (if necessary).
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| UCC28781-Q1 | Texas Instruments | WQFN-24 4.0x4.0mm |
| UCC28781A | Texas Instruments | WQFN-24 4x4mm |
| UCC28781ARTWR | Texas Instruments | WQFN-24 4x4mm |
More datasheets
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