TSL2561CS/FN/CL

Part: TSL2561

Type: Light-to-Digital Converter

Description: The TSL2561 is a light-to-digital converter that transforms light intensity to a digital signal output capable of direct I²C interface, combining one broadband and one infrared photodiode for a near-photopic response over an effective 20-bit dynamic range (16-bit resolution).

Operating Conditions:

• Supply voltage: 2.7–3.6 V
• Operating temperature: -30 to 70 °C
• I²C clock frequency: up to 400 kHz

Absolute Maximum Ratings:

• Max supply voltage: 3.8 V
• Max digital output current: 20 mA
• Max storage temperature: 85 °C

Key Specs:

• Dynamic Range: 1,000,000-to-1
• Resolution: 16-bit
• Supply current (Active): 0.24 mA (Typ)
• Supply current (Power down): 3.2 μA (Typ)
• Oscillator frequency: 690–780 kHz
• Conversion time: 12–400 ms
• Dark ADC count value: 0–4 counts (E e = 0, T int = 402ms)
• Full scale ADC count value: 65535 counts (T int > 178ms, 16-bit register limited)

Features:

• Patented Dual-Diode Architecture
• Programmable Interrupt Function with User-Defined Upper and Lower Threshold Settings
• I²C Fast-Mode at 400kHz
• Programmable Analog Gain and Integration Time
• Automatically Rejects 50/60Hz Lighting Ripple
• Low Active Power with Power Down Mode

Applications:

• Display panels (LCD, OLED, etc.)
• Keyboard illumination
• Exposure control in digital cameras
• Notebook/tablet PCs
• LCD monitors
• Flat-panel televisions
• Cell phones
• Street light control
• Security lighting
• Sunlight harvesting
• Machine vision
• Automotive instrumentation clusters

Package:

• 6-Lead TMB

The benefits and features of TSL2561, Light-to-Digital Converter is listed below:

Figure 2: TSL2561 Block Diagram

Package T 6-Lead TMB:

Package drawings are not to scale

Figure 4:

Terminal Functions

Terminal	Terminal	Type	Description
Name	Pin No.
ADDR SEL	2	I	I 2 C address select - three-state
GND	3		Power supply ground. All voltages are referenced to GND.
INT	5	O	Interrupt - open drain output (active low)
SCL	4	I	I 2 C serial clock input terminal
SDA	6	I/O	I 2 C serial data I/O terminal
V DD	1		Supply voltage

The TSL2561 pin assignments are described below:

Figure 3: Pin Diagram of Package T 6-Lead TMB (Top View)

Figure 6:

Recommended Operating Conditions

Symbol	Parameter	Min	Nom	Max	Unit
V DD	Supply voltage	2.7	3	3.6	V
T A	Operating free-air temperature	-30		70	°C
V IL	SCL, SDA input low voltage	-0.5		0.8	V
V IH	SCL, SDA input high voltage	2.1		3.6	V

Figure 7:

Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted)

Symbol	Parameter	Test Conditions	Min	Typ	Max	Unit
I DD	Supply current	Active		0.24	0.6	mA
I DD	Supply current	Power down		3.2	15	μA
V OL	INT, SDA output low voltage	3mAsink current	0		0.4	V
V OL	INT, SDA output low voltage	6mAsink current	0		0.6	V
I LEAK	Leakage current		-5		5	μA

All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.

Figure 8:

Figure 8:

Operating Characteristics, High Gain (16×), V DD = 3V, T A = 25°C (unless otherwise noted) (1) , (2) , (3) , (4)

Symbol	Parameter	Test Conditions	Channel	TSL2561T	TSL2561T	TSL2561T	Unit
Symbol	Parameter	Test Conditions	Channel	Min	Typ	Max	Unit
f OSC	Oscillator frequency			690	735	780	kHz
	Dark ADC count value	E e = 0, T int = 402ms	Ch0	0		4	counts
	Dark ADC count value	E e = 0, T int = 402ms	Ch1	0		4	counts
	Full scale ADC (5)	T int > 178ms	Ch0			65535	counts
	Full scale ADC (5)	T int > 178ms	Ch1			65535	counts
	count value	T int = 101ms	Ch0			37177	counts
	count value	T int = 101ms	Ch1			37177	counts
	count value	T int = 13.7ms	Ch0			5047	counts
	count value	T int = 13.7ms	Ch1			5047	counts
	ADC count value	λ p = 640nm, T int = 101ms E e = 36.3μW/cm 2	Ch0	750	1000	1250	counts
	ADC count value	λ p = 640nm, T int = 101ms E e = 36.3μW/cm 2	Ch1		200		counts
	ADC count value	λ p = 940nm, T int = 101ms E = 119μW/cm 2	Ch0	700	1000	1300	counts
	ADC count value	e	Ch1		820		counts
	ADC count value	λ p = 640nm, T int = 101ms E e = 41μW/cm 2	Ch0				counts
	ADC count value	λ p = 640nm, T int = 101ms E e = 41μW/cm 2	Ch1				counts
	ADC count value	λ p = 940nm, T int = 101ms E e = 135μW/cm 2	Ch0				counts
	ADC count value	λ p = 940nm, T int = 101ms E e = 135μW/cm 2	Ch1				counts
	ADC count value ratio: Ch1/Ch0	λ p = 640nm, T int = 101ms		0.15	0.20	0.25
	ADC count value ratio: Ch1/Ch0	λ p = 940nm, T int = 101ms		0.69	0.82	0.95
R e	Irradiance responsivity	λ p = 640nm, T int = 101ms	Ch0		27.5		counts/ (μW/cm 2 )
R e	Irradiance responsivity	λ p = 640nm, T int = 101ms	Ch1		5.5		counts/ (μW/cm 2 )
R e	Irradiance responsivity	λ p = 940nm, T int = 101ms	Ch0		8.4		counts/ (μW/cm 2 )
R e	Irradiance responsivity	λ p = 940nm, T int = 101ms	Ch1		6.9		counts/ (μW/cm 2 )
Symbol	Parameter	Test Conditions	Channel	TSL2561T	TSL2561T	TSL2561T	Unit
Symbol	Parameter	Test Conditions Fluorescent light source: T int = 402ms Fluorescent light source: T int = 402ms Incandescentlight source: T int = 402ms Incandescentlight source: T int = 402ms Fluorescent light source: T int = 402ms Incandescentlight source: T int = 402ms Fluorescent light source: T int = 402ms Fluorescent light source: T int = 402ms Incandescentlight source: T int = 402ms Incandescentlight source: T int = 402ms	Channel Ch0 Ch1 Ch0 Ch1 Ch0 Ch1 Ch0 Ch1	Min	Typ 36 4 144 72 0.11 0.5 2.3 0.25 9 4.5	Max	Unit
		Fluorescent light source: T int = 402ms		0.65	1	1.35
		Incandescentlight source: T int = 402ms		0.60	1	1.40

Field value 00: T int = (11 × 918)/f osc = 13.7ms

Field value 01: T int = (81 × 918)/f osc = 101ms

Field value 10: T int = (322 × 918)/f osc = 402ms

Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01), and 322/322 = 1 (field value 10).

1. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also by a 2-count offset.

Full scale ADC count value = ((number of clock cycles)/2 - 2)

Field value 00: Full scale ADC count value = ((11 × 918)/2 - 2) = 5047

Field value 01: Full scale ADC count value = ((81 × 918)/2 - 2) = 37177

Field value 10: Full scale ADC count value = 65535, which is limited by 16-bit register. This full scale ADC count value is reached for 131074 clock cycles, which occurs for T int = 178ms for nominal f osc = 735kHz.

1. Low gain mode has 16× lower gain than high gain mode: (1/16 = 0.0625).
2. The sensor Lux is calculated using the empirical formula shown in Calculating Lux of this data sheet based on measured Ch0 and Ch1 ADC count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual Lux) ratio is estimated based on the variation of the 640nm and 940nm optical parameters. Devices are not 100% tested with fluorescent or incandescent light sources.

Figure 5:

Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted)

Symbol	Parameter	Min	Max	Unit
V DD	Supply voltage (1)		3.8	V
V O	Digital output voltage range	-0.5	3.8	V
I O	Digital output current	-1	20	mA
T strg	Storage temperature range	-40	85	°C
ESD HBM	ESD tolerance, human body model	±2000	±2000	V

1. All voltages are with respect to GND.

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 25: Bus Pull-Up Resistors

Pull-up resistors (R p ) maintain the SDAH and SCLH lines at a high level when the bus is free and ensure the signals are pulled up from a low to a high level within the required rise time. For a complete description of I²C maximum and minimum R p values, please review the I²C Specification at http://www.nxp.com.

A pull-up resistor (RPI) is also required for the interrupt (INT), which functions as a wired-AND signal in a similar fashion to the SCL and SDA lines. A typical impedance value between 10kΩ and 100kΩ can be used. Please note that while Figure 25 shows INT being pulled up to V DD , the interrupt can optionally be pulled up to V BUS .

Figure 27: Package T - Six-Lead TMB Plastic Surface Mount Packaging Configuration

1. All linear dimensions are in millimeters. Dimension tolerance is ±0.20mm unless otherwise noted.
2. The photo-active area is 1398μm by 203μm.
3. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
4. Contact finish is 0.5μm minimum of soft gold plated over a 18μm thick copper foil pattern with a 5μm to 9μm nickel barrier.
5. The underside of the package includes copper traces used to connect the pads during package substrate fabrication. Accordingly, exposed traces and vias should not be placed under the footprint of the TMB package in a PCB layout.
6. This package contains no lead (Pb).
7. This drawing is subject to change without notice.