TSL2561CS/FN/CL

Part: TSL2561 Type: Light-to-Digital Converter

Key Specs:

• Dynamic Range: 1,000,000-to-1
• Resolution: 16-bit
• I²C Fast-Mode: 400kHz
• Low Active Power: 0.75mW typical
• Recommended Supply Voltage: 2.7 V to 3.6 V
• Recommended Operating Temperature: -30 °C to 70 °C
• Absolute Maximum Supply Voltage: 3.8 V
• Absolute Maximum Storage Temperature: -40 °C to 85 °C
• ESD Tolerance (HBM): ±2000 V

Features:

• Patented Dual-Diode Architecture
• Programmable Interrupt Function with User-Defined Upper and Lower Threshold Settings
• I²C Digital Interface
• Approximates Human Eye Response
• Programmable Analog Gain and Integration Time
• Automatically Rejects 50/60Hz Lighting Ripple
• Power Down Mode
• Traditional level style interrupt that remains asserted until the firmware clears it
• Two integrating ADCs convert photodiode currents to a digital output
• Double-buffered transfers

Applications:

• Display panels (LCD, OLED, etc.)
• Controlling keyboard illumination
• Exposure control in digital cameras
• Notebook/tablet PCs
• LCD monitors
• Flat-panel televisions
• Cell phones
• Digital cameras
• Street light control
• Security lighting
• Sunlight harvesting
• Machine vision
• Automotive instrumentation clusters

Package:

• TMB Packages: 2.6mm x 3.8mm
• 6-Lead TMB

The benefits and features of TSL2561, Light-to-Digital Converter is listed below:

Figure 1: Added Value of Using TSL2561

Benefits	Features
• Enables Operation in IR Light Environments	• Patented Dual-Diode Architecture
• Enables Dark Room to High Lux Sunlight Operation	• 1M:1 Dynamic Range
• Reduces Micro-Processor Interrupt Overhead	• Programmable Interrupt Function
• Digital Interface is Less Susceptible to Noise	• I²C Digital Interface
• Reduces Board Space Requirements while Simplifying Designs	• Available in 2.6mm x 3.8mm TMB Packages

• • Approximates Human Eye Response
• • Programmable Interrupt Function with User-Defined Upper and Lower Threshold Settings
• • 16-Bit Digital Output with I²C Fast-Mode at 400kHz
• • Programmable Analog Gain and Integration Time Supporting 1,000,000-to-1 Dynamic Range
• • Automatically Rejects 50/60Hz Lighting Ripple
• • Low Active Power (0.75mW typical) with Power Down Mode

Package T 6-Lead TMB:

Package drawings are not to scale

The TSL2561 pin assignments are described below:

Figure 3: Pin Diagram of Package T 6-Lead TMB (Top View)

6 SDA 5 INT 4 SCL VDD 1 ADDR SEL 2 GND 3

Figure 4: Terminal Functions

Name	Pin No.	Type	Description
ADDR SEL	2	I	I²C address select - three-state
GND	3		Power supply ground. All voltages are referenced to GND.
INT	5	O	Interrupt - open drain output (active low)
SCL	4	I	I²C serial clock input terminal
SDA	6	I/O	I²C serial data I/O terminal
VDD	1		Supply voltage

All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.

Figure 6:

Recommended Operating Conditions

Symbol	Parameter	Min	Nom	Max	Unit
VDD	Supply voltage	2.7	3	3.6	V
TA	Operating free-air temperature	-30		70	°C
VIL	SCL, SDA input low voltage	-0.5		0.8	V
VIH	SCL, SDA input high voltage	2.1		3.6	V

Figure 7:

Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted)

Symbol	Parameter	Test Conditions	Min	Typ	Max	Unit
I DD	Supply current	Active		0.24	0.6	mA
		Power down		3.2	15	μA
VOL	INT, SDA output low voltage	3mA sink current	0		0.4	V
		6mA sink current	0		0.6	V
I LEAK	Leakage current		-5		5	μA

Figure 8:

Operating Characteristics, High Gain (16×), VDD = 3V, TA = 25°C (unless otherwise noted) (1), (2), (3), (4)

Symbol	Parameter	Min	Nom	Max	Unit
VDD	Supply voltage	2.7	3	3.6	V
TA	Operating free-air temperature	-30		70	°C
VIL	SCL, SDA input low voltage	-0.5		0.8	V
VIH	SCL, SDA input high voltage	2.1		3.6	V
Symbol	Parameter	Test Conditions	Min	Typ	Max
---	---	---	---	---	---
IDD	Supply current	Active		0.24	0.6
		Power down		3.2	15
VOL	INT, SDA output low voltage	3mA sink current	0		0.4
		6mA sink current	0		0.6
ILEAK	Leakage current		-5		5

Note(s):

1. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640nm LEDs and infrared 940nm LEDs are used for final product testing for compatibility with high-volume production.

2. The 640nm irradiance Ee is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength λp = 640nm and spectral halfwidth Δλ½ = 17nm.

3. The 940nm irradiance Ee is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelength λp = 940nm and spectral halfwidth Δλ½ = 40nm.

4. Integration time Tint, is dependent on internal oscillator frequency (fosc) and on the integration field value in the timing register as described in the Register Set section. For nominal fosc = 735kHz, nominal Tint = (number of clock cycles)/fosc.

Field value 00: Tint = (11 × 918)/fosc = 13.7ms

Field value 01: Tint = (81 × 918)/fosc = 101ms

Field value 10: Tint = (322 × 918)/fosc = 402ms

Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01), and 322/322 = 1 (field value 10).

• 5. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also by a 2-count offset.
  • Full scale ADC count value = ((number of clock cycles)/2 - 2)

Field value 00: Full scale ADC count value = ((11 × 918)/2 - 2) = 5047

Field value 01: Full scale ADC count value = ((81 × 918)/2 - 2) = 37177

Field value 10: Full scale ADC count value = 65535, which is limited by 16-bit register. This full scale ADC count value is reached for 131074 clock cycles, which occurs for Tint = 178ms for nominal fosc = 735kHz.

6. Low gain mode has 16× lower gain than high gain mode: (1/16 = 0.0625).

7. The sensor Lux is calculated using the empirical formula shown in Calculating Lux of this data sheet based on measured Ch0 and

Ch1 ADC count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual Lux) ratio is estimated based on the variation of the 640nm and 940nm optical parameters. Devices are not 100% tested with fluorescent or incandescent light sources.

Figure 9:

AC Electrical Characteristics, VDD = 3V, TA = 25°C (unless otherwise noted)

Symbol	Parameter (1)	Test Conditions	Min	Typ	Max	Unit
t(CONV)	Conversion time		12	100	400	ms
f(SCL)	Clock frequency (I²C)		0		400	kHz
t(BUF)	Bus free time between start and stop condition		1.3			μs
t(HDSTA)	Hold time after (repeated) start condition. After this period, the first clock is generated.		0.6			μs
t(SUSTA)	Repeated start condition setup time		0.6			μs
t(SUSTO)	Stop condition setup time		0.6			μs
t(HDDAT)	Data hold time		0		0.9	μs
t(SUDAT)	Data setup time		100			ns
t(LOW)	SCL clock low period		1.3			μs
t(HIGH)	SCL clock high period		0.6			μs
tF	Clock/data fall time				300	ns
tR	Clock/data rise time				300	ns
Ci	Input pin capacitance				10	pF

Note(s):

1. Specified by design and characterization; not production tested.

Figure 10: Timing Diagrams

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 5:

Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted)

Symbol	Parameter	Min	Max	Unit
VDD	Supply voltage (1)		3.8	V
VO	Digital output voltage range	-0.5	3.8	V
IO	Digital output current	-1	20	mA
Tstrg	Storage temperature range	-40	85	°C
ESDHBM	ESD tolerance, human body model	±2000		V

Note(s):

1. All voltages are with respect to GND.

Power Supply Decoupling and Application Hardware Circuit

The power supply lines must be decoupled with a 0.1μF capacitor placed as close to the device package as possible (Figure 25). The bypass capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents caused by internal logic switching.

Figure 25: Bus Pull-Up Resistors

Pull-up resistors (Rp) maintain the SDAH and SCLH lines at a high level when the bus is free and ensure the signals are pulled up from a low to a high level within the required rise time. For a complete description of I²C maximum and minimum Rp values, please review the I²C Specification at http://www.nxp.com.

A pull-up resistor (RPI) is also required for the interrupt (INT), which functions as a wired-AND signal in a similar fashion to the SCL and SDA lines. A typical impedance value between 10kΩ and 100kΩ can be used. Please note that while Figure 25 shows INT being pulled up to VDD, the interrupt can optionally be pulled up to VBUS.

PCB Pad Layout

Suggested PCB pad layout guidelines for the TMB-6 (T) surface mount package is shown in Figure 26.

Figure 26: Suggested T Package PCB Layout

Note(s):

1. All linear dimensions are in millimeters.

2. This drawing is subject to change without notice.

Figure 27: Package T - Six-Lead TMB Plastic Surface Mount Packaging Configuration

Note(s):

• 1. All linear dimensions are in millimeters. Dimension tolerance is ±0.20mm unless otherwise noted.
• 1. The photo-active area is 1398μm by 203μm.
• 1. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
• 1. Contact finish is 0.5μm minimum of soft gold plated over a 18μm thick copper foil pattern with a 5μm to 9μm nickel barrier.
• 1. The underside of the package includes copper traces used to connect the pads during package substrate fabrication. Accordingly, exposed traces and vias should not be placed under the footprint of the TMB package in a PCB layout.
• 1. This package contains no lead (Pb).
• 1. This drawing is subject to change without notice.

Figure 28: TSL2561 TMB Carrier Tape

Note(s):

• 1. All linear dimensions are in millimeters.
• 1. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
• 1. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481-B 2001.
• 1. Each reel is 178 millimeters in diameter and contains 1000 parts.
• 1. ams AG packaging tape and reel conform to the requirements of EIA Standard 481-B.
• 1. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
• 1. This drawing is subject to change without notice.