TLV1117LV

Part: TLV1117LVxx — Texas Instruments

Type: Low Dropout Linear Regulator (LDO)

Description: A low dropout linear regulator (LDO) capable of delivering up to 1A to the load, featuring internal thermal and current limit shutdown circuitry, and very low dropout voltage.

Operating Conditions:

• Supply voltage: 2V to 6V
• Max output current: 1A

Absolute Maximum Ratings:

• Max junction temperature: 150 °C

Key Specs:

• Output current: Up to 1A
• Minimum effective input/output capacitance for stability: 0.4 μF
• Thermal resistance (θ JA, EVM layout, DCY package): 47.8 °C/W
• Max power dissipation (EVM layout, T A = 25 °C): 2.615W
• Max power dissipation (EVM layout, T A = 70 °C): 1.674W
• Dropout voltage: Very low

Features:

• Internal thermal shutdown circuitry
• Internal current limit shutdown circuitry
• Very low dropout voltage

Package:

• SOT-223

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated

Thermal management is a key component of design of any power converter and is especially important when the power dissipation in the LDO is high. Use the following formula to approximate the maximum power dissipation for the particular ambient temperature:

Where TJ is the junction temperature, T A is the ambient temperature, P D is the power dissipation in the device (Watts), and θ JA is the thermal resistance from junction to ambient. All temperatures are in degrees Celsius. The maximum silicon junction temperature, T J , must not be allowed to exceed 150 ° C. The layout design must use copper trace and plane areas smartly, as thermal sinks, in order not to allow T J to exceed the absolute maximum rating under all temperature conditions and voltage conditions across the part.

The layout should consider carefully the thermal design of the PCB for optimal performance over temperature. For this EVM, Figure 4 shows the PCB top V OUT plane has twenty-four 6-mil thermal via connections to the bottom side copper V OUT plane to dissipate heat. The PCB is a two layer board with 2oz. copper on top and bottom layers. The DCY package drawing can be found at the Texas Instruments web site in the product folder for the TLV1117LVxx LDO.

Table 1 repeats information from the Dissipation Ratings Table of the TLV1117LV series data sheet for comparison with the thermal resistance, θ JA , calculated for this EVM layout to show the wide variation in thermal resistances for given copper areas. The High-K value is determined using a standard JEDEC High-K (2s2p) board having dimensions of 3-inch x 3-inch with 1-oz internal power and ground planes and 2-oz copper traces on top and bottom of the board.

Table 1. Thermal Resistance, θ JA, and Maximum Power Dissipation