TLV1117LV

Part: TLV1117LVxxEVM-714 (TLV1117LV18DCY / TLV1117LV33DCY LDO) — Texas Instruments

Type: LDO Linear Regulator Evaluation Module

Description: Evaluation module for the TLV1117LVxx family of 1 A fixed-output low dropout linear regulators in a SOT-223 package, with an EVM input range of 2–6 V.

Operating Conditions:

• Supply voltage: 2–6 V (EVM input range); output not to exceed 6 V
• Operating temperature: not applicable
• Load current: 0–1 A
• Input/output capacitors: 0.4 μF effective minimum for stability; 10 μF used on the EVM

Absolute Maximum Ratings:

• Max junction temperature: 150 °C (stated as the maximum silicon junction temperature in the thermal guidelines)

Key Specs:

• Output current: up to 1 A
• EVM input voltage: 2–6 V; recommended initial setting 5 V
• Thermal resistance θJA: 47.8 °C/W (EVM layout, DCY package); 62.9 °C/W (High-K JEDEC board)
• Max dissipation without derating, EVM board: 2.615 W at TA = 25 °C; 1.674 W at TA = 70 °C
• Max dissipation without derating, High-K board: 1.59 W at TA = 25 °C; 874 mW at TA = 70 °C
• Load transient test: 100 mA to 500 mA step at VIN = 3.3 V (1.8 V version)
• Turn-on test: VIN = 3.3 V, 1 A full load; startup ramp is not load dependent

Features:

• Internal thermal shutdown and current limit
• Very low dropout voltage
• Two-layer, 2 oz copper PCB with twenty-four 6-mil thermal vias on the VOUT plane
• 10 μF ceramic input and output capacitors (0603, X5R, 6.3 V)
• Available in 1.8 V (TLV1117LV18DCY) and 3.3 V (TLV1117LV33DCY) fixed-output versions

Applications:

• Engineering evaluation and demonstration of the TLV1117LVxx LDO family

Package:

• SOT-223 (DCY)

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Thermal management is a key component of design of any power converter and is especially important when the power dissipation in the LDO is high. Use the following formula to approximate the maximum power dissipation for the particular ambient temperature:

TJ = T A + P D × θ JA

Where TJ is the junction temperature, T A is the ambient temperature, P D is the power dissipation in the device (Watts), and θ JA is the thermal resistance from junction to ambient. All temperatures are in degrees Celsius. The maximum silicon junction temperature, T J , must not be allowed to exceed 150 ° C. The layout design must use copper trace and plane areas smartly, as thermal sinks, in order not to allow T J to exceed the absolute maximum rating under all temperature conditions and voltage conditions across the part.

The layout should consider carefully the thermal design of the PCB for optimal performance over temperature. For this EVM, Figure 4 shows the PCB top V OUT plane has twenty-four 6-mil thermal via connections to the bottom side copper V OUT plane to dissipate heat. The PCB is a two layer board with 2oz. copper on top and bottom layers. The DCY package drawing can be found at the Texas Instruments web site in the product folder for the TLV1117LVxx LDO.

Table 1 repeats information from the Dissipation Ratings Table of the TLV1117LV series data sheet for comparison with the thermal resistance, θ JA , calculated for this EVM layout to show the wide variation in thermal resistances for given copper areas. The High-K value is determined using a standard JEDEC High-K (2s2p) board having dimensions of 3-inch x 3-inch with 1-oz internal power and ground planes and 2-oz copper traces on top and bottom of the board.

Table 1. Thermal Resistance, θ JA, and Maximum Power Dissipation