TLV1117LV

TLV1117LVxxEVM-714 Evaluation Module

Manufacturer

Texas Instruments

Overview

Part: Texas Instruments TLV1117LVxx

Type: Low Dropout Linear Regulator (LDO)

Key Specs:

  • Max Output Current: 1A
  • Min Input/Output Capacitance for Stability: 0.4 μF
  • Max Junction Temperature: 150°C

Features:

  • Internal thermal shutdown circuitry
  • Internal current limit shutdown circuitry
  • Very low dropout voltage

Applications: null

Package:

  • SOT-223: dimensions null
  • DCY: dimensions null

Thermal Information

Thermal management is a key component of design of any power converter and is especially important when the power dissipation in the LDO is high. Use the following formula to approximate the maximum power dissipation for the particular ambient temperature:

$mathbf{T}lambda = mathbf{T}lambda + mathbf{P}odot × mathbf{G}lambda tag{7}$

Where TJ is the junction temperature, TA is the ambient temperature, PD is the power dissipation in the device (Watts), and θJA is the thermal resistance from junction to ambient. All temperatures are in degrees Celsius. The maximum silicon junction temperature, TJ , must not be allowed to exceed 150°C. The layout design must use copper trace and plane areas smartly, as thermal sinks, in order not to allow TJ to exceed the absolute maximum rating under all temperature conditions and voltage conditions across the part.

The layout should consider carefully the thermal design of the PCB for optimal performance over temperature. For this EVM, Figure 4 shows the PCB top VOUT plane has twenty-four 6-mil thermal via connections to the bottom side copper VOUT plane to dissipate heat. The PCB is a two layer board with 2oz. copper on top and bottom layers. The DCY package drawing can be found at the Texas Instruments web site in the product folder for the TLV1117LVxx LDO.

Table 1 repeats information from the Dissipation Ratings Table of the TLV1117LV series data sheet for comparison with the thermal resistance, θJA, calculated for this EVM layout to show the wide variation in thermal resistances for given copper areas. The High-K value is determined using a standard JEDEC High-K (2s2p) board having dimensions of 3-inch x 3-inch with 1-oz internal power and ground planes and 2-oz copper traces on top and bottom of the board.

Table
1.
Thermal
Resistance,
θJA,and
Maximum
PowerDissipation
---------------------------------------------------------------------------------

BoardPackageθJAMax Dissipation Without
Derating
(TA
= 25°C)
Max Dissipation Without
Derating
(TA
= 70°C)
High-KDCY62.9°C/W1.59 W874 mW
TLV1117LVxxEVM-714DCY47.8°C/W2.615 W1.674 W

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
TLV1117LV33Texas Instruments
TLV1117LVXXTexas Instruments
TLV1117LVXXEVMTexas Instruments
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