TLC5940
TLC5940 16-Channel LED Driver With DOT Correction and Grayscale PWM Control
Manufacturer
unknown
Overview
Part: TLC5940
Type: 16-Channel LED Driver With DOT Correction and Grayscale PWM Control
Key Specs:
- Channels: 16
- Grayscale PWM Control: 12 bit (4096 Steps)
- Dot Correction: 6 bit (64 Steps)
- Drive Capability (Constant-Current Sink, VCC < 3.6 V): 0 mA to 60 mA
- Drive Capability (Constant-Current Sink, VCC > 3.6 V): 0 mA to 120 mA
- LED Power Supply Voltage: up to 17 V
- VCC: 3 V to 5.5 V
- Data Transfer Rate: 30 MHz
Features:
- 16 Channels
- 12 bit (4096 Steps) Grayscale PWM Control
- Dot Correction (6 bit, 64 Steps)
- Dot Correction Storable in Integrated EEPROM
- Drive Capability (Constant-Current Sink) 0 mA to 120 mA
- LED Power Supply Voltage up to 17 V
- VCC = 3 V to 5.5 V
- Serial Data Interface
- Controlled In-Rush Current
- 30 MHz Data Transfer Rate
- CMOS Level I/O
- Error Information: LOD (LED Open Detection)
- Error Information: TEF (Thermal Error Flag)
Applications:
- Monocolor, Multicolor, Full-Color LED Displays
- LED Signboards
- Display Backlighting
- General, High-Current LED Drive
Package:
- PDIP (28): 35.69 mm × 6.73 mm
- HTSSOP (28): 9.70 mm × 4.40 mm
- VQFN (32): 5.00 mm × 5.00 mm
Features
- 16 Channels
- 12 bit (4096 Steps) Grayscale PWM Control
- Dot Correction
- 6 bit (64 Steps)
- Storable in Integrated EEPROM
- Drive Capability (Constant-Current Sink)
- 0 mA to 60 mA (VCC < 3.6 V)
- 0 mA to 120 mA ( $V_{CC} > 3.6 \text{ V}$ )
- LED Power Supply Voltage up to 17 V
- $V_{CC} = 3 \text{ V to } 5.5 \text{ V}$
- Serial Data Interface
- Controlled In-Rush Current
- 30 MHz Data Transfer Rate
- CMOS Level I/O
- Error Information
- LOD: LED Open Detection
- TEF: Thermal Error Flag
Applications
- Monocolor, Multicolor, Full-Color LED Displays
- LED Signboards
- Display Backlighting
- General, High-Current LED Drive
Pin Configuration
NC - No internal connection
Pin Functions
| | Pin Functions | |-------|---------------|---------|---------|------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--| | | | PIN | | TYPE | DESCRIPTION | | NAME | DIP NO. | PWP NO. | RHB NO. | ITFE | DESCRIPTION | | BLANK | 23 | 2 | 31 | I | Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also reset. When BLANK = L, OUTn are controlled by grayscale PWM control. | | DCPRG | 19 | 26 | 25 | 1 | Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H, DC is connected to the DC register. DCPRG also controls EEPROM writing, when VPRG = $V_{(PRG)}$ . EEPROM data = 3 Fh (default) | | GND | 22 | 1 | 30 | G | Ground | | GSCLK | 18 | 25 | 24 | 1 | Reference clock for grayscale PWM control | | IREF | 20 | 27 | 26 | I | Reference current terminal | | | _ | _ | 12 | | NO | _ | _ | 13 | | No connection | | NC | _ | _ | 28 | _ | No connection | | | _ | _ | 29 | | OUT0 | 28 | 7 | 4 | 0 | Constant current output | | OUT1 | 1 | 8 | 5 | 0 | Constant current output | | OUT2 | 2 | 9 | 6 | 0 | Constant current output | | OUT3 | 3 | 10 | 7 | 0 | Constant current output | | OUT4 | 4 | 11 | 8 | 0 | Constant current output | | OUT5 | 5 | 12 | 9 | 0 | Constant current output | | OUT6 | 6 | 13 | 10 | 0 | Constant current output | | OUT7 | 7 | 14 | 11 | 0 | Constant current output | | OUT8 | 8 | 15 | 14 | 0 | Constant current output | | OUT9 | 9 | 16 | 15 | 0 | Constant current output | | OUT10 | 10 | 17 | 16 | 0 | Constant current output | | OUT11 | 11 | 18 | 17 | 0 | Constant current output | | OUT12 | 12 | 19 | 18 | 0 | Constant current output | | OUT13 | 13 | 20 | 19 | 0 | Constant current output | | OUT14 | 14 | 21 | 20 | 0 | Constant current output | | OUT15 | 15 | 22 | 21 | 0 | Constant current output | | SCLK | 25 | 4 | 1 | I | Serial data shift clock | | SIN | 26 | 5 | 2 | I | Serial data input | | SOUT | 17 | 24 | 23 | 0 | Serial data output | | VCC | 21 | 28 | 27 | 1 | Power supply voltage | | VPRG | 27 | 6 | 3 | I | Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = $V_{CC}$ , the device is in DC mode. When VPRG = $V_{(VPRG)}$ , DC register data can programmed into DC EEPROM with DCPRG=HIGH. EEPROM data = 3 Fh (default) | | XERR | 16 | 23 | 22 | 0 | Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected. | | XLAT | 24 | 3 | 32 | I | Level triggered latch signal. When XLAT = high, the TLC5940 writes data from the input shift register to either GS register (VPRG = low) or DC register (VPRG = high). When XLAT = low, the data in GS or DC register is held constant. | Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Electrical Characteristics
$V_{CC} = 3 \text{ V to } 5.5 \text{ V}, T_A = -40^{\circ}\text{C to } 85^{\circ}\text{C}$ (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| V OH | High-level output voltage | I OH = -1 mA, SOUT | V CC -0.5 | V | ||
| V OL | Low-level output voltage | I OL = 1 mA, SOUT | 0.5 | V | ||
| $V_{I} = V_{CC}$ or GND; BLANK, DCPRG, GSCLK, SCLK, SIN, XLAT | -1 | 1 | ||||
| II | Input current | V I = GND; VPRG | -1 | 1 | μA | |
| $V_I = V_{CC}$ ; VPRG | 50 | |||||
| $V_I = 22 \text{ V}; \text{ VPRG}; \text{ DCPRG} = V_{CC}$ | 4 | 10 | mA | |||
| No data transfer, all output OFF, $V_O = 1 \text{ V}, \text{ R}_{(IREF)} = 10 \text{ k}\Omega$ | 0.9 | 6 | ||||
| L | Supply current | No data transfer, all output OFF, $V_O = 1 \text{ V}, \text{ R}_{(IREF)} = 1.3 \text{ k}\Omega$ | 5.2 | 12 | mA | |
| I CC | Зиppіy cипeні | Data transfer 30MHz, all output ON, $V_O = 1 \text{ V}, \text{ R}_{(IREF)} = 1.3 \text{ k}\Omega$ | 16 | 25 | ШA | |
| Data transfer 30MHz, all output ON, $V_O = 1 \text{ V}, R_{(IREF)} = 640 \Omega$ | 30 | 60 | ||||
| $I_{O(LC)}$ | Constant sink current (see Figure 10) | All output ON, $V_O = 1 \text{ V}$ , $R_{(IREF)} = 640 \Omega$ | 54 | 61 | 69 | mA |
| I lkg | Leakage output current | All output OFF, $V_0$ = 15 V, $R_{(IREF)}$ = 640 $\Omega$ , OUT0 to OUT15 | 0.1 | μΑ | ||
| All output ON, $V_O$ = 1 V, $R_{(IREF)}$ = 640 $\Omega$ , OUT0 to OUT15, -20°C to 85°C | ±1% | ±4% | ||||
| A.1 | Constant sink current error (see Figure 10) | All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 640 $\Omega$ , OUT0 to OUT15 (1) | ±1% | ±8% | ||
| ΔI O(LC0) | All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 320 $\Omega$ , OUT0 to OUT15, -20°C to 85°C | ±1% | ±6% | |||
| All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 320 $\Omega$ , $V_{CC}$ = 4.5 V to 5.5 V, OUT0 to OUT15 (1) | ±1% | ±8% | ||||
| $\Delta I_{O(LC1)}$ | Constant sink current error (see Figure 10) | Device to device, Averaged current from OUT0 to OUT15, $R_{(IREF)} = 1920 \Omega (20 \text{ mA})^{(2)}$ | -2% +0.4% | ±4% | ||
| $\Delta I_{O(LC2)}$ | Constant sink current error (see Figure 10) | Device to device, Averaged current from OUT0 to OUT15, $R_{(IREF)} = 480 \Omega (80 \text{ mA})^{(2)}$ | -2.7% +2% | ±4% | ||
| A.1 | Line negation (see Figure 40) | All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 640 $\Omega$ OUT0 to OUT15, $V_{CC}$ = 3 V to 5.5 $V^{(3)}$ | ±1 | ±4 | %/V | |
| ΔI O(LC3) | Line regulation (see Figure 10) | All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 320 $\Omega$ , OUT0 to OUT15, $V_{CC}$ = 3 V to 5.5 V $^{(3)}$ | ±1 | ±6 | %/V | |
| Δ1 | Load regulation (see | All output ON, $V_O$ = 1 V to 3 V, $R_{(IREF)}$ = 640 $\Omega$ , OUT0 to OUT15 $^{(4)}$ | ±2 | ±6 | %/V | |
| $\Delta I_{O(LC4)}$ | Figure 10) | All output ON, $V_O = 1$ V to 3 V, $R_{(IREF)} = 320 \Omega$ , OUT0 to OUT15 (4) | ±2 | ±8 | %/V | |
| T (TEF) | Thermal error flag threshold | Junction temperature (5) | 150 | 170 | °C | |
| V (LED) | LED open detection threshold | 0.3 | 0.4 | ٧ | ||
| V (IREF) | Reference voltage output | $R_{(IREF)} = 640 \Omega$ | 1.20 | 1.24 | 1.28 | V |
(1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Test Parameter Equations.
(2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Test Parameter Equations. The ideal current is calculated by Equation 3 in Test Parameter Equations.
(3) The line regulation is calculated by Equation 4 in Test Parameter Equations.
(4) The load regulation is calculated by Equation 5 in Test Parameter Equations.
(5) Not tested. Specified by design
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VCC | –0.3 | 6 | V | |
| Input voltage(2) | V(BLANK), V(DCPRG), V(SCLK), V(XLAT), V(SIN), V(GSCLK), V(IREF) | –0.3 | VCC +0.3 | V |
| V(SOUT), V(XERR) | –0.3 | VCC +0.3 | V | |
| Output voltage | V(OUT0) to V(OUT15) | –0.3 | 18 | V |
| Output current (dc) | 130 | mA | ||
| EEPROM program range | V(VPRG) | –0.3 | 24 | V |
| EEPROM write cycles | 50 | — | ||
| Storage temperature, Tstg | –55 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operting Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| DC CHARACTERISTICS | ||||||
| VCC | Supply Voltage | 3 | 5.5 | V | ||
| V O | Voltage applied to output (OUT0–OUT15) | 17 | V | |||
| VIH | High-level input voltage | 0.8 VCC | VCC | V | ||
| VIL | Low-level input voltage | GND | 0.2 VCC | V | ||
| IOH | High-level output current | VCC = 5 V at SOUT | –1 | mA | ||
| IOL | Low-level output current | VCC = 5 V at SOUT, XERR | 1 | mA | ||
| OUT0 to OUT15, VCC < 3.6 V | 60 | mA | ||||
| IOLC | Constant output current | OUT0 to OUT15, VCC > 3.6 V | 120 | mA | ||
| V(VPRG) | EEPROM program voltage | 20 | 22 | 23 | V | |
| TA | Operating free-air temperature range | -40 | 85 | °C | ||
| AC CHARACTERISTICS VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted) | ||||||
| f(SCLK) | Data shift clock frequency | SCLK | 30 | MHz | ||
| f(GSCLK) | Grayscale clock frequency | GSCLK | 30 | MHz | ||
| twh0/twl0 | SCLK pulse duration | SCLK = H/L (see Figure 11) | 16 | ns | ||
| twh1/twl1 | GSCLK pulse duration | GSCLK = H/L (see Figure 11) | 16 | ns | ||
| twh2 | XLAT pulse duration | XLAT = H (see Figure 11) | 20 | ns | ||
| twh3 | BLANK pulse duration | BLANK = H (see Figure 11) | 20 | ns |
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Thermal Information
| | | TLC | 5940 | |-----------------------|----------------------------------------------|--------------|------------|------| | | THERMAL METRIC (1) | PWP (HTSSOP) | RHB (VQFN) | UNIT | | | | 28 PINS | 32 PINS | | $R_{\theta JA}$ | Junction-to-ambient thermal resistance | 36.7 | 34.3 | °C/W | | $R_{\theta JC(top)}$ | Junction-to-case (top) thermal resistance | 18.9 | 36.8 | °C/W | | $R_{\theta JB}$ | Junction-to-board thermal resistance | 15.9 | 8.5 | °C/W | | ΨЈT | Junction-to-top characterization parameter | 0.6 | 0.3 | °C/W | | ΨЈB | Junction-to-board characterization parameter | 15.8 | 8.7 | °C/W | | R 0JC(bot) | Junction-to-case (bottom) thermal resistance | 2.3 | 1.6 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
$V_{CC} = 3 \text{ V to } 5.5 \text{ V}, T_A = -40^{\circ}\text{C to } 85^{\circ}\text{C}$ (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| V OH | High-level output voltage | I OH = -1 mA, SOUT | V CC -0.5 | V | ||
| V OL | Low-level output voltage | I OL = 1 mA, SOUT | 0.5 | V | ||
| $V_{I} = V_{CC}$ or GND; BLANK, DCPRG, GSCLK, SCLK, SIN, XLAT | -1 | 1 | ||||
| II | Input current | V I = GND; VPRG | -1 | 1 | μA | |
| $V_I = V_{CC}$ ; VPRG | 50 | |||||
| $V_I = 22 \text{ V}; \text{ VPRG}; \text{ DCPRG} = V_{CC}$ | 4 | 10 | mA | |||
| No data transfer, all output OFF, $V_O = 1 \text{ V}, \text{ R}_{(IREF)} = 10 \text{ k}\Omega$ | 0.9 | 6 | ||||
| L | Supply current | No data transfer, all output OFF, $V_O = 1 \text{ V}, \text{ R}_{(IREF)} = 1.3 \text{ k}\Omega$ | 5.2 | 12 | mA | |
| I CC | Зиppіy cипeні | Data transfer 30MHz, all output ON, $V_O = 1 \text{ V}, \text{ R}_{(IREF)} = 1.3 \text{ k}\Omega$ | 16 | 25 | ШA | |
| Data transfer 30MHz, all output ON, $V_O = 1 \text{ V}, R_{(IREF)} = 640 \Omega$ | 30 | 60 | ||||
| $I_{O(LC)}$ | Constant sink current (see Figure 10) | All output ON, $V_O = 1 \text{ V}$ , $R_{(IREF)} = 640 \Omega$ | 54 | 61 | 69 | mA |
| I lkg | Leakage output current | All output OFF, $V_0$ = 15 V, $R_{(IREF)}$ = 640 $\Omega$ , OUT0 to OUT15 | 0.1 | μΑ | ||
| All output ON, $V_O$ = 1 V, $R_{(IREF)}$ = 640 $\Omega$ , OUT0 to OUT15, -20°C to 85°C | ±1% | ±4% | ||||
| A.1 | Constant sink current error (see Figure 10) | All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 640 $\Omega$ , OUT0 to OUT15 (1) | ±1% | ±8% | ||
| ΔI O(LC0) | All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 320 $\Omega$ , OUT0 to OUT15, -20°C to 85°C | ±1% | ±6% | |||
| All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 320 $\Omega$ , $V_{CC}$ = 4.5 V to 5.5 V, OUT0 to OUT15 (1) | ±1% | ±8% | ||||
| $\Delta I_{O(LC1)}$ | Constant sink current error (see Figure 10) | Device to device, Averaged current from OUT0 to OUT15, $R_{(IREF)} = 1920 \Omega (20 \text{ mA})^{(2)}$ | -2% +0.4% | ±4% | ||
| $\Delta I_{O(LC2)}$ | Constant sink current error (see Figure 10) | Device to device, Averaged current from OUT0 to OUT15, $R_{(IREF)} = 480 \Omega (80 \text{ mA})^{(2)}$ | -2.7% +2% | ±4% | ||
| A.1 | Line negation (see Figure 40) | All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 640 $\Omega$ OUT0 to OUT15, $V_{CC}$ = 3 V to 5.5 $V^{(3)}$ | ±1 | ±4 | %/V | |
| ΔI O(LC3) | Line regulation (see Figure 10) | All output ON, $V_O$ = 1V, $R_{(IREF)}$ = 320 $\Omega$ , OUT0 to OUT15, $V_{CC}$ = 3 V to 5.5 V $^{(3)}$ | ±1 | ±6 | %/V | |
| Δ1 | Load regulation (see | All output ON, $V_O$ = 1 V to 3 V, $R_{(IREF)}$ = 640 $\Omega$ , OUT0 to OUT15 $^{(4)}$ | ±2 | ±6 | %/V | |
| $\Delta I_{O(LC4)}$ | Figure 10) | All output ON, $V_O = 1$ V to 3 V, $R_{(IREF)} = 320 \Omega$ , OUT0 to OUT15 (4) | ±2 | ±8 | %/V | |
| T (TEF) | Thermal error flag threshold | Junction temperature (5) | 150 | 170 | °C | |
| V (LED) | LED open detection threshold | 0.3 | 0.4 | ٧ | ||
| V (IREF) | Reference voltage output | $R_{(IREF)} = 640 \Omega$ | 1.20 | 1.24 | 1.28 | V |
(1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Test Parameter Equations.
(2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Test Parameter Equations. The ideal current is calculated by Equation 3 in Test Parameter Equations.
(3) The line regulation is calculated by Equation 4 in Test Parameter Equations.
(4) The load regulation is calculated by Equation 5 in Test Parameter Equations.
(5) Not tested. Specified by design
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