TDA7313N

Part: TDA7313N — STMicroelectronics

Type: Digital Controlled Stereo Audio Processor

Description: A digital controlled stereo audio processor with 3 stereo inputs, selectable input gain, loudness function, volume control in 1.25dB steps, bass and treble control, and four independent speaker attenuators, all programmable via serial I2C bus.

Operating Conditions:

• Supply voltage: 6–10 V
• Operating temperature: -40 to 85 °C
• Max input signal handling: 2 Vrms

Absolute Maximum Ratings:

• Max supply voltage: 10.2 V
• Max junction/storage temperature: +150 °C

Key Specs:

• Supply Current (I_S): 8 mA (Typ) at V_S = 9V
• Total Harmonic Distortion (THD): 0.01 % (Typ) at V = 1Vrms, f = 1KHz
• Signal to Noise Ratio (S/N): 106 dB (Typ)
• Channel Separation (S_C): 103 dB (Typ) at f = 1KHz
• Volume Control Step Resolution: 1.25 dB (Typ)
• Bass and Treble Control Range: ±14 dB (Typ)
• Input Gain Step Resolution: 3.75 dB (Typ)
• Mute Attenuation: 100 dB (Typ)

Features:

• 3 stereo inputs with selectable input gain
• Loudness function
• Volume control in 1.25dB steps
• Treble and Bass control
• Four independent speaker attenuators for balance and fader facilities
• Independent mute function
• All functions programmable via serial I2C bus

Applications:

• Car radio systems
• Hi-Fi systems

Package:

• SO28
• DIP28

Symbol	Parameter	Test Condition	Min.	Typ.	Max.	Unit
AUDIO OUTPUTS	AUDIO OUTPUTS	AUDIO OUTPUTS	AUDIO OUTPUTS	AUDIO OUTPUTS	AUDIO OUTPUTS	AUDIO OUTPUTS
V OCL	Clipping Level	d = 0.3%	2	2.5		Vrms
R L	Output Load Resistance		2			K W
C L	Output Load Capacitance				10	nF
R OUT	Output resistance		30	75	120	W
V OUT	DC Voltage Level		4.2	4.5	4.8	V
GENERAL	GENERAL	GENERAL	GENERAL	GENERAL	GENERAL	GENERAL
e NO	Output Noise	BW = 20-20KHz, flat output muted all gains = 0dB		2.5 5	15	m V m V
e NO		A curve all gains = 0dB		3	15	m V
S/N	Signal to Noise Ratio	all gains = 0dB; V O = 1Vrms		106		dB
d	Distortion	A V = 0, V IN = 1Vrms A V = -20dB V IN = 1Vrms V IN = 0.3Vrms	Product(s)	0.01 0.09 0.04	0.1 0.3	% % %
Sc	Channel Separation left/right		80	103		dB
	Total Tracking error	A V = 0 to -20dB -20 to -60 dB		0 0	1 2	dB dB
Product(s) Product(s) BUS INPUTS Obsolete	Product(s) Product(s) BUS INPUTS Obsolete	Product(s) Product(s) BUS INPUTS Obsolete	Product(s) Product(s) BUS INPUTS Obsolete	Product(s) Product(s) BUS INPUTS Obsolete	Product(s) Product(s) BUS INPUTS Obsolete	Product(s) Product(s) BUS INPUTS Obsolete
V IL	Input Low Voltage				1	V
V IH	Input High Voltage	-	3			V
I IN	Input Current		-5		+5	m A
V O	Output Voltage SDA Acknowledge	I O = 1.6mA			0.4	V

Obsolete Product(s) - Obsolete Product(s) BUS INPUTS Notes: (1) Bass and Treble response see attached diagram (fig.16). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network (2) The selected input is grounded thru the 2.2 m F capacitor. Figure 2: Loudness vs. Frequency (CLOUD = 100nF) vs. Volume Attenuation Figure 1: Loudness vs. Volume Attenuation Obsolete Product(s) - Obsolete Product(s)

Figure 3: Loudness vs. External Capacitors

Figure 4: Noise vs. Volume/Gain Settings

Obsolete Product(s) - Obsolete Product(s) Figure 6: Distortion & Noise vs. Frequency Figure 7: Distortion & Noise vs. Frequency Figure 8: Distortion vs. Load Resistance Figure 5: Signal to Noise Ratio vs. Volume Setting Obsolete Product(s) - Obsolete Product(s)

6/14

Figure 9: Channel Separation (L fi R) vs. Frequency

Figure 10: Input Separation (L1 fi L2, L3, L4) vs. Frequency

Obsolete Product(s) - Obsolete Product(s) Figure 12: Output Clipping Level vs. Supply Voltage Figure 14: Supply Current vs. Temperature Figure 13: Quiescent Current vs. Supply Voltage Figure 11: Supply Voltage Rejection vs. Frequency Obsolete Product(s) - Obsolete Product(s)

Figure 15: Bass Resistance vs. Temperature

Figure 16: Typical Tone Response (with the ext. components indicated in the test circuit)

Obsolete Product(s) - Obsolete Product(s) I 2 C BUS INTERFACE Data transmission from microprocessor to the TDA7313N and viceversa takes place thru the 2 wires I 2 C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 17, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.18 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master ( m P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 19). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the m P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 17: Data Validity on the I 2 CBUS Obsolete Product(s) - Obsolete Product(s)

Figure 18: Timing Diagram of I 2 CBUS

Figure 19: Acknowledge on the I 2 CBUS

MSB							LSB	FUNCTION
0	0	B2	B1	B0	A2	A1	A0	Volume control
1	1	0	B1	B0	A2	A1	A0	Speaker ATT LR
1	1	1	B1	B0	A2	A1	A0	Speaker ATT RR
1	0	0	B1	B0	A2	A1	A0	Speaker ATT LF
1	0	1	B1	B0	A2	A1	A0	Speaker ATT RF
0	1	0	G1	G0	S2	S1	S0	Audio switch
0	1	1	0	C3	C2	C1	C0	Bass control
0	1	1	1	C3	C2	C1	C0	Treble control

Obsolete Product(s) - Obsolete Product(s) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7313N address (the 8th bit of the byte must be 0). The TDA7313N must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) Data Transferred (N-bytes + Acknowledge) MAX CLOCK SPEED 100kbits/s SOFTWARE SPECIFICATION Chip address DATA BYTES Obsolete Product(s) - Obsolete Product(s)

Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 3.75dB steps