STM32MP135FAF7

Part: STM32MP135FAF7 (STM32MP135C/F family) — STMicroelectronics

Type: Arm Cortex-A7 microprocessor (MPU)

Description: 32-bit Arm Cortex-A7 MPU at up to 1 GHz (STM32MP135F) with DDR3/DDR3L/LPDDR2/LPDDR3 interface, 168 Kbytes internal SRAM, LCD-TFT controller, 2× Gigabit Ethernet, 2× CAN FD, 2× ADC and 24 timers.

Operating Conditions:

• I/O supply voltage VDD: 1.71–3.6 V (1.71–2.7 V when SYSCFG_HSLVENxR ≠ 0)
• Core supply VDDCORE: 1.21–1.29 V in Run mode
• Cortex-A7 supply VDDCPU: 1.21–1.38 V in Run mode (up to 650 MHz); 1.32–1.38 V in Run Overdrive mode (above 650 MHz)
• Cortex-A7 max frequency: 1000 MHz (STM32MP135F), 650 MHz (STM32MP135C)

Absolute Maximum Ratings:

• Max external main supply voltage (VDDX − VSSX): 3.9 V
• Max VDDCORE and VDDCPU: 1.5 V
• Max DDR IO supply voltage (VDDA_DDR): 1.98 V
• Total current into all VDD lines: 440 mA
• Max current into each VDD pin: 100 mA
• Max output current sunk by any I/O or control pin: 20 mA

Key Specs:

• Cortex-A7 subsystem clock: up to 1000 MHz (STM32MP135F)
• AXI/AHB5/AHB6 clock: up to 266.5 MHz; AHB: up to 209 MHz
• VDDQ_DDR: 1.425–1.575 V (DDR3), 1.283–1.45 V (DDR3L), 1.14–1.3 V (LPDDR2/LPDDR3)
• VDDA (ADC with VREF > 2 V): 2–3.6 V
• VBAT: 1.6–3.6 V
• VDD3V3_USBHS: 3.07–3.6 V when USB HS is used
• Injected current on FT_xxx, TT_xx and NRST pins: −5/+0 mA
• Total output current sunk or sourced by all I/Os: 140 mA each

Features:

• Cortex-A7 with 32 KB I / 32 KB D L1 cache, 128 KB L2 cache, NEON and TrustZone
• External DDR up to 1 Gbyte: LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066, 16-bit
• 168 KB internal SRAM plus 8 KB backup SRAM
• Dual Quad-SPI and flexible memory controller (FMC)
• Up to 135 secure I/O ports
• 2× Ethernet MAC/GMAC with IEEE 1588v2, 2× CAN FD, 2× USB 2.0 HS
• 5× I2C, 4× USART + 4× UART, 5× SPI, 2× SAI, 2× SDMMC
• 2× 12-bit ADC up to 5 Msps
• LCD-TFT controller up to 24-bit RGB888, WXGA at 60 fps
• Camera interface up to 5 Mpix at 15 fps
• Crypto and security: AES, DES/TDES, PKA, HASH, TRNG, secure boot, 12 tamper pins
• Low-power modes: Sleep, Stop, LPLV-Stop, LPLV-Stop2, Standby
• 4 DMA controllers with 56 channels in total
• ECOPACK2 compliant

Applications:

• Industrial and embedded systems with HMI displays
• Secure connected gateways

Package:

• LFBGA289
• TFBGA289
• TFBGA320

• ARMv7-A architecture
• 32-Kbyte L1 instruction cache
• 32-Kbyte L1 data cache
• 128-Kbyte level2 cache
• Arm + Thumb ® -2 instruction set
• Arm TrustZone security technology
• Arm NEON advanced SIMD
• DSP and SIMD extensions
• VFPv4 floating-point
• Hardware virtualization support
• Embedded trace module (ETM)
• Integrated generic interrupt controller (GIC) with 160 shared peripheral interrupts
• Integrated generic timer (CNT)

Unless otherwise specified, the parameters given in Table 79 , Table 80 and Table 81 are derived from tests performed under the ambient temperature and V DDA supply voltage conditions summarized in Table 13: General operating conditions . In Table 79 , Table 80 and Table 81 , f ADC refers to f adc_ker_ck .

Note: When both ADCs are used, the kernel clock should be the same for both ADCs and the embedded ADC prescalers cannot be used.

Table 79. 12-bit ADC characteristics (1)(2)

Table 79. 12-bit ADC characteristics (1)(2)

Table 79. 12-bit ADC characteristics (1)(2) (continued)

Table 79. 12-bit ADC characteristics (1)(2) (continued)

177/224

Table 79. 12-bit ADC characteristics (1)(2) (continued)

Table 79. 12-bit ADC characteristics (1)(2) (continued)

1. The voltage booster on ADC switches must be used for V DDA < 2.4 V (embedded I/O switches).
2. The conversion of the first element in the group is excluded.
3. f ADC value corresponds to the maximum frequency that can be reached considering a 2.5 sampling period. For other SMPy sampling periods, the maximum frequency is f ADC value * SMPy / 2.5 with a limitation to 75 MHz.
4. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. It is otherwise specified.
5. The sampling time can vary depending on the condition with ±0.5 clock cycles. Resulting in minimum of 2.0 cycles and maximum of 641 cycles. Refer to the detailed description in the reference manual.

Table 80. Minimum sampling time vs R AIN (12-bit ADC) (1)(2)

• Resolution RAIN ( Ω ) Minimum sampling time (s) - Fast channels (3) Minimum sampling time (s) - Slow channels (4)
• 47 3.75E-08 6.12E-08
• 68 3.94E-08 6.25E-08
• 100 4.36E-08 6.51E-08
• 150 5.11E-08 7.00E-08
• 220 6.54E-08 7.86E-08
• 330 8.80E-08 9.57E-08
• 470 1.17E-07 1.23E-07
• 680 1.60E-07 1.65E-07
• 47 3.19E-08 5.17E-08
• 68 3.35E-08 5.28E-08
• 100 3.66E-08 5.45E-08
• 150 4.35E-08 5.83E-08
• 220 5.43E-08 6.50E-08
• 330 7.18E-08 7.89E-08
• 470 9.46E-08 1.00E-07
• 680 1.28E-07 1.33E-07
• 1000 1.81E-07 1.83E-07
• 1500 2.63E-07 2.63E-07
• 2200 3.79E-07 3.76E-07
• 3300 5.57E-07 5.52E-07
• 47 2.64E-08 4.17E-08
• 68 2.76E-08 4.24E-08
• 100 3.02E-08 4.39E-08
• 150 3.51E-08 4.66E-08
• 220 4.27E-08 5.13E-08
• 330 5.52E-08 6.19E-08
• 470 7.17E-08 7.72E-08
• 680 9.68E-08 1.00E-07
• 1000 1.34E-07 1.37E-07
• 1500 1.93E-07 1.94E-07
• 2200 2.76E-07 2.74E-07
• 3300 4.06E-07 4.01E-07
• 4700 5.73E-07 5.62E-07

210

Table 80. Minimum sampling time vs R AIN (12-bit ADC) (1)(2) (continued)

1. Specified by design, not tested in production.
2. Data valid up to 130 °C, with a 22 pF PCB capacitor and V DDA = 1.62 V.
3. Fast channels correspond to ADCx_INx[0:5].
4. Slow channels correspond to all ADC inputs except for the Fast channels.

Table 81. 12-bit ADC accuracy (1)(2)

210

Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics , Table 11: Current characteristics , and Table 12: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 10. Voltage characteristics (1)

Table 10. Voltage characteristics (1)

Table 10. Voltage characteristics (continued) (1)

1. All power (V DD , V DDSD1 , V DDSD2 , V DDA , V DD3V3_USBHS , V DDCORE , V DDCPU , V BAT ) and ground (V SS , V SSA , VSSX ) pins must always be connected to the external/internal power supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 53 for the maximum allowed injected current values.

3. Min(6.0, V DD +3.9, V DDA +3.9, V DD3V3_USBHS +3.9, V BAT +3.9).

4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. To sustain a voltage higher than 3.9 V the internal pull-up/pull-down resistors must be disabled.

5. Min(6.0, V DD +3.9, V DD3V3_USBHS +3.9). It is recommended to not use OTG_VBUS pin but rather any GPIO with an EXTI and external pull-up resistance in case the STM32MP13x device can be used with V DD off while plugging OTG_VBUS > 3.9 V (see AN4879: USB hardware and PCB guidelines using STM32 MCUs for details).

6. Min(5.25, V DD +3.9, V DD3V3_USBHS +3.9). It is recommended to not use OTG_VBUS pin but rather any GPIO with an EXTI and external pull-up resistance in case the STM32MP13x device can be used with V DD off while plugging OTG_VBUS > 3.9 V (see AN4879: USB hardware and PCB guidelines using STM32 MCUs for details).

7. All power (V DD , V DDSD1 , V DDSD2 , V DDA , V DD3V3_USBHS ) and ground (V SS , V SSA , V SSX ) pins must always be connected to the external/internal power supply, in the permitted range.

8. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins.

9. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

Table 11. Current characteristics (1)

210

1. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer also to Table 10: Voltage characteristics for the maximum allowed input voltage values.
2. When several inputs are submitted to a current injection, the maximum ∑ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 12. Thermal characteristics

Package thermal characteristics in Table 118 are specified with conditions as per JEDEC JESD51-6, JESD51-8, JESD51-9, and JESD51-12. These typical values will vary in function of board thermal characteristics and other components on the board.

Θ JA :

Thermal resistance junction-ambient.

Θ JB :

Thermal resistance junction-board.

Θ JC :

Thermal resistance junction-top-case.

Θ jb:

Thermal parameter junction-board.

Ψ jt:

Thermal parameter junction-top-case.

Motherboard type: four layers, JEDEC 2S2P

Table 118. Thermal characteristics

1. Per JEDEC JESD51-9
2. Per JEDEC JESD51-8
3. Per JEDEC JESD51-12 best practice guidelines
4. Per JEDEC JESD51-12.
5. Per JEDEC JESD51-12.

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

No explicit ordering variant list (e.g., STM32MP135FAF7) is provided in the supplied section. The section only contains the ordering scheme reference (Table 119: STM32MP135C/F ordering information scheme), a note that no character indicates tray or tube packing, a footnote referring to application note AN5438 for lifetime estimates, and a contact note for available options.