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STM32MP135DAG

Dual Cortex-A7 + Cortex-M4 MPU

The STM32MP135DAG is a dual cortex-a7 + cortex-m4 mpu from STMicroelectronics. View the full STM32MP135DAG datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

STM32MP135DAG shares its datasheet with STM32MP135DAF7, whose page lists every part number it covers.

Official STM32MP135DAG datasheet (PDF) — the source this page was extracted from.

Manufacturer

STMicroelectronics

Category

Dual Cortex-A7 + Cortex-M4 MPU

STM32MP135DAG Key Specifications

ParameterValue
Additional InterfacesCANbus, GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART
Case/PackageTFBGA
China RoHSCompliant
Co-Processors/DSPMultimedia; NEON™ MPE
Core ArchitectureRISC
Core ProcessorARM® Cortex®-A7
Display & Interface ControllersLCD
Ethernet10/100/1000Mbps (2)
Graphics AccelerationYes
Height - Seated (Max)1.2 mm
Introduction Date2023-03-03
Length11 mm
Lifecycle StatusProduction (Last Updated: 2 weeks ago)
Max Frequency1 GHz
Max Operating Temperature105 °C
Max Supply Current268 mA
Max Supply Voltage1.38 V
Min Operating Temperature-40 °C
Min Supply Voltage1.32 V
Mounting TypeSurface Mount
Nominal Supply Voltage (DC)1.35 V
Number of Cores/Bus Width1 Core, 32-Bit
Number of I/Os10
Number of Pins320
Number of Terminals320
Operating Temperature-40°C ~ 105°C (TJ)
Package / Case320-TFBGA
PackagingTray
RAM ControllersDDR3, DDR3L, LPDDR2, LPDDR3
REACH SVHCUnaffected
RoHSCompliant
Security FeaturesAES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
Clock Speed1GHz
Standard Pack Qty960
Supplier Device Package320-TFBGA (11x11)
Terminal Pitch500 µm
USBUSB 2.0 (2)
Voltage - I/O1.8V, 2.5V, 3.3V
Width11 mm

STM32MP135DAG Overview

Part: STM32MP135DAF7 — STMicroelectronics (STM32MP135A/D family)

Type: Arm Cortex-A7 Microprocessor (MPU)

Description: 32-bit Arm Cortex-A7 MPU running at up to 1 GHz (STM32MP135D) with 2× Gigabit Ethernet, 2× CAN FD, 2× 12-bit ADC (up to 5 Msps), LCD-TFT controller, camera interface and DDR3/DDR3L/LPDDR2/LPDDR3 support.

Operating Conditions:

  • Supply voltage: VDD 1.71–3.6 V (I/Os and embedded regulators; max 2.7 V when SYSCFG_HSLVENxR ≠ 0)
  • Operating temperature (junction, suffix 7): -40 to +105 °C
  • Cortex-A7 subsystem clock: up to 1000 MHz (STM32MP135D); VDDCPU 1.32–1.38 V in Run Overdrive mode (above 650 MHz)
  • VDDCORE: 1.21–1.29 V in Run mode

Absolute Maximum Ratings:

  • Max external main supply voltage (VDDX − VSSX): 3.9 V
  • VDDCORE: 1.5 V; VDDCPU: 1.5 V; VDDA_DDR: 1.98 V
  • Total current into all VDD lines: 440 mA; per VDD/VSS pin: 100 mA
  • Output current sunk by any I/O: 20 mA
  • Storage temperature: -65 to +150 °C
  • Max junction temperature: 105 °C (suffix 7), 125 °C (suffix 3)

Key Specs:

  • Cortex-A7 subsystem clock: 0–1000 MHz (STM32MP135D), 0–650 MHz (STM32MP135A)
  • AXI/AHB5/AHB6 clock: up to 266.5 MHz; AHB clock: up to 209 MHz
  • VDD (I/O and regulators): 1.71–3.6 V; 2.25 V minimum when REG1V8 is used (BYPASS_REG1V8 = 0)
  • VDDA (analog): 2–3.6 V with ADC VREF > 2 V; 1.62–2.15 V with VREF < 2 V
  • VBAT: 1.6–3.6 V
  • VDD3V3_USBHS: 3.07–3.6 V when USB is used
  • VDDQ_DDR: 1.425–1.575 V (DDR3), 1.283–1.45 V (DDR3L), 1.14–1.3 V (LPDDR2/LPDDR3)
  • Junction temperature: -40 to +105 °C (suffix 7)

Features:

  • 32-bit Arm Cortex-A7 with 32 KB I / 32 KB D L1 cache, 128 KB L2 cache, NEON and TrustZone
  • External DDR up to 1 GB (LPDDR2/LPDDR3-1066, DDR3/DDR3L-1066, 16-bit)
  • 168 KB internal SRAM plus 8 KB backup SRAM
  • Dual Quad-SPI and flexible memory controller (FMC) with SLC NAND support
  • 2× Ethernet MAC/GMAC (IEEE 1588v2; MII/RMII/RGMII)
  • 2× CAN FD, 2× USB 2.0 high-speed, 5× I2C, 4× UART + 4× USART, 5× SPI, 2× SAI, SPDIF Rx, 2× SDMMC
  • 2× 12-bit ADC up to 5 Msps, DFSDM, temperature sensor
  • LCD-TFT controller up to 24-bit RGB888 (WXGA @60 fps or Full HD @30 fps)
  • 8- to 16-bit camera interface
  • Up to 24 timers, 2 watchdogs, secure RTC
  • Security features: ECDSA verification, HASH (SHA-1/2/3), HMAC, TRNG, 12 tamper pins
  • 4 DMA controllers (56 channels)
  • Low-power modes: Sleep, Stop, LPLV-Stop, LPLV-Stop2, Standby
  • Controls for PMIC companion chip
  • ECOPACK2 compliant

Applications:

  • Industrial and embedded HMI
  • Networked and secure edge devices (dual Ethernet, CAN FD)

Package:

  • LFBGA289
  • TFBGA289
  • TFBGA320

STM32MP135DAG Features

  • ARMv7-A architecture
  • 32-Kbyte L1 instruction cache
  • 32-Kbyte L1 data cache
  • 128-Kbyte level2 cache
  • Arm + Thumb ® -2 instruction set
  • Arm TrustZone security technology
  • Arm NEON advanced SIMD
  • DSP and SIMD extensions
  • VFPv4 floating-point
  • Hardware virtualization support
  • Embedded trace module (ETM)
  • Integrated generic interrupt controller (GIC) with 160 shared peripheral interrupts
  • Integrated generic timer (CNT)

STM32MP135DAG Pin Configuration

Figure 5. STM32MP135A/D LFBGA289 ballout

The above figure shows the package top view.

99

Figure 6. STM32MP135A/D TFBGA289 ballout

The above figure shows the package top view.

Figure 7. STM32MP135A/D TFBGA320 ballout

The above figure shows the package top view.

99

Table 6. Legend/abbreviations used in the pinout table

NameAbbreviationDefinition
Pin nameUnless otherwise specified, the pin function during and after reset is the same as the actual pin nameUnless otherwise specified, the pin function during and after reset is the same as the actual pin name
Pin typeSSupply pin
Pin typeIInput only pin
Pin typeOOutput only pin
Pin typeI/OInput/output pin
Pin typeAAnalog or special level pin
I/O structureFT(U/D/PD)5 V tolerant I/O (with fixed pull-up / pull-down / programmable pull-down)
I/O structureDDR1.5 V, 1.35 V or 1.2 V I/O for DDR3, DDR3L, LPDDR2/LPDDR3 interface
I/O structureAAnalog signal
I/O structureRSTReset pin with weak pull-up resistor
I/O structureOption for FT I/OsOption for FT I/Os
I/O structure_f (1)I2C FM+ option
I/O structure_a (2)Analog option (supplied by VDDAfor the analog part of the I/O)
I/O structure_u (3)USB option (supplied by VDD3V3_USBxx for the USB part of the I/O)
I/O structure_h (4)High-speed output for 1.8V typ. VDD (for SPI, SDMMC, QUADSPI, TRACE)
I/O structure_vh (5)Very-high-speed option for 1.8V typ. VDD (for ETH, SPI, SDMMC, QUADSPI, TRACE)
NotesUnless otherwise specified by a note, all I/Os are set as floating inputs during and after resetUnless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functionsFunctions selected through GPIOx_AFR registersFunctions selected through GPIOx_AFR registers
Additional functionsFunctions directly selected/enabled through peripheral registersFunctions directly selected/enabled through peripheral registers
  1. The related I/O structures in Table 7 are: FT_f, FT_fh, FT_fvh
  2. The related I/O structures in Table 7 are: FT_a, FT_ha, FT_vha
  3. The related I/O structures in Table 7 are: FT_u
  4. The related I/O structures in Table 7 are: FT_h, FT_fh, FT_fvh, FT_vh, FT_ha, FT_vha
  5. The related I/O structures in Table 7 are: FT_vh, FT_vha, FT_fvh

Table 7. STM32MP135A/D ball definitions

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
K10F6U14VDDCORES----
A2D2A2PA9I/OFT_h-TIM1_CH2, I2C3_SMBA, DFSDM1_DATIN0, USART1_TX, UART4_TX, FMC_NWAIT(boot), DCMIPP_D0, LCD_R6-
A1A1T5VSSS----
M6F3U7VDDS----
D4E4B2PE11I/OFT_vh-TIM1_CH2, USART2_CTS/USART2_NSS, SAI1_D2, SPI4_MOSI/I2S4_SDO, SAI1_FS_A, USART6_CK, LCD_R0, ETH2_MII_TX_ER, ETH1_MII_TX_ER, FMC_D8(boot)/FMC_AD8, DCMIPP_D10, LCD_R5-
B2D1B3PF5I/OFT_h-TRACED12,DFSDM1_CKIN0, I2C1_SMBA, LCD_G0, FMC_A5, DCMIPP_D11, LCD_R5-
B1G6C2PD3I/OFT_f-TIM2_CH1, USART2_CTS/USART2_NSS, DFSDM1_CKOUT,I2C1_SDA, SAI1_D3, FMC_CLK, DCMIPP_D5-
C3E2C3PE14I/OFT_h-TIM1_BKIN, SAI1_D4, UART8_RTS/UART8_DE, QUADSPI_BK1_NCS, QUADSPI_BK2_IO2, FMC_D11(boot)/FMC_AD11, DCMIPP_D7, LCD_G0TAMP_IN6
F6D4E7VDDCPUS----
E4E1B1PD0I/OFT-SAI1_MCLK_A, SAI1_CK1, FDCAN1_RX, FMC_D2(boot)/FMC_AD2, DCMIPP_D1-
C2G7D3PH12I/OFT_fh-USART2_TX, TIM5_CH3, DFSDM1_CKIN1, I2C3_SCL, SPI5_MOSI, SAI1_SCK_A, QUADSPI_BK2_IO2, SAI1_CK2, ETH1_MII_CRS, FMC_A6, DCMIPP_D3-

Table 7. STM32MP135A/D ball definitions

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
C1G3C1PB6I/OFT_h-TRACED6, TIM16_CH1N, TIM4_CH1, TIM8_CH1, USART1_TX, SAI1_CK2, LCD_B6, QUADSPI_BK1_NCS, ETH2_MDIO, FMC_NE3, DCMIPP_D5, LCD_B7, HDP6-
A17A17T17VSSS----
M7-J13VDDS----
D2G9D2PD6I/OFT-TIM16_CH1N, SAI1_D1, SAI1_SD_A, UART4_TX(boot), DCMIPP_D4, DCMIPP_D0-
F5F1E3PH8I/OFT_fh-TRACED9, TIM5_ETR, USART2_RX, I2C3_SDA, LCD_R6, FMC_A8, DCMIPP_HSYNC, LCD_R2, HDP2-
D1G4D1PB8I/OFT_f-TIM16_CH1, TIM4_CH3, I2C1_SCL, I2C3_SCL, DFSDM1_DATIN1, UART4_RX, SAI1_D1, FMC_D13(boot)/FMC_AD13, DCMIPP_D6-
E3F2F4PA12I/OFT_h-TIM1_ETR, SAI2_MCLK_A, USART1_RTS/USART1_DE, ETH2_MII_RX_DV/ETH2_ RGMII_RX_CTL/ETH2_RMII_ CRS_DV, FMC_A7, DCMIPP_D1, LCD_G6-
F8D6E10VDDCPUS----
F4G2E2PH2I/OFT_h-LPTIM1_IN2, DCMIPP_D9, LCD_G1, UART7_TX, QUADSPI_BK2_IO0(boot), ETH2_MII_CRS, ETH1_MII_CRS, FMC_NE4, ETH2_RGMII_CLK125, LCD_B0-
C8B8T21VSSS----

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
E2G1F3PD11I/OFT_h-LPTIM2_IN2, I2C4_SMBA, USART3_CTS/USART3_NSS, SPDIFRX_IN0, QUADSPI_BK1_IO2, ETH2_RGMII_CLK125, LCD_R7, FMC_CLE(boot)/FMC_A16, UART7_RX, DCMIPP_D4-
E1G5F2PG9I/OFT_f-DBTRGO, I2C2_SDA, USART6_RX, SPDIFRX_IN3, FDCAN1_RX, FMC_NE2, FMC_NCE(boot), DCMIPP_VSYNC-
G5H3F1PF8I/OFT_h-TIM16_CH1N, TIM4_CH3, TIM8_CH3, SAI1_SCK_B, USART6_TX, TIM13_CH1, QUADSPI_BK1_IO0(boot), DCMIPP_D15, LCD_B3WKUP1
M8-M5VDDS----
F3J3H5PG8I/OFT_h-TIM2_CH1, TIM8_ETR, SPI5_MISO, SAI1_MCLK_B, LCD_B1, USART3_RTS/USART3_DE, SPDIFRX_IN2, QUADSPI_BK2_IO2, QUADSPI_BK1_IO3, FMC_NE2, ETH2_CLK, DCMIPP_D6TAMP_IN4
F9D8G5VDDCPUS----
F2H1G3PG5I/OFT_h-TIM17_CH1, ETH2_MDC, LCD_G4, FMC_A15, DCMIPP_VSYNC, DCMIPP_D3-
G4G8H4PG15I/OFT_h-USART6_CTS/USART6_NSS, UART7_CTS, QUADSPI_BK1_IO1, ETH2_PHY_INTN, LCD_B4, DCMIPP_D10, LCD_B3-
F1H2G2PG10I/OFT_h-SPI5_SCK, SAI1_SD_B, UART8_CTS, FDCAN1_TX, QUADSPI_BK2_IO1(boot), FMC_NE3, DCMIPP_D2-
D3B14U5VSSS----

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
G3K2H3PF10I/OFT_h-TIM16_BKIN, SAI1_D3, TIM8_BKIN, SPI5_NSS, USART6_RTS/USART6_DE, UART7_RTS/UART7_DE, QUADSPI_CLK(boot), DCMIPP_HSYNC, LCD_B5TAMP_IN1
H8F10-VDDCORES----
G2L1G1PF6I/OFT_vh-TIM16_CH1, SPI5_NSS, UART7_RX(boot), QUADSPI_BK1_IO2, ETH2_MII_TX_EN/ETH2_ RGMII_TX_CTL/ETH2_RMII_ TX_EN, LCD_R7, LCD_G4-
D12C5U6VSSS----
M9K4N7VDDS----
G1H9J5PF9I/OFT_h-TIM17_CH1N, TIM1_CH1, DFSDM1_CKIN3, SAI1_D4, UART7_CTS, UART8_RX, TIM14_CH1, QUADSPI_BK1_IO1(boot), QUADSPI_BK2_IO3, FMC_A9, LCD_B6-
H5K1H2PE4I/OFT_h-SPI5_MISO, SAI1_D2, DFSDM1_DATIN3, TIM15_CH1N, I2S_CKIN, SAI1_FS_A, UART7_RTS/UART7_DE, UART8_TX, QUADSPI_BK2_NCS, FMC_NCE2, FMC_A25, DCMIPP_D3, LCD_G7-
H6E5G7VDDCPUS----
H4K3J3PB2I/OFT_h-RTC_OUT2, SAI1_D1, I2S_CKIN, SAI1_SD_A, UART4_RX, QUADSPI_BK1_NCS(boot), ETH2_MDIO, FMC_A6, LCD_B4TAMP_IN7
E5D13U11VSSS----

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
H3L3J1PH7I/OFT_fh-SAI2_FS_B, I2C3_SDA, SPI5_SCK, QUADSPI_BK2_IO3, ETH2_MII_TX_CLK, ETH1_MII_TX_CLK, QUADSPI_BK1_IO3, LCD_B2-
H1H7K3PH11I/OFT_fh-SPI5_NSS, TIM5_CH2, SAI2_SD_A, SPI2_NSS/I2S2_WS, I2C4_SCL, USART6_RX, QUADSPI_BK2_IO0, ETH2_MII_RX_CLK/ETH2_ RGMII_RX_CLK/ETH2_RMII_ REF_CLK, FMC_A12, LCD_G6-
J1N1J2PD13I/OFT_h-LPTIM2_ETR, TIM4_CH2, TIM8_CH2, SAI1_CK1, SAI1_MCLK_A, USART1_RX, QUADSPI_BK1_IO3, QUADSPI_BK2_IO2, FMC_A18, LCD_G4-
J5J1K2VDD_PLLS----
J4J2K1VSS_PLLS----
H2H8L4PI3I/OFT(1)SPDIFRX_IN3, ETH1_MII_RX_ERTAMP_IN4/TAMP_ OUT5, WKUP2
K4M3M3PC13I/OFT(1)-RTC_OUT1/RTC_TS/ RTC_LSCO, TAMP_IN1/TAMP_ OUT2, WKUP3
J3J4N5PI2I/OFT(1)SPDIFRX_IN2TAMP_IN3/TAMP_ OUT4, WKUP5
K5N4P4PI1I/OFT(1)SPDIFRX_IN1RTC_OUT2/RTC_ LSCO, TAMP_IN2/TAMP_ OUT3, WKUP4
F13L2U13VSSS----
J2J5L2VBATS----
L4N3P5PI0I/OFT(1)SPDIFRX_IN0TAMP_IN8/TAMP_ OUT1
K2M2L3PC15- OSC32_OUTI/OFT(1)-OSC32_OUT

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
F15N2U16VSSS----
K1M1M2PC14- OSC32_INI/OFT(1)-OSC32_IN
G7E3V16VSSS----
H9K6N15VDDCORES----
M10M4N9VDDS----
G8E6W16VSSS----
L2P3N2PF4I/OFT_h-USART2_RX, ETH2_MII_RXD0/ETH2_ RGMII_RXD0/ETH2_RMII_ RXD0, FMC_A4, DCMIPP_D4, LCD_B6-
M2J8P2PA8I/OFT_fh-MCO1, SAI2_MCLK_A, TIM8_BKIN2, I2C4_SDA, SPI5_MISO, SAI2_CK1, USART1_CK, SPI2_MOSI/I2S2_SDO, OTG_HS_SOF, ETH2_MII_RXD3/ETH2_ RGMII_RXD3, FMC_A21, LCD_B7-
L1T1N1PE2I/OFT_fh-TRACECLK, TIM2_ETR, I2C4_SCL, SPI5_MOSI, SAI1_FS_B, USART6_RTS/USART6_DE, SPDIFRX_IN1, ETH2_MII_RXD1/ETH2_ RGMII_RXD1/ETH2_RMII_ RXD1, FMC_A23, LCD_R1-
M1J7P3PF7I/OFT_vh-TIM17_CH1, UART7_TX(boot), UART4_CTS, ETH1_RGMII_CLK125, ETH2_MII_TXD0/ETH2_ RGMII_TXD0/ETH2_RMII_ TXD0, FMC_A18, LCD_G2-
M3R1R2PG11I/OFT_vh-SAI2_D3, I2S2_MCK, USART3_TX, UART4_TX, ETH2_MII_TXD1/ETH2_ RGMII_TXD1/ETH2_RMII_ TXD1, FMC_A24, DCMIPP_D14, LCD_B2-

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
L3J6N3PH6I/OFT_fh-TIM12_CH1, USART2_CK, I2C5_SDA, SPI2_SCK/I2S2_CK, QUADSPI_BK1_IO2, ETH1_PHY_INTN, ETH1_MII_RX_ER, ETH2_MII_RXD2/ETH2_ RGMII_RXD2, QUADSPI_BK1_NCS-
N2P4R1PG1I/OFT_vh-LPTIM1_ETR, TIM4_ETR, SAI2_FS_A, I2C2_SMBA, SPI2_MISO/I2S2_SDI, SAI2_D2, FDCAN2_TX, ETH2_MII_TXD2/ETH2_ RGMII_TXD2, FMC_NBL0, LCD_G7-
M11-N12VDDS----
N1R2T2PE6I/OFT_vh-MCO2, TIM1_BKIN2, SAI2_SCK_B, TIM15_CH2, I2C3_SMBA, SAI1_SCK_B, UART4_RTS/UART4_DE, ETH2_MII_TXD3/ETH2_ RGMII_TXD3, FMC_A22, DCMIPP_D7, LCD_G3-
P1P1T3PH0-OSC_INI/OFT--OSC_IN
G9U1N11VSSS----
P2P2U2PH1-OSC_OUTI/OFT--OSC_OUT
R2T2R3PH3I/OFT_fh-I2C3_SCL, SPI5_MOSI, QUADSPI_BK2_IO1, ETH1_MII_COL, LCD_R5, ETH2_MII_COL, QUADSPI_BK1_IO0, LCD_B4-
M5L5U3VSS_ANAS----
L5U2W1PG3I/OFT_fvh-TIM8_BKIN2, I2C2_SDA, SAI2_SD_B, FDCAN2_RX, ETH2_RGMII_GTX_CLK, ETH1_MDIO, FMC_A13, DCMIPP_D15, DCMIPP_D12-
M4L4V2VDD_ANAS----
R1U3V3PG2I/OFT-MCO2, TIM8_BKIN, SAI2_MCLK_B, ETH1_MDC, DCMIPP_D1-

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typestructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
T1L6W2PG12I/OFT-LPTIM1_IN1, SAI2_SCK_A, SAI2_CK2, USART6_RTS/USART6_DE, USART3_CTS, ETH2_PHY_INTN, ETH1_PHY_INTN, ETH2_MII_RX_DV/ETH2_ RGMII_RX_CTL/ETH2_RMII_ CRS_DV-
F7P6R5VDDS----
G10E8T1VSSS----
N3R3V1PD7I/OFT_fh-MCO1, USART2_CK, I2C2_SCL, I2C3_SDA, SPDIFRX_IN0, ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_ REF_CLK, QUADSPI_BK1_IO2, FMC_NE1-
P3K7T4PA13I/OFT-DBTRGO, DBTRGI, MCO1, UART4_TXBOOTFAILN
R3R4W3PWR_CPU_ONOFT---
T2N5Y1PA11I/OFT_f-TIM1_CH4, I2C5_SCL, SPI2_NSS/I2S2_WS, USART1_CTS/USART1_NSS, ETH2_MII_RXD1/ETH2_ RGMII_RXD1/ETH2_RMII_ RXD1, ETH1_CLK, ETH2_CLK-
N5M6AA2PB11I/OFT_vh-TIM2_CH4, LPTIM1_OUT, I2C5_SMBA, USART3_RX, ETH1_MII_TX_EN/ETH1_ RGMII_TX_CTL/ETH1_RMII_ TX_EN-
P4U4Y2PF14(JTCK/SW CLK)I/OFT(2)JTCK/SWCLK-
U3L7Y3PA0I/OFT_a-TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SAI1_SD_B, UART5_TX, ETH1_MII_CRS, ETH2_MII_CRSADC1_INP7, ADC1_INN3, ADC2_INP7, ADC2_INN3

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after reset)type - Pinstructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
N6T3W4PF13I/OFT_a-TIM2_ETR, SAI1_MCLK_B, DFSDM1_DATIN3, USART2_TX, UART5_RXADC1_INP11, ADC1_INN10, ADC2_INP11, ADC2_INN10
G11E10P7VSSS----
F10--VDDS----
R4K8AA3PA1I/OFT_a-TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N, DFSDM1_CKIN0, USART2_RTS/USART2_DE, ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_ REF_CLKADC1_INP3, ADC2_INP3
P5R5Y4PA2I/OFT_a-TIM2_CH3, TIM5_CH3, LPTIM4_OUT, TIM15_CH1, USART2_TX, ETH1_MDIOADC1_INP1, ADC2_INP1
U4M7Y5PA5I/OFT_a-TIM2_CH1/TIM2_ETR, USART2_CK, TIM8_CH1N, SAI1_D1, SPI1_NSS/I2S1_WS, SAI1_SD_A,ETH1_PPS_OUT, ETH2_PPS_OUTADC1_INP2
T3T4W5PC0I/OFT_ha-SAI1_SCK_A, SAI1_CK2, I2S1_MCK, SPI1_MOSI/I2S1_SDO, USART1_TXADC1_INP0, ADC1_INN1, ADC2_INP0, ADC2_INN1, TAMP_IN3
T4J9AA4PF12I/OFT_vha-SPI1_NSS/I2S1_WS, SAI1_SD_A, UART4_TX, ETH1_MII_TX_ER, ETH1_RGMII_CLK125ADC1_INP6, ADC1_INN2
R6U6W7VREF+S----
P7U5U8VDDAS----
P6T6V8VREF-S----
N7T5U9VSSAS----

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
U2R6V6PA7I/OFT_ha-TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SAI2_D1, SPI1_SCK/I2S1_CK, USART1_CTS/USART1_NSS, TIM14_CH1, ETH1_MII_RX_DV/ETH1_ RGMII_RX_CTL/ETH1_RMII_ CRS_DV, SAI2_SD_AADC1_INP16
T6L8Y6PF11I/OFT_a-USART2_TX, SAI1_D2, DFSDM1_CKIN3,SAI1_FS_A, ETH2_MII_RX_ERADC1_INP8, ADC1_INN4, ADC2_INP8, ADC2_INN4
U5N7AA6PA4I/OFT_a-TIM5_ETR, USART2_CK, SAI1_SCK_B, SPI1_NSS/I2S1_WS, DFSDM1_CKIN1, ETH1_PPS_OUT, ETH2_PPS_OUT, SAI1_SCK_AADC1_INP14
U6K9Y7PC4I/OFT_a-TIM3_ETR, DFSDM1_CKIN2, SAI1_D3, I2S1_MCK, UART5_RTS/UART5_DE, SPDIFRX_IN2, ETH1_MII_RXD0/ETH1_ RGMII_RXD0/ETH1_RMII_ RXD0, SAI2_D3ADC1_INP4, ADC2_INP4
F11P9-VDDS----
H7E12P15VSSS----
T5P7W6PC3I/OFT_ha-SAI1_CK1,DFSDM1_CKOUT, SPI1_MISO/I2S1_SDI, SPI1_SCK/I2S1_CK, UART5_CTS, SAI1_MCLK_A, ETH1_MII_TX_CLK, ETH2_MII_TX_CLKADC1_INP13, ADC1_INN12, TAMP_IN5
J8M9-VDDCORES----
R7P8AA7PC5I/OFT_a-DFSDM1_DATIN2, SAI2_D4, I2S_CKIN, SAI1_D4, USART2_CTS/USART2_NSS, SPDIFRX_IN3, ETH1_MII_RXD1/ETH1_ RGMII_RXD1/ETH1_RMII_ RXD1ADC1_INP10, ADC2_INP10

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
U7M8W8PB0I/OFT_a-DBTRGI, TIM1_CH2N, TIM3_CH3, TIM8_CH2N, USART1_RX, I2S1_MCK, SAI2_FS_A, USART1_CK, UART4_CTS, SAI2_D2, ETH1_MII_RXD2/ETH1_ RGMII_RXD2ADC1_INP9, ADC1_INN5, ADC2_INP9, ADC2_INN5
N8T7W9PA3I/OFT_ha-TIM2_CH4, TIM5_CH4, LPTIM5_OUT, TIM15_CH2, SPI1_MOSI/I2S1_SDO, SAI1_FS_B, USART2_RX, ETH1_MII_COL, ETH2_MII_COLADC1_INP12, ADC1_INN11, PVD_IN, WKUP6
T7N8Y8PB1I/OFT_ha-TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI1_SCK/I2S1_CK, DFSDM1_DATIN1, UART4_RX, ETH1_MII_RXD3/ETH1_ RGMII_RXD3ADC1_INP5, ADC2_INP5
U8R7Y9PC1I/OFT_vha-DFSDM1_DATIN0, SAI1_D3, ETH1_MII_RX_DV/ETH1_ RMII_CRS_DV, ETH1_RGMII_GTX_CLKADC2_INP2
H10-R10VDDCORES----
T8R8U10PA6I/OFT_ha-TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SAI2_CK2, SPI1_MISO/I2S1_SDI, USART1_CK, UART4_RTS/UART4_DE, TIM13_CH1, SAI2_SCK_AADC1_INP17, ADC1_INN16, TAMP_IN2
H11E14R8VSSS----
G6P10-VDDS----
J10-R13VDDCORES----
P8R9AA9PG13I/OFT_vha-LPTIM1_OUT, USART6_CTS/USART6_NSS, ETH1_MII_TXD0/ETH1_ RGMII_TXD0/ETH1_RMII_ TXD0ADC2_INP6, ADC2_INN2
T9L9W10PE5I/OFT_vh-SAI2_SCK_B, TIM8_CH3, TIM15_CH1, UART4_RX, ETH1_MII_TXD3/ETH1_ RGMII_TXD3, FMC_NE1-

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typestructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
P9T8Y10PG14I/OFT_vh-LPTIM1_ETR, SAI2_D1, USART6_TX, SAI2_SD_A, ETH1_MII_TXD1/ETH1_ RGMII_TXD1/ETH1_RMII_TX D1-
J13-U12VDDCORES----
U9U8AA10PC2I/OFT_vha-SPI5_NSS, SPI1_NSS/I2S1_WS, SAI2_MCLK_A, USART1_RTS/USART1_DE, SAI2_CK1, ETH1_MII_TXD2/ETH1_ RGMII_TXD2ADC1_INP15
H14E16R11VSSS----
R9J10W11VDDS----
K8-G11VDDCORES----
N9R10V11NJTRSTIFTU---
U10K10Y11NRSTI/ORST---
T10U7AA12PDR_ONIFT---
U12M10W12USB_RREFAA---
P10U11W14VDD3V3_ USBHSS----
T11T9AA13USB_DP2AFT_u--USBH_HS_DP2 (boot), OTG_HS_DP
U11U9Y13USB_DM2AFT_u--USBH_HS_DM2 (boot), OTG_HS_DM
N10T11Y14VSS_USBHSS----
R10L10Y12PF15 (JTMS/SWDIO)I/OFT(3)JTMS/SWDIO-
T12R11W13PA14I/OFT-DBTRGO, DBTRGI, MCO2, OTG_HS_SOF-
R12M11Y15PI6-BOOT2 (BOOT2)I/OFT(4)BOOT2-
K6--VDDS----
L6--VDDS----
--R7VDDS----

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
R11J11W15VDDA1V8_ REGS----
J7R12R14VSSS----
N11U10V14VDDA1V1_ REGS----
J9T10-VSSS----
--R9VDDS----
--R12VDDS----
P12N11AA15PI5-BOOT1 (BOOT1)I/OFT(4)BOOT1-
U14P11Y17PI4-BOOT0 (BOOT0)I/OFT(4)BOOT0-
U13U12AA16USB_DM1AFT_u--USBH_HS_DM1
T13T12Y16USB_DP1AFT_u--USBH_HS_DP1
U15J12AA19PA10I/OFT_u-TIM1_CH3OTG_HS_ID
U16U13AA20PI7I/OFT_u--OTG_HS_VBUS
R13L11Y18VDD_PLL2S----
P13K11AA18VSS_PLL2S----
K9F12J11VDDCORES----
T14H11W17BYPASS_REG 1V8IFT---
-F5B12VSSS----
T15T13Y19PH4(JTDI)I/OFT(3)JTDI-
R14L12W18PH5(JTDO)I/OFT(3)JTDO-
N13U14V19PWR_LPOFT---
P14R13U17PWR_ONOFT--PWR_ONLP
-F13F17VSSS----
-P12E12VDDS----
E12K14E15VDDQ_DDRS----
R15R15W19DDR_DQ12I/ODDR---
F12M14G15VDDQ_DDRS----
T16U15Y20DDR_DQ15I/ODDR---
-H5A1VSSS----

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typestructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
T17T15Y21DDR_DQ14I/ODDR---
-H13A21VSSS----
P15R16W20DDR_DQ11I/ODDR---
G12N13G17VDDQ_DDRS----
N14R14W21DDR_DQM1ODDR---
H12N15K15VDDQ_DDRS----
R17T16V20DDR_DQS1PI/ODDR---
-J16AA1VSSS----
R16T17V21DDR_DQS1NI/ODDR---
-K5AA21VSSS----
-K13G14VSSS----
M13J13T18DDR_VREFAA---
-H6J15VDDCORES----
J12P14K17VDDQ_DDRS----
P16T14U19DDR_DQ13I/ODDR---
K12-M15VDDQ_DDRS----
P17R17U20DDR_DQ9I/ODDR---
-M5D16VSSS----
N15U16T19DDR_DQ10I/ODDR---
-M13E5VSSS----
N16P17T20DDR_DQ8I/ODDR---
L12-M17VDDQ_DDRS----
N17P16R20DDR_ZQAA---
M16-P17DDR_DTO1ODDR---
M12-R15VDDQ_DDRS----
M14P15R19DDR_A4ODDR---
L15M16P19DDR_A8ODDR---
M17M15R21DDR_A6ODDR---
-N6E6VSSS----
L13N17P18DDR_ATOAA---
-N9E11VSSS----

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
L14--DDR_DTO0ODDR---
N12-R17VDDQ_DDRS----
L16M17P20DDR_BA1ODDR---
--U15VDDQ_DDRS----
L17L17N19DDR_A14ODDR---
-N10E16VSSS----
K13L16N17DDR_A11ODDR---
-N12F5VSSS----
L8N14K11VSSS----
K14L13N20DDR_CKEODDR---
-H12L7VDDCORES----
K15L15N21DDR_A1ODDR---
K17L14M19DDR_A12ODDR---
K16K15M21DDR_A15ODDR---
-N16F18VSSS----
J16K16M20DDR_CLKPODDR---
-P5F21VSSS----
J17K17L20DDR_CLKNODDR---
-H14-VDDQ_DDRS----
J14J15L18DDR_A10ODDR---
-P13G8VSSS----
H17J14K20DDR_RASNODDR---
J15J17L19DDR_CASNODDR---
H13H17K19DDR_WENODDR---
-U17G12VSSS----
P11-L12VSSS----
--H7VSSS----
-K12L9VDDCORES----
H16H16J20DDR_CSNODDR---
G17H15J19DDR_BA0ODDR---
J11-H15VSSS----

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typestructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
H15G17J21DDR_ODTODDR---
K3-J10VSSS----
G16G16H20DDR_A0ODDR---
G15G15H19DDR_A3ODDR---
G14F15J17DDR_A7ODDR---
-D14-VDDQ_DDRS----
F17G13G20DDR_A2ODDR---
-E13-VDDQ_DDRS----
E16F16F20DDR_A5ODDR---
G13G14H18DDR_BA2ODDR---
F16F17G21DDR_A9ODDR---
K7-J12VSSS----
F14E17G19DDR_A13ODDR---
K11-K9VSSS----
E17D15H17DDR_RESETNODDR---
-E15-VDDQ_DDRS----
E15D16F19DDR_DQ7I/ODDR---
-F14-VDDQ_DDRS----
E14D17E20DDR_DQ6I/ODDR---
L7-K10VSSS----
R5-L15VSSS----
L9-K12VSSS----
-M12L13VDDCORES----
D17C16E19DDR_DQ3I/ODDR---
D16C17D20DDR_DQ5I/ODDR---
C17B17C20DDR_DQS0PI/ODDR---
L10-K13VSSS----
C16B16C21DDR_DQS0NI/ODDR---
L11-K21VSSS----
D15C15D21DDR_DQM0ODDR---
E13C14D19DDR_DQ2I/ODDR---

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after reset)Pin typestructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
C15B15B20DDR_DQ1I/ODDR---
M15-L5VSSS----
B17A16B21DDR_DQ0I/ODDR---
N4-L10VSSS----
B16A15B19DDR_DQ4I/ODDR---
A16G12A20PC9I/OFT_h(5)TRACED1, TIM3_CH4, TIM8_CH4, USART3_RTS, UART5_CTS, FDCAN1_TX, SDMMC1_D1, LCD_B4-
C12A14E17VDDSD1S----
R8-L17VSSS----
D14C13C18PC8I/OFT_h(5)TRACED0, TIM3_CH3, TIM8_CH3, SPI3_MISO/I2S3_SDI, USART6_CK, USART3_CTS, SAI2_FS_B, UART5_RTS/UART5_DE, SDMMC1_D0(boot), LCD_G7-
A15G11C19PD2I/OFT_h(5)TRACED4, TIM3_ETR, I2C1_SMBA, SPI3_NSS/I2S3_WS, SAI2_D1, USART3_RX, SDMMC1_CMD(boot)-
B15B13A19PC12I/OFT_h(5)TRACECLK, UART7_TX, SAI2_SD_B, SDMMC1_CK(boot), LCD_DE-
B14F11A18PC10I/OFT_fh(5)TRACED2, I2C1_SCL, SPI3_SCK/I2S3_CK, USART3_TX, SAI2_MCLK_B, SDMMC1_D2-
C14C12B18PC11I/OFT_fh(5)TRACED3, I2C1_SDA, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_RX, SAI2_SCK_B, SDMMC1_D3-
--N10VDDCORES----
A14H10C17PG6I/OFT_h(6)TRACED3, TIM17_BKIN, TIM5_CH4, SAI2_D1, USART1_RX, SAI2_SD_A, SDMMC2_CMD(boot), LCD_G0, LCD_DE, LCD_R7, HDP3-

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
D13B12B17PE3I/OFT_h(6)TRACED11, SAI2_D4, TIM15_BKIN, SPI4_MISO/I2S4_SDI, USART3_RTS/USART3_DE, FDCAN1_RX, SDMMC2_CK(boot), LCD_R4-
B13E11C16PB4I/OFT_h(6)TRACED14, TIM16_BKIN, TIM3_CH1, SAI2_CK2, SPI4_SCK/I2S4_CK, USART3_CK, SDMMC2_D3, LCD_G1, SAI2_SCK_A, LCD_B6, LCD_R0-
A13A12B16PB14I/OFT_h(6)TRACED0, TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SDMMC2_D0(boot), SDMMC1_D4, LCD_R0, LCD_G5-
--N13VDDCORES----
D11A13C15VDDSD2S----
U1-M1VSSS----
C11B11C14PB3I/OFT_h(6)TRACED2, TIM2_CH2, SAI2_CK1, SPI4_NSS/I2S4_WS, SDMMC1_D123DIR, SDMMC2_D2, LCD_R6, SAI2_MCLK_A, UART7_RX, LCD_B2-
B12D11B15PB15I/OFT_h(6)RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, SAI2_D2, SPI4_MOSI/I2S4_SDO, DFSDM1_CKIN2, UART7_CTS, SDMMC1_CKIN, SDMMC2_D1, SAI2_FS_A, LCD_CLK, LCD_B0-
U17-M7VSSS----
C13A11A16PF0I/OFT_h-TRACED13, DFSDM1_CKOUT, USART3_CK, SDMMC2_D4, FMC_A0, LCD_R6, LCD_G0-

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)type - Pinstructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
E11C11E14PH10I/OFT_h-TRACED0, TIM5_CH1, SAI2_D3, DFSDM1_DATIN2, I2S3_MCK, SPI2_MOSI/I2S2_SDO, USART3_CTS/USART3_NSS, SDMMC1_D4, LCD_HSYNC, LCD_R2, HDP0-
A12C10A15PB9I/OFT_fh-TRACED3, TIM4_CH4, I2C4_SDA, FDCAN1_TX, SDMMC2_D5, UART5_TX, SDMMC1_CDIR(boot), LCD_DE, LCD_B1-
-D10G9VDDS----
--M9VSSS----
E10B10D14PB13I/OFT_fh-TRACECLK, TIM1_CH1N, LPTIM2_OUT, SPI2_NSS/I2S2_WS, I2C4_SCL, SDMMC1_D123DIR, FDCAN2_TX, UART5_TX(boot), LCD_CLK-
D10G10E13PB10I/OFT_h-TIM2_CH3, LPTIM2_IN1, I2C5_SMBA, SPI4_NSS/I2S4_WS, SPI2_SCK/I2S2_CK, USART3_TX(boot), LCD_R3-
B11A10B14PC6I/OFT_h-TRACED2, TIM3_CH1, TIM8_CH1,DFSDM1_DATIN0, I2S3_MCK, USART6_TX(boot), SDMMC1_D6, SDMMC2_D0DIR, SDMMC2_D6, LCD_B1, FMC_A19, LCD_R6, LCD_HSYNC, HDP2-
C10F9B13PB5I/OFT_h-TRACED4, TIM17_BKIN, TIM3_CH2, SPI2_MISO/I2S2_SDI, I2C4_SMBA,SDMMC1_CKIN, FDCAN2_RX, UART5_RX(boot), LCD_B6, LCD_DE-

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)Pin typestructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
A11A9C13PC7I/OFT_h-TRACED4, TIM3_CH2, TIM8_CH2, I2S2_MCK, USART6_RX(boot), USART3_CTS, SDMMC2_CDIR, SDMMC2_D7, LCD_R1, SDMMC1_D7, LCD_G6, HDP4-
B10B9A13PF3I/OFT_fh-LPTIM2_IN2, I2C5_SDA, SPI4_MISO/I2S4_SDI, SPI3_NSS/I2S3_WS, FMC_A3, LCD_G3-
A9D9C12PH9I/OFT_h-TIM1_CH4, TIM12_CH2, SPI4_SCK/I2S4_CK, DCMIPP_D13, LCD_B5, LCD_DE, FMC_A20, DCMIPP_D9, DCMIPP_D8-
-C6G13VDDS----
--M10VSSS----
B9A8B11PF1I/OFT_fh-TRACED7, I2C2_SDA, SPI3_MOSI/I2S3_SDO, FMC_A1, LCD_B7, LCD_G1, HDP7-
A10E9A12PH13I/OFT_fh-TRACED15, USART2_CK, TIM8_CH1N, I2C5_SCL, SPI3_SCK/I2S3_CK, UART4_TX, LCD_G3, LCD_G2-
C9C8A10PG7I/OFT_h-TRACED8, TIM1_ETR, SPI3_MISO/I2S3_SDI, UART7_CTS, SDMMC2_CKIN, LCD_R1, LCD_R5, LCD_R2-
A8C9B10PG4I/OFT_h-TRACED1, TIM1_BKIN2, DFSDM1_CKIN3, USART3_RX, SDMMC2_D123DIR, LCD_VSYNC, FMC_A14, DCMIPP_D8, DCMIPP_D13, HDP1-

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typestructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
D9A7C11PB12I/OFT_h-TRACED10, I2C2_SMBA, DFSDM1_DATIN1, UART7_RTS/UART7_DE, USART3_RX(boot), UART5_RX, SDMMC1_D5, LCD_R3, LCD_VSYNC-
E9B7D11PF2I/OFT_fh-TRACED1, I2C2_SCL, DFSDM1_CKIN1, USART6_CK, SDMMC2_D0DIR, SDMMC1_D0DIR, FMC_A2, LCD_G4, LCD_B3-
--M11VSSS----
--J7VDDS----
J6F4G10VDDCPUS----
B8C7C10PE10I/OFT-TIM1_CH2N, UART7_RX, FDCAN1_TX, FMC_D7(boot)/FMC_AD7-
--M12VSSS----
D8A6A9PE15I/OFT_fh-TIM2_ETR, TIM1_BKIN, USART2_CTS/USART2_NSS, I2C4_SCL, FMC_D12(boot)/FMC_AD12, DCMIPP_D10, LCD_B7, HDP7-
-H4-VDDCPUS----
B7B6B8PH14I/OFT_fh-DFSDM1_DATIN2,I2C3_SDA, DCMIPP_D8, UART4_RX, LCD_B4, DCMIPP_D2, DCMIPP_PIXCLK-
A7F8B9PE8I/OFT_f-TIM1_CH1N, DFSDM1_CKIN2, I2C1_SDA, UART7_TX, FMC_D5(boot)/FMC_AD5-
C7A5E9PD15I/OFT_h-USART2_RX, TIM4_CH4, DFSDM1_DATIN2, QUADSPI_BK1_IO3, FMC_D1(boot)/FMC_AD1, LCD_B5-

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after - reset)Pin typestructure - I/ONotesBall functions - Alternate functionsBall functions - Additional functions
E8B5C9PD9I/OFT_h-TRACECLK, DFSDM1_DATIN3, SDMMC2_CDIR, LCD_B5, FMC_D14(boot)/FMC_AD14, LCD_CLK, LCD_B0-
--M13VSSS----
D7A4A7PG0I/OFT_h-FDCAN2_TX, FMC_A10, DCMIPP_PIXCLK, LCD_G5-
A6B4C8PD5I/OFT_h-QUADSPI_BK1_IO0, FMC_NWE(boot), LCD_B0, LCD_G4-
--J9VDDS----
B6A3B7PE9I/OFT_h-TIM1_CH1, QUADSPI_BK1_IO1, LCD_HSYNC, FMC_D6(boot)/FMC_AD6, DCMIPP_D7, LCD_R7, HDP3-
A5C4D8PE7I/OFT_h-TIM1_ETR, LPTIM2_IN1, UART5_TX, FMC_D4(boot)/FMC_AD4, LCD_B3, LCD_R5-
D6B3B6PE0I/OFT_h-DCMIPP_D12, UART8_RX(boot), FDCAN2_RX, LCD_B1, FMC_A11, DCMIPP_D1, LCD_B5-
C6D7A6PD12I/OFT_f-LPTIM1_IN1, TIM4_CH1, I2C1_SCL, USART3_RTS/USART3_DE, FMC_ALE(boot)/FMC_A17, DCMIPP_D6-
E7A2C7PD4I/OFT_h-USART2_RTS/USART2_DE, SPI3_MISO/I2S3_SDI, DFSDM1_CKIN0, QUADSPI_CLK, LCD_R1, FMC_NOE(boot), LCD_R4, LCD_R6-
C5B2B5PD8I/OFT-USART2_TX, I2S4_WS, USART3_TX, UART4_RX(boot), DCMIPP_D9, DCMIPP_D3-

Table 7. STM32MP135A/D ball definitions (continued)

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name - (function after reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
B5C3E8PE1I/OFT_h-LPTIM1_IN2, UART8_TX(boot), LCD_HSYNC, LCD_R4, FMC_NBL1, DCMIPP_D3, DCMIPP_D12-
A4D5C6PB7I/OFT_f-TIM17_CH1N, TIM4_CH2, I2S4_CK, I2C4_SDA, FMC_NCE2, FMC_NL, DCMIPP_D13, DCMIPP_PIXCLK-
B4B1A4PE12I/OFT_h-TIM1_CH3N, SPI4_SCK/I2S4_CK, UART8_RTS/UART8_DE, LCD_VSYNC, LCD_G4, FMC_D9(boot)/FMC_AD9, DCMIPP_D11, LCD_G6, HDP4-
--K7VDDCPUS----
D5C2C5PD1I/OFT_fh-I2C5_SCL, SPI4_MOSI/I2S4_SDO, UART4_TX, QUADSPI_BK1_NCS, LCD_B6, FMC_D3(boot)/FMC_AD3, DCMIPP_D13, LCD_G2-
--K5VDDCPUS----
A3D3D6PD10I/OFT_h-RTC_REFIN, I2C5_SMBA, SPI4_NSS/I2S4_WS, USART3_CK, LCD_G5, LCD_B7, FMC_D15(boot)/FMC_AD15, DCMIPP_VSYNC, LCD_B2-
E6E7B4PA15I/OFT_h-TRACED5, TIM2_CH1, I2S4_MCK, UART4_RTS/UART4_DE, UART4_RX, LCD_R0, LCD_G7, FMC_A9, DCMIPP_D14, DCMIPP_D5, HDP5-
C4C1A3PE13I/OFT_fh-TIM1_CH3, I2C5_SDA, SPI4_MISO/I2S4_SDI, LCD_B1, FMC_D10(boot)/FMC_AD10, DCMIPP_D4, LCD_R6-

Table 7. STM32MP135A/D ball definitions (continued)

99

Table 7. STM32MP135A/D ball definitions (continued)

Pin Number - LFBGA289Pin Number - TFBGA289Pin Number - TFBGA320Pin name (function after reset)Pin typeI/O structureNotesBall functions - Alternate functionsBall functions - Additional functions
B3F7C4PD14I/OFT_fh-TIM4_CH3, I2C3_SDA, USART1_RX, UART8_CTS, FMC_D0(boot)/FMC_AD0, DCMIPP_D8, LCD_R4-
-D12-VDDS----
  1. Power supply is V BAT .
  2. During reset and when configured as alternate function for JTAG/SWD an internal pull-down is present.
  3. During reset and when configured as alternate function for JTAG/SWD an internal pull-up is present.
  4. During reset an internal pull-down is present.
  5. Power supply is V DDSD1 .
  6. Power supply is V DDSD2 .

Table 8. Alternate function AF0 to AF7

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PA0-TIM2_CH1TIM5_CH1TIM8_ETRTIM15_BKIN-SAI1_SD_B-
PA1-TIM2_CH2TIM5_CH2LPTIM3_OUTTIM15_CH1N-DFSDM1_ CKIN0USART2_RTS/ USART2_DE
PA2-TIM2_CH3TIM5_CH3LPTIM4_OUTTIM15_CH1--USART2_TX
PA3-TIM2_CH4TIM5_CH4LPTIM5_OUTTIM15_CH2SPI1_MOSI/ I2S1_SDOSAI1_FS_BUSART2_RX
PA4--TIM5_ETRUSART2_CKSAI1_SCK_BSPI1_NSS/ I2S1_WSDFSDM1_ CKIN1-
PA5-TIM2_CH1/ TIM2_ETRUSART2_CKTIM8_CH1NSAI1_D1SPI1_NSS/ I2S1_WSSAI1_SD_A-
PA6-TIM1_BKINTIM3_CH1TIM8_BKINSAI2_CK2SPI1_MISO/ I2S1_SDI-USART1_CK
PA7-TIM1_CH1NTIM3_CH2TIM8_CH1NSAI2_D1SPI1_SCK/ I2S1_CK-USART1_CTS/ USART1_NSS
PA8MCO1-SAI2_MCLK_ATIM8_BKIN2I2C4_SDASPI5_MISOSAI2_CK1USART1_CK
PA9-TIM1_CH2--I2C3_SMBA-DFSDM1_ DATIN0USART1_TX
PA10-TIM1_CH3------
PA11-TIM1_CH4--I2C5_SCLSPI2_NSS/ I2S2_WS-USART1_CTS/ USART1_NSS
PA12-TIM1_ETRSAI2_MCLK_A----USART1_RTS/ USART1_DE
PA13DBTRGODBTRGIMCO1-----

Table 8. Alternate function AF0 to AF7

Table 8. Alternate function AF0 to AF7 (continued)

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PA14DBTRGODBTRGIMCO2-----
PA15TRACED5TIM2_CH1---I2S4_MCK-UART4_RTS/ UART4_DE
PB0DBTRGITIM1_CH2NTIM3_CH3TIM8_CH2NUSART1_RXI2S1_MCKSAI2_FS_AUSART1_CK
PB1-TIM1_CH3NTIM3_CH4TIM8_CH3N-SPI1_SCK/ I2S1_CKDFSDM1_ DATIN1UART4_RX
PB2-RTC_OUT2SAI1_D1--I2S_CKINSAI1_SD_A-
PB3TRACED2TIM2_CH2--SAI2_CK1SPI4_NSS/ I2S4_WS--
PB4TRACED14TIM16_BKINTIM3_CH1-SAI2_CK2SPI4_SCK/ I2S4_CK-USART3_CK
PB5TRACED4TIM17_BKINTIM3_CH2--SPI2_MISO/ I2S2_SDII2C4_SMBA-
PB6TRACED6TIM16_CH1NTIM4_CH1TIM8_CH1USART1_TX-SAI1_CK2LCD_B6
PB7-TIM17_CH1NTIM4_CH2--I2S4_CKI2C4_SDA-
PB8-TIM16_CH1TIM4_CH3-I2C1_SCLI2C3_SCLDFSDM1_ DATIN1-
PB9TRACED3-TIM4_CH4---I2C4_SDA-
PB10-TIM2_CH3-LPTIM2_IN1I2C5_SMBASPI4_NSS/ I2S4_WSSPI2_SCK/ I2S2_CKUSART3_TX
PB11-TIM2_CH4-LPTIM1_OUTI2C5_SMBA--USART3_RX
PB12TRACED10---I2C2_SMBA-DFSDM1_ DATIN1UART7_RTS/ UART7_DE

Table 8. Alternate function AF0 to AF7 (continued)

Table 8. Alternate function AF0 to AF7 (continued)

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PB13TRACECLKTIM1_CH1N--LPTIM2_OUTSPI2_NSS/ I2S2_WSI2C4_SCL-
PB14TRACED0TIM1_CH2NTIM12_CH1TIM8_CH2NUSART1_TX---
PB15RTC_REFINTIM1_CH3NTIM12_CH2TIM8_CH3NSAI2_D2SPI4_MOSI/ I2S4_SDODFSDM1_ CKIN2UART7_CTS
PC0--SAI1_SCK_A-SAI1_CK2I2S1_MCKSPI1_MOSI/ I2S1_SDOUSART1_TX
PC1---DFSDM1_ DATIN0--SAI1_D3-
PC2-SPI5_NSS---SPI1_NSS/ I2S1_WSSAI2_MCLK_AUSART1_RTS/ USART1_DE
PC3--SAI1_CK1DFSDM1_ CKOUT-SPI1_MISO/ I2S1_SDISPI1_SCK/ I2S1_CK-
PC4--TIM3_ETRDFSDM1_ CKIN2SAI1_D3I2S1_MCK--
PC5---DFSDM1_ DATIN2SAI2_D4I2S_CKINSAI1_D4USART2_CTS/ USART2_NSS
PC6TRACED2-TIM3_CH1TIM8_CH1DFSDM1_ DATIN0I2S3_MCK-USART6_TX
PC7TRACED4-TIM3_CH2TIM8_CH2--I2S2_MCKUSART6_RX
PC8TRACED0-TIM3_CH3TIM8_CH3-SPI3_MISO/ I2S3_SDI-USART6_CK
PC9TRACED1-TIM3_CH4TIM8_CH4---USART3_RTS

Table 8. Alternate function AF0 to AF7 (continued)

Table 8. Alternate function AF0 to AF7 (continued)

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PC10TRACED2----I2C1_SCLSPI3_SCK/ I2S3_CKUSART3_TX
PC11TRACED3---I2C1_SDA-SPI3_MOSI/ I2S3_SDOUSART3_CK
PC12TRACECLK-------
PC13--------
PC14--------
PC15--------
PD0--SAI1_MCLK_A---SAI1_CK1-
PD1----I2C5_SCLSPI4_MOSI/ I2S4_SDO--
PD2TRACED4-TIM3_ETR-I2C1_SMBASPI3_NSS/ I2S3_WSSAI2_D1USART3_RX
PD3--TIM2_CH1USART2_CTS/ USART2_NSSDFSDM1_ CKOUTI2C1_SDASAI1_D3-
PD4---USART2_RTS/ USART2_DE-SPI3_MISO/ I2S3_SDIDFSDM1_ CKIN0-
PD5--------
PD6-TIM16_CH1NSAI1_D1---SAI1_SD_A-
PD7MCO1--USART2_CKI2C2_SCLI2C3_SDA--
PD8---USART2_TX-I2S4_WS-USART3_TX
PD9TRACECLK--DFSDM1_ DATIN3----

Table 8. Alternate function AF0 to AF7 (continued)

Table 8. Alternate function AF0 to AF7 (continued)

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PD10RTC_REFIN---I2C5_SMBASPI4_NSS/ I2S4_WS-USART3_CK
PD11---LPTIM2_IN2I2C4_SMBA--USART3_CTS/ USART3_NSS
PD12-LPTIM1_IN1TIM4_CH1--I2C1_SCL-USART3_RTS/ USART3_DE
PD13-LPTIM2_ETRTIM4_CH2TIM8_CH2SAI1_CK1-SAI1_MCLK_AUSART1_RX
PD14--TIM4_CH3-I2C3_SDA--USART1_RX
PD15-USART2_RXTIM4_CH4DFSDM1_ DATIN2----
PE0------DCMIPP_D12-
PE1-LPTIM1_IN2------
PE2TRACECLKTIM2_ETR--I2C4_SCLSPI5_MOSISAI1_FS_BUSART6_RTS/ USART6_DE
PE3TRACED11-SAI2_D4-TIM15_BKINSPI4_MISO/ I2S4_SDI--
PE4-SPI5_MISOSAI1_D2DFSDM1_ DATIN3TIM15_CH1NI2S_CKINSAI1_FS_AUART7_RTS/U ART7_DE
PE5--SAI2_SCK_BTIM8_CH3TIM15_CH1---
PE6MCO2TIM1_BKIN2SAI2_SCK_B-TIM15_CH2I2C3_SMBASAI1_SCK_B-
PE7-TIM1_ETR--LPTIM2_IN1---
PE8-TIM1_CH1N-DFSDM1_ CKIN2-I2C1_SDA-UART7_TX

Table 8. Alternate function AF0 to AF7 (continued)

Table 8. Alternate function AF0 to AF7 (continued)

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PE9-TIM1_CH1------
PE10-TIM1_CH2N-----UART7_RX
PE11-TIM1_CH2USART2_CTS/ USART2_NSS-SAI1_D2SPI4_MOSI/ I2S4_SDOSAI1_FS_AUSART6_CK
PE12-TIM1_CH3N---SPI4_SCK/ I2S4_CK--
PE13-TIM1_CH3--I2C5_SDASPI4_MISO/ I2S4_SDI--
PE14-TIM1_BKIN--SAI1_D4---
PE15-TIM2_ETRTIM1_BKINUSART2_CTS/ USART2_NSS--I2C4_SCL-
PF0TRACED13--DFSDM1_ CKOUT---USART3_CK
PF1TRACED7---I2C2_SDASPI3_MOSI/ I2S3_SDO--
PF2TRACED1---I2C2_SCL-DFSDM1_ CKIN1USART6_CK
PF3---LPTIM2_IN2I2C5_SDASPI4_MISO/ I2S4_SDISPI3_NSS/ I2S3_WS-
PF4---USART2_RX----
PF5TRACED12---DFSDM1_ CKIN0I2C1_SMBA--
PF6-TIM16_CH1---SPI5_NSS-UART7_RX

Table 8. Alternate function AF0 to AF7 (continued)

Table 8. Alternate function AF0 to AF7 (continued)

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PF7-TIM17_CH1-----UART7_TX
PF8-TIM16_CH1NTIM4_CH3TIM8_CH3--SAI1_SCK_BUSART6_TX
PF9-TIM17_CH1NTIM1_CH1DFSDM1_CKIN 3--SAI1_D4UART7_CTS
PF10-TIM16_BKINSAI1_D3TIM8_BKIN-SPI5_NSS-USART6_RTS/ USART6_DE
PF11-USART2_TXSAI1_D2DFSDM1_ CKIN3--SAI1_FS_A-
PF12-----SPI1_NSS/ I2S1_WSSAI1_SD_A-
PF13-TIM2_ETRSAI1_MCLK_B---DFSDM1_ DATIN3USART2_TX
PF14JTCK/SWCLK-------
PF15JTMS/SWDIO-------
PG0--------
PG1-LPTIM1_ETRTIM4_ETRSAI2_FS_AI2C2_SMBASPI2_MISO/ I2S2_SDISAI2_D2-
PG2-MCO2-TIM8_BKIN----
PG3---TIM8_BKIN2I2C2_SDA-SAI2_SD_B-
PG4TRACED1TIM1_BKIN2--DFSDM1_ CKIN3---
PG5-TIM17_CH1------
PG6TRACED3TIM17_BKINTIM5_CH4SAI2_D1USART1_RX-SAI2_SD_A-

Table 8. Alternate function AF0 to AF7 (continued)

Table 8. Alternate function AF0 to AF7 (continued)

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PG7TRACED8TIM1_ETR---SPI3_MISO/ I2S3_SDI--
PG8-TIM2_CH1-TIM8_ETR-SPI5_MISOSAI1_MCLK_BLCD_B1
PG9DBTRGO---I2C2_SDA--USART6_RX
PG10-----SPI5_SCKSAI1_SD_B-
PG11----SAI2_D3I2S2_MCK-USART3_TX
PG12-LPTIM1_IN1--SAI2_SCK_A-SAI2_CK2USART6_RTS/ USART6_DE
PG13-LPTIM1_OUT-----USART6_CTS/ USART6_NSS
PG14-LPTIM1_ETR----SAI2_D1USART6_TX
PG15-------USART6_CTS/ USART6_NSS
PH0--------
PH1--------
PH2-LPTIM1_IN2----DCMIPP_D9LCD_G1
PH3----I2C3_SCLSPI5_MOSI--
PH4JTDI-------
PH5JTDO-------
PH6--TIM12_CH1USART2_CKI2C5_SDASPI2_SCK/ I2S2_CK--
PH7--SAI2_FS_B--I2C3_SDASPI5_SCK-

Table 8. Alternate function AF0 to AF7 (continued)

Table 8. Alternate function AF0 to AF7 (continued)

PortPortAF0 - RTC/SYSAF1 - LPTIM1/RTC/ SPI5/SYS/ TIM1/2/16/17/ USART2AF2 - SAI1/2/SYS/ TIM1/3/4/5/12/ USART2AF3 - DFSDM1/ LPTIM2/3/4/5/ SAI2/TIM8/ USART2AF4 - DFSDM1/ I2C1/2/3/4/5/ LPTIM2/SAI1/2/ TIM15/USART1AF5 - I2C1/3/SPI1/ I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/ I2S4/SPI5AF6 - DCMIPP/DFSD M1/I2C4/SAI1/2 /SPI1/I2S1/SPI2 /I2S2/SPI3/I2S3 /SPI5AF7 - LCD/UART4/7/ USART1/2/3/6
PH8TRACED9-TIM5_ETRUSART2_RXI2C3_SDA---
PH9-TIM1_CH4TIM12_CH2--SPI4_SCK/ I2S4_CKDCMIPP_D13-
PH10TRACED0-TIM5_CH1SAI2_D3DFSDM1_ DATIN2I2S3_MCKSPI2_MOSI/ I2S2_SDOUSART3_CTS/ USART3_NSS
PH11-SPI5_NSSTIM5_CH2SAI2_SD_A-SPI2_NSS/ I2S2_WSI2C4_SCLUSART6_RX
PH12-USART2_TXTIM5_CH3DFSDM1_ CKIN1I2C3_SCLSPI5_MOSISAI1_SCK_A-
PH13TRACED15-USART2_CKTIM8_CH1NI2C5_SCL-SPI3_SCK/ I2S3_CK-
PH14---DFSDM1_ DATIN2I2C3_SDA-DCMIPP_D8-
PI0--------
PI1--------
PI2--------
PI3--------
PI4BOOT0-------
PI5BOOT1-------
PI6BOOT2-------
PI7--------

Table 8. Alternate function AF0 to AF7 (continued)

Table 9. Alternate function AF8 to AF15

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PA0UART5_TX--ETH1_MII_CRSETH2_MII_CRS---
PA1---ETH1_MII_RX_ CLK/ ETH1_RGMII_ RX_CLK/ ETH1_RMII_ REF_CLK----
PA2---ETH1_MDIO----
PA3---ETH1_MII_COLETH2_MII_COL---
PA4--ETH1_PPS_ OUTETH2_PPS_ OUTSAI1_SCK_A---
PA5--ETH1_PPS_ OUTETH2_PPS_ OUT----
PA6UART4_RTS/ UART4_DETIM13_CH1--SAI2_SCK_A---
PA7-TIM14_CH1-ETH1_MII_RX_ DV/ ETH1_RGMII_ RX_CTL/ ETH1_RMII_ CRS_DVSAI2_SD_A---
PA8SPI2_MOSI/ I2S2_SDO-OTG_HS_SOFETH2_MII_ RXD3/ ETH2_RGMII_ RXD3FMC_A21-LCD_B7-
PA9UART4_TX-FMC_NWAIT--DCMIPP_D0LCD_R6-
PA10--------

Table 9. Alternate function AF8 to AF15

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PA11--ETH2_MII_ RXD1/ ETH2_RGMII_ RXD1/ ETH2_RMII_ RXD1ETH1_CLK-ETH2_CLK--
PA12---ETH2_MII_RX_ DV/ ETH2_RGMII_ RX_CTL/ ETH2_RMII_ CRS_DVFMC_A7DCMIPP_D1LCD_G6-
PA13UART4_TX-------
PA14--OTG_HS_SOF-----
PA15UART4_RXLCD_R0-LCD_G7FMC_A9DCMIPP_D14DCMIPP_D5HDP5
PB0UART4_CTS-SAI2_D2ETH1_MII_ RXD2/ ETH1_RGMII_ RXD2----
Port BPB1---ETH1_MII_ RXD3/ ETH1_RGMII_ RXD3----
Port BPB2UART4_RXQUADSPI_ BK1_NCS-ETH2_MDIOFMC_A6-LCD_B4-
Port BPB3SDMMC1_ D123DIR-SDMMC2_D2LCD_R6SAI2_MCLK_AUART7_RXLCD_B2-

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PB4--SDMMC2_D3LCD_G1SAI2_SCK_ALCD_B6LCD_R0-
PB5SDMMC1_ CKINFDCAN2_RX-UART5_RX-LCD_B6LCD_DE-
PB6-QUADSPI_ BK1_NCS-ETH2_MDIOFMC_NE3DCMIPP_D5LCD_B7HDP6
PB7--FMC_NCE2-FMC_NLDCMIPP_D13DCMIPP_PIXC LK-
PB8UART4_RX-SAI1_D1-FMC_D13/FMC _AD13DCMIPP_D6--
PB9-FDCAN1_TXSDMMC2_D5UART5_TXSDMMC1_ CDIRLCD_DELCD_B1-
PB10------LCD_R3-
PB11---ETH1_MII_TX_ EN/ ETH1_RGMII_ TX_CTL/ ETH1_RMII_TX _EN----
PB12USART3_RX--UART5_RXSDMMC1_D5LCD_R3LCD_VSYNC-
PB13SDMMC1_ D123DIRFDCAN2_TX-UART5_TX-LCD_CLK--
PB14--SDMMC2_D0SDMMC1_D4-LCD_R0LCD_G5-
PB15SDMMC1_ CKIN-SDMMC2_D1-SAI2_FS_ALCD_CLKLCD_B0-

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PC0--------
PC1--ETH1_MII_RX_ DV/ ETH1_RMII_ CRS_DVETH1_RGMII_ GTX_CLK----
PC2--SAI2_CK1ETH1_MII_ TXD2/ ETH1_RGMII_ TXD2----
PC3UART5_CTS-SAI1_MCLK_AETH1_MII_TX_ CLKETH2_MII_TX_ CLK---
PC4UART5_RTS/ UART5_DESPDIFRX_IN2-ETH1_MII_ RXD0/ ETH1_RGMII_ RXD0/ ETH1_RMII_ RXD0SAI2_D3---
PC5-SPDIFRX_IN3-ETH1_MII_ RXD1/ ETH1_RGMII_ RXD1/ ETH1_RMII_ RXD1----
PC6SDMMC1_D6SDMMC2_ D0DIRSDMMC2_D6LCD_B1FMC_A19LCD_R6LCD_HSYNCHDP2

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PC7USART3_CTSSDMMC2_ CDIRSDMMC2_D7LCD_R1SDMMC1_D7-LCD_G6HDP4
PC8USART3_CTS-SAI2_FS_BUART5_RTS/ UART5_DESDMMC1_D0-LCD_G7-
PC9UART5_CTSFDCAN1_TX--SDMMC1_D1-LCD_B4-
PC10--SAI2_MCLK_B-SDMMC1_D2---
PC11UART5_RX-SAI2_SCK_B-SDMMC1_D3---
PC12UART7_TX-SAI2_SD_B-SDMMC1_CK-LCD_DE-
PC13--------
PC14--------
PC15--------
PD0-FDCAN1_RX--FMC_D2/ FMC_AD2DCMIPP_D1--
PD1UART4_TXQUADSPI_BK1 _NCS-LCD_B6FMC_D3/ FMC_AD3DCMIPP_D13LCD_G2-

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PD2----SDMMC1_CMD---
PD3----FMC_CLKDCMIPP_D5--
PD4-QUADSPI_CLK-LCD_R1FMC_NOELCD_R4LCD_R6-
PD5-QUADSPI_BK1 _IO0--FMC_NWELCD_B0LCD_G4-
PD6UART4_TX----DCMIPP_D4DCMIPP_D0-
PD7-SPDIFRX_IN0ETH1_MII_RX_ CLK/ ETH1_RGMII_ RX_CLK/ ETH1_RMII_ REF_CLKQUADSPI_BK1 _IO2FMC_NE1---
PD8UART4_RX----DCMIPP_D9DCMIPP_D3-
PD9--SDMMC2_ CDIRLCD_B5FMC_D14/ FMC_AD14LCD_CLKLCD_B0-
PD10-LCD_G5-LCD_B7FMC_D15/ FMC_AD15DCMIPP_VSYN CLCD_B2-
PD11SPDIFRX_IN0QUADSPI_BK1 _IO2ETH2_RGMII_ CLK125LCD_R7FMC_CLE/FMC _A16UART7_RXDCMIPP_D4-
PD12----FMC_ALE/FMC _A17DCMIPP_D6--
PD13-QUADSPI_BK1 _IO3-QUADSPI_BK2 _IO2FMC_A18-LCD_G4-

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PD14UART8_CTS---FMC_D0/FMC_ AD0DCMIPP_D8LCD_R4-
PD15-QUADSPI_BK1 _IO3--FMC_D1/FMC_ AD1-LCD_B5-
PE0UART8_RXFDCAN2_RX-LCD_B1FMC_A11DCMIPP_D1LCD_B5-
PE1UART8_TXLCD_HSYNC-LCD_R4FMC_NBL1DCMIPP_D3DCMIPP_D12-
PE2-SPDIFRX_IN1ETH2_MII_ RXD1/ ETH2_RGMII_ RXD1/ ETH2_RMII_ RXD1-FMC_A23-LCD_R1-
PE3USART3_RTS/ USART3_DEFDCAN1_RXSDMMC2_CK--LCD_R4--
PE4UART8_TXQUADSPI_BK2 _NCSFMC_NCE2-FMC_A25DCMIPP_D3LCD_G7-
PE5UART4_RX-ETH1_MII_ TXD3/ ETH1_RGMII_ TXD3-FMC_NE1---
PE6UART4_RTS/ UART4_DE--ETH2_MII_ TXD3/ ETH2_RGMII_ TXD3FMC_A22DCMIPP_D7LCD_G3-
PE7UART5_TX---FMC_D4/ FMC_AD4LCD_B3LCD_R5-

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PE8----FMC_D5/ FMC_AD5---
PE9-QUADSPI_BK1 _IO1-LCD_HSYNCFMC_D6/ FMC_AD6DCMIPP_D7LCD_R7HDP3
PE10-FDCAN1_TX--FMC_D7/ FMC_AD7---
PE11-LCD_R0ETH2_MII_TX_ ERETH1_MII_TX_ ERFMC_D8/ FMC_AD8DCMIPP_D10LCD_R5-
PE12UART8_RTS/ UART8_DELCD_VSYNC-LCD_G4FMC_D9/ FMC_AD9DCMIPP_D11LCD_G6HDP4
PE13---LCD_B1FMC_D10/ FMC_AD10DCMIPP_D4LCD_R6-
PE14UART8_RTS/ UART8_DEQUADSPI_BK1 _NCSQUADSPI_BK2 _IO2-FMC_D11/ FMC_AD11DCMIPP_D7LCD_G0-
PE15----FMC_D12/ FMC_AD12DCMIPP_D10LCD_B7HDP7
PF0--SDMMC2_D4-FMC_A0LCD_R6LCD_G0-
PF1----FMC_A1LCD_B7LCD_G1HDP7
PF2-SDMMC2_ D0DIR-SDMMC1_ D0DIRFMC_A2LCD_G4LCD_B3-
PF3----FMC_A3-LCD_G3-

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PF4---ETH2_MII_ RXD0/ ETH2_RGMII_ RXD0/ ETH2_RMII_ RXD0FMC_A4DCMIPP_D4LCD_B6-
PF5-LCD_G0--FMC_A5DCMIPP_D11LCD_R5-
PF6-QUADSPI_BK1 _IO2-ETH2_MII_TX_ EN/ ETH2_RGMII_ TX_CTL/ ETH2_RMII_TX _EN-LCD_R7LCD_G4-
PF7UART4_CTS-ETH1_RGMII_ CLK125ETH2_MII_ TXD0/ ETH2_RGMII_ TXD0/ ETH2_RMII_ TXD0FMC_A18-LCD_G2-
PF8-TIM13_CH1QUADSPI_BK1 _IO0--DCMIPP_D15LCD_B3-
PF9UART8_RXTIM14_CH1QUADSPI_BK1 _IO1QUADSPI_BK2 _IO3FMC_A9-LCD_B6-
PF10UART7_RTS/ UART7_DEQUADSPI_CLK---DCMIPP_HSYN CLCD_B5-
PF11----ETH2_MII_RX_ ER---

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PF12UART4_TX-ETH1_MII_TX_ ERETH1_RGMII_ CLK125----
PF13UART5_RX-------
PF14--------
PF15--------
PG0-FDCAN2_TX--FMC_A10DCMIPP_PIXC LKLCD_G5-
PG1-FDCAN2_TXETH2_MII_TXD 2/ETH2_RGMII _TXD2-FMC_NBL0-LCD_G7-
PG2--SAI2_MCLK_BETH1_MDC-DCMIPP_D1--
PG3-FDCAN2_RXETH2_RGMII_ GTX_CLKETH1_MDIOFMC_A13DCMIPP_D15DCMIPP_D12-
PG4USART3_RX-SDMMC2_ D123DIRLCD_VSYNCFMC_A14DCMIPP_D8DCMIPP_D13HDP1
PG5--ETH2_MDCLCD_G4FMC_A15DCMIPP_VSYN CDCMIPP_D3-
PG6--SDMMC2_CMDLCD_G0-LCD_DELCD_R7HDP3
PG7UART7_CTS-SDMMC2_ CKINLCD_R1-LCD_R5LCD_R2-
PG8USART3_RTS/ USART3_DESPDIFRX_IN2QUADSPI_BK2 _IO2QUADSPI_BK1 _IO3FMC_NE2ETH2_CLKDCMIPP_D6-

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PG9SPDIFRX_IN3FDCAN1_RXFMC_NE2-FMC_NCEDCMIPP_VSYN C--
PG10UART8_CTSFDCAN1_TXQUADSPI_BK2 _IO1-FMC_NE3DCMIPP_D2--
PG11UART4_TX-ETH2_MII_ TXD1/ ETH2_RGMII_ TXD1/ ETH2_RMII_ TXD1-FMC_A24DCMIPP_D14LCD_B2-
PG12USART3_CTS-ETH2_PHY_ INTNETH1_PHY_ INTNETH2_MII_RX_ DV/ ETH2_RGMII_ RX_CTL/ ETH2_RMII_ CRS_DV---
PG13---ETH1_MII_ TXD0/ ETH1_RGMII_ TXD0/ ETH1_RMII_ TXD0----
PG14--SAI2_SD_AETH1_MII_ TXD1/ ETH1_RGMII_ TXD1/ ETH1_RMII_ TXD1----

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
Port GPG15UART7_CTSQUADSPI_BK1 _IO1ETH2_PHY_ INTNLCD_B4-DCMIPP_D10LCD_B3-
Port HPH0--------
PH1--------
PH2UART7_TXQUADSPI_BK2 _IO0ETH2_MII_CRSETH1_MII_CRSFMC_NE4ETH2_RGMII_ CLK125LCD_B0-
PH3-QUADSPI_BK2 _IO1ETH1_MII_COLLCD_R5ETH2_MII_COLQUADSPI_BK1 _IO0LCD_B4-
PH4--------
PH5--------
PH6-QUADSPI_BK1 _IO2ETH1_PHY_IN TNETH1_MII_RX_ ERETH2_MII_ RXD2/ ETH2_RGMII_ RXD2QUADSPI_BK1 _NCS--
PH7-QUADSPI_BK2 _IO3ETH2_MII_TX_ CLKETH1_MII_TX_ CLK-QUADSPI_BK1 _IO3LCD_B2-
PH8---LCD_R6FMC_A8DCMIPP_HSYN CLCD_R2HDP2
PH9-LCD_B5-LCD_DEFMC_A20DCMIPP_D9DCMIPP_D8-
PH10SDMMC1_D4----LCD_HSYNCLCD_R2HDP0

Table 9. Alternate function AF8 to AF15 (continued)

Table 9. Alternate function AF8 to AF15 (continued)

PortPortAF8 - SDMMC1/ SPDIFRX/SPI2/ I2S2/ UART4/5/7/8/ USART3AF9 - FDCAN1/2/LCD /QUADSPI/ SDMMC2/ SPDIFRX/ TIM13/14AF10 - ETH1/2/FMC/ OTG_HS/ QUADSPI/ SAI1/2/ SDMMC2AF11 - ETH1/2/LCD/ QUADSPI/ SDMMC1/ UART5AF12 - ETH2/FMC/ SAI1/2/ SDMMC1AF13 - DCMIPP/ETH2/ LCD/QUADSPI/ UART7AF14 - DCMIPP/LCDAF15 - HDP/SYS
PH11-QUADSPI_BK2 _IO0-ETH2_MII_RX_ CLK/ ETH2_RGMII_ RX_CLK/ ETH2_RMII_ REF_CLKFMC_A12-LCD_G6-
PH12-QUADSPI_BK2 _IO2SAI1_CK2ETH1_MII_CRSFMC_A6DCMIPP_D3--
PH13UART4_TX----LCD_G3LCD_G2-
PH14UART4_RX--LCD_B4-DCMIPP_D2DCMIPP_PIXC LK-
PI0SPDIFRX_IN0-------
PI1SPDIFRX_IN1-------
PI2SPDIFRX_IN2-------
PI3SPDIFRX_IN3--ETH1_MII_RX_ ER----
PI4--------
PI5--------
PI6--------
PI7--------

STM32MP135DAG Electrical Characteristics

Unless otherwise specified, the parameters given in Table 79 , Table 80 and Table 81 are derived from tests performed under the ambient temperature and V DDA supply voltage conditions summarized in Table 13: General operating conditions . In Table 79 , Table 80 and Table 81 , f ADC refers to f adc_ker_ck .

Note: When both ADCs are used, the kernel clock should be the same for both ADCs and the embedded ADC prescalers cannot be used.

209

Table 79. 12-bit ADC characteristics (1)(2)

SymbolParameterConditionsConditionsConditionsMinTypMaxUnit
V DDAAnalog power supply forADC ON---1.62-3.6V
V REF+Positive reference voltageV DDA ≥ V REF+V DDA ≥ V REF+V DDA ≥ V REF+1.62-V DDAV
V REF-Negative reference voltage---V SSA--V
f ADCADC clock frequency1,62 V ≤ V DDA ≤ 3.6 V1,62 V ≤ V DDA ≤ 3.6 V1,62 V ≤ V DDA ≤ 3.6 V1.5-75MHz
f SSampling rate for fast channels (VIN[0:5])Resolution = 12 bits -40 °C ≤ T J ≤ 125 °CContinuous mode (3)1.8 V ≤ V DDA ≤ 3.6 V f ADC = 75 MHz--5.00MSPS
f SSampling rate for fast channels (VIN[0:5])Resolution = 12 bits -40 °C ≤ T J ≤ 125 °CContinuous mode (3)1.62 V ≤ V DDA ≤ 3.6 V f ADC = 70 MHz--4.66MSPS
f SSampling rate for fast channels (VIN[0:5])SMP = 2.5Single or Discontinuous mode2.4 V ≤ V DDA ≤ 3.6 V f ADC = 60 MHz (4)--4.00MSPS
f SSampling rate for fast channels (VIN[0:5])Resolution = 12 bits -40 °C ≤ T J ≤ 125 °CSingle or Discontinuous mode1.62 V ≤ V DDA ≤ 3.6V f ADC = 50 MHz (4)--3.33MSPS
f SSampling rate for fast channels (VIN[0:5])Resolution = 10 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5Continuous mode (3)1.62 V ≤ V DDA ≤ 3.6V f ADC = 75 MHz--5.77MSPS
f SSampling rate for fast channels (VIN[0:5])Resolution = 10 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5Single or Discontinuous mode2.4 V ≤ V DDA ≤ 3.6 V f ADC = 75 MHz (4)--5.77MSPS
f SSampling rate for fast channels (VIN[0:5])Resolution = 10 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5Single or Discontinuous mode1.62 V ≤ V DDA ≤ 3.6V f ADC = 65 MHz (4)--5.00MSPS
f SSampling rate for fast channels (VIN[0:5])Resolution = 8 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5All modes (3)1.62 V ≤ V DDA ≤ 3.6V f ADC = 75 MHz--6.82MSPS
f SSampling rate for fast channels (VIN[0:5])Resolution = 6 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5All modes (3)1.62 V ≤ V DDA ≤ 3.6V f ADC = 75 MHz--8.33MSPS

Table 79. 12-bit ADC characteristics (1)(2)

Table 79. 12-bit ADC characteristics (1)(2) (continued)

SymbolParameterConditionsConditionsConditionsMinTypMaxUnit
f SSampling rate for slow channelsResolution = 12 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5-f ADC = 35 MHz (4)--2.3MSPS
f SSampling rate for slow channelsResolution = 10 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5-f ADC = 35 MHz (4)--2.7MSPS
f SSampling rate for slow channelsResolution = 8 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5-f ADC = 50 MHz (4)--4.5MSPS
f SSampling rate for slow channelsResolution = 6 bits -40 °C ≤ T J ≤ 125 °C SMP = 2.5-f ADC = 50 MHz (4)--5.5MSPS
t TRIGExternal trigger periodResolution = 12 bitsResolution = 12 bitsResolution = 12 bits--151/f ADC
V AINConversion voltage range---0-V REF+V
V CMIVCommon mode input voltageDifferential modeDifferential modeDifferential modeV REF /2 - 10%V REF /2V REF /2+ 10%V
R AIN (5)External input impedanceResolution = 12 bits, T J = 125 °CResolution = 12 bits, T J = 125 °CResolution = 12 bits, T J = 125 °C--220Ω
R AIN (5)External input impedanceResolution = 10 bits, T J = 125 °CResolution = 10 bits, T J = 125 °CResolution = 10 bits, T J = 125 °C--2100Ω
R AIN (5)External input impedanceResolution = 8 bits, T J = 125 °CResolution = 8 bits, T J = 125 °CResolution = 8 bits, T J = 125 °C--12000Ω
R AIN (5)External input impedanceResolution = 6 bits, T J = 125 °CResolution = 6 bits, T J = 125 °CResolution = 6 bits, T J = 125 °C--80000Ω
C ADCInternal sample and hold capacitor----3-pF
t ADC VREG_ STUPADC LDO startup time----510μs
t STABADC power-up timeLDO already startedLDO already startedLDO already started1--con- version cycle

Table 79. 12-bit ADC characteristics (1)(2) (continued)

Table 79. 12-bit ADC characteristics (1)(2) (continued)

SymbolParameterConditionsMinTypMaxUnit
t OFF_ CALOffset calibration time-135135135
t LATRTrigger conversion latency for regular and injected channels without aborting the conversionCKMODE = 001.522.5
t LATRTrigger conversion latency for regular and injected channels without aborting the conversionCKMODE = 01--2.5
t LATRTrigger conversion latency for regular and injected channels without aborting the conversionCKMODE = 10--2.5
t LATRTrigger conversion latency for regular and injected channels without aborting the conversionCKMODE = 11--2.25
t LATR INJTrigger conversion latency for regular and injected channels when a regular conversion is abortedCKMODE = 002.533.51/f ADC
t LATR INJTrigger conversion latency for regular and injected channels when a regular conversion is abortedCKMODE = 01--3.5
t LATR INJTrigger conversion latency for regular and injected channels when a regular conversion is abortedCKMODE = 10--3.5
t LATR INJTrigger conversion latency for regular and injected channels when a regular conversion is abortedCKMODE = 11--3.25
t SSampling time (6)-2.5-640.5
t CONVTotal conversion time (including sampling time)N-bits resolutiont S + 0.5 + N--
I DDA_D (ADC)ADC consumption on V DDA and V REF , Differential modef S = 5 MSPS-540-μA
I DDA_D (ADC)ADC consumption on V DDA and V REF , Differential modef S = 1 MSPS-190-μA
I DDA_D (ADC)ADC consumption on V DDA and V REF , Differential modef S =0.1 MSPS-49-μA
I DDA_SE (ADC)ADC consumption on V DDA and V REF , Single-ended modef S = 5 MSPS-416-μA
I DDA_SE (ADC)ADC consumption on V DDA and V REF , Single-ended modef S = 1 MSPS-153-μA
I DDA_SE (ADC)ADC consumption on V DDA and V REF , Single-ended modef S = 0.1 MSPS-46-μA
I DD (ADC)ADC consumption on V DDf ADC = 75 MHz-180-μA
I DD (ADC)ADC consumption on V DDf ADC = 50 MHz-135-μA
I DD (ADC)ADC consumption on V DDf ADC = 25 MHz-90-μA
I DD (ADC)ADC consumption on V DDf ADC = 12.5 MHz-45-μA
I DD (ADC)ADC consumption on V DDf ADC = 6.25 MHz-22-μA
I DD (ADC)ADC consumption on V DDf ADC = 3.125 MHz-11-μA

Table 79. 12-bit ADC characteristics (1)(2) (continued)

  1. The voltage booster on ADC switches must be used for V DDA < 2.4 V (embedded I/O switches).
  2. The conversion of the first element in the group is excluded.
  3. f ADC value corresponds to the maximum frequency that can be reached considering a 2.5 sampling period. For other SMPy sampling periods, the maximum frequency is f ADC value * SMPy / 2.5 with a limitation to 75 MHz.
  4. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. It is otherwise specified.
  5. The sampling time can vary depending on the condition with ±0.5 clock cycles. Resulting in minimum of 2.0 cycles and maximum of 641 cycles. Refer to the detailed description in the reference manual.

Table 80. Minimum sampling time vs R AIN (12-bit ADC) (1)(2)

  • Resolution RAIN ( Ω ) Minimum sampling time (s) - Fast channels (3) Minimum sampling time (s) - Slow channels (4)
  • 47 3.75E-08 6.12E-08
  • 68 3.94E-08 6.25E-08
  • 100 4.36E-08 6.51E-08
  • 150 5.11E-08 7.00E-08
  • 220 6.54E-08 7.86E-08
  • 330 8.80E-08 9.57E-08
  • 470 1.17E-07 1.23E-07
  • 680 1.60E-07 1.65E-07
  • 47 3.19E-08 5.17E-08
  • 68 3.35E-08 5.28E-08
  • 100 3.66E-08 5.45E-08
  • 150 4.35E-08 5.83E-08
  • 220 5.43E-08 6.50E-08
  • 330 7.18E-08 7.89E-08
  • 470 9.46E-08 1.00E-07
  • 680 1.28E-07 1.33E-07
  • 1000 1.81E-07 1.83E-07
  • 1500 2.63E-07 2.63E-07
  • 2200 3.79E-07 3.76E-07
  • 3300 5.57E-07 5.52E-07
  • 47 2.64E-08 4.17E-08
  • 68 2.76E-08 4.24E-08
  • 100 3.02E-08 4.39E-08
  • 150 3.51E-08 4.66E-08
  • 220 4.27E-08 5.13E-08
  • 330 5.52E-08 6.19E-08
  • 470 7.17E-08 7.72E-08
  • 680 9.68E-08 1.00E-07
  • 1000 1.34E-07 1.37E-07
  • 1500 1.93E-07 1.94E-07
  • 2200 2.76E-07 2.74E-07
  • 3300 4.06E-07 4.01E-07
  • 4700 5.73E-07 5.62E-07

Table 80. Minimum sampling time vs R AIN (12-bit ADC) (1)(2)

Table 80. Minimum sampling time vs R AIN (12-bit ADC) (1)(2) (continued)

ResolutionRAIN ( Ω )Minimum sampling time (s) - Fast channels (3)Minimum sampling time (s) - Slow channels (4)
8 bits (continued)68008.21E-077.99E-07
8 bits (continued)100001.20E-061.17E-06
8 bits (continued)150001.79E-061.74E-06
6 bits472.14E-083.16E-08
6 bits682.23E-083.21E-08
6 bits1002.40E-083.31E-08
6 bits1502.68E-083.52E-08
6 bits2203.13E-083.87E-08
6 bits3303.89E-084.51E-08
6 bits4704.88E-085.39E-08
6 bits6806.38E-086.79E-08
6 bits10008.70E-088.97E-08
6 bits15001.23E-071.24E-07
6 bits22001.73E-071.73E-07
6 bits33002.53E-072.49E-07
6 bits47003.53E-073.45E-07
6 bits68005.04E-074.90E-07
6 bits100007.34E-077.11E-07
6 bits150001.09E-061.05E-06
  1. Specified by design, not tested in production.
  2. Data valid up to 130 °C, with a 22 pF PCB capacitor and V DDA = 1.62 V.
  3. Fast channels correspond to ADCx_INx[0:5].
  4. Slow channels correspond to all ADC inputs except for the Fast channels.

209

Table 81. 12-bit ADC accuracy (1)(2)

SymbolParameterConditionsConditionsMinTypMaxUnit
ETTotal unadjusted errorFastandslow channelSingle ended-±3.5±12±LSB
ETTotal unadjusted errorFastandslow channelDifferential-±2.5±5±LSB
EOOffset errorSingle endedSingle ended-±3±5.5±LSB
EOOffset errorDifferentialDifferential-±2±3.5±LSB
EGGain errorSingle endedSingle ended-±3.5±11±LSB
EGGain errorDifferentialDifferential-±2.5±5±LSB
EDDifferential linearity errorSingle endedSingle ended-±0.75+1.5/-1±LSB
EDDifferential linearity errorDifferentialDifferential-±0.75+2.5/-1±LSB
ELIntegral linearity errorFastandslow channelSingle ended-±2±4.5±LSB
ELIntegral linearity errorFastandslow channelDifferential-±1±2±LSB
ENOBEffective number of bitsSingle endedSingle ended-10.8-bits
ENOBEffective number of bitsDifferentialDifferential-11.5-bits
SINADSignal-to-noise and distortion ratioSingle endedSingle ended-68-dB
SINADSignal-to-noise and distortion ratioDifferentialDifferential-71-dB
SNRSignal-to-noise ratioSingle endedSingle ended-70-dB
SNRSignal-to-noise ratioDifferentialDifferential-72-dB
THDTotal harmonic distortionSingle endedSingle ended--70-dB
THDTotal harmonic distortionDifferentialDifferential--80-dB
  1. ADC DC accuracy values are measured after internal calibration in Continuous mode.

Figure 36. ADC accuracy characteristics

Figure 37. Typical connection diagram using the ADC with FT/TT pins featuring analog switch function

  1. Refer to Table 79 and Table 80 for the values of R AIN and C ADC .
  2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 54: I/O static characteristics ). A high C parasitic value downgrades conversion accuracy. To remedy this, f ADC should be reduced.
  3. Refer to Table 54: I/O static characteristics for value of I leak .
  4. Refer to Figure 10: Power supply scheme .

209

STM32MP135DAG Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics , Table 11: Current characteristics , and Table 12: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 10. Voltage characteristics (1)

SymbolsRatingsMinMaxUnit
V DDX - V SSXExternal main supply voltage (including V DD, V DDSD1 , V DDSD2 , V DD_ANA , V DD_PLL , V DDA , V DD3V3_USBHS , V BAT , V REF+ )-0.33.9V
V DDCORE - V SSExternal core supply voltage-0.31.5V
V DDCPU - V SSExternal Cortex ® -A7 CPU supply voltage-0.31.5V
V DDA_DDR - V SSDDR IO supply voltage-0.31.98V

Table 10. Voltage characteristics (1)

Table 10. Voltage characteristics (continued) (1)

SymbolsRatingsMinMaxUnit
V DDA1V8 - V SS1.8 V supply (V DDA1V8_REG )-0.33.9V
V IN (2)Input voltage on FT_xxx pinsV SS - 0.3(3)V
V IN (2)Input voltage on TT_xx pinsV SS - 0.33.9V
V IN (2)Input voltage on USB/OTG_HS_DP/DM pinsV SS - 0.3(4)V
V IN (2)Input voltage on any other pinsV SS - 0.33.9V
| ∆ V DDX |Variations between differentV DDX power pins of the same domain-50mV
|V SSx -V SS |Variations between all the different ground pins-50mV
V REF+ - V DDAAllowed voltage difference for V REF+ > V DDA-0.4V
  1. Min(6.0, V DD +3.9, V DDA +3.9, V DD3V3_USBHS +3.9, V BAT +3.9). This formula has to be applied on power supplies related to the IO structure described by the pin definition table.

To sustain a voltage higher than 3.9 V the internal pull-up/pull-down resistors must be disabled.

  1. Min(5.25, V DD +3.9, V DD3V3_USBHS +3.9).
  2. All power (V DD , V DDSD1 , V DDSD2 , V DDA , V DD3V3_USBHS ) and ground (V SS , V SSA , V SSX ) pins must always be connected to the external/internal power supply, in the permitted range.
  3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins.
  4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
  5. A positive injection is induced by V IN >V DD while a negative injection is induced by V IN <V SS . I INJ(PIN) must never be exceeded. Refer also to Table 10: Voltage characteristics for the maximum allowed input voltage values.
  6. When several inputs are submitted to a current injection, the maximum ∑ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 11. Current characteristics (1)

SymbolsRatingsMaxUnit
Σ IV DDTotal current into sum of all V DD power lines (source)440mA
IV DDMaximum current into each V DD power pin (source)100mA
IV SSMaximum current out of each V SS ground pin (sink)100mA
I IOOutput current sunk by any I/O and control pin20mA
Σ I (PIN)Total output current sunk by sum of all I/Os and control pins (2)140mA
Σ I (PIN)Total output current sourced by sum of all I/Os and control pins (2)140mA
I INJ(PIN) (3)(4)Injected current on FT_xxx, TT_xx, NRST pins-5/+0mA
Σ I INJ(PIN)Total injected current (sum of all I/Os and control pins) (5)±25mA

209

Table 12. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature (suffix 7)105°C
T JMaximum junction temperature (suffix 3)125°C

STM32MP135DAG Thermal Information

Package thermal characteristics in Table 117 are specified with conditions as per JEDEC JESD51-6, JESD51-8, JESD51-9, and JESD51-12. These typical values will vary in function of board thermal characteristics and other components on the board.

Θ JA :

Thermal resistance junction-ambient.

Θ JB :

Thermal resistance junction-board.

Θ JC :

Thermal resistance junction-top-case.

Θ jb:

Thermal parameter junction-board.

Ψ jt:

Thermal parameter junction-top-case.

Motherboard type: four layers, JEDEC 2S2P

Table 117. Thermal characteristics

SymbolValue - Natural convectionValue - 1m/s (200 ft/mn)Unit
Θ JA (1)LFBGA289 - 289-ball 14x14 mm0.80 mm pitch31.729.2°C/W
Θ JA (1)TFBGA289 - 289-ball 9x9 mm0.50 mm pitch29.327°C/W
Θ JA (1)TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch2926.6°C/W
Θ JB (2)LFBGA289 - 289-ball 14x14 mm0.80 mm pitch21.221.2°C/W
Θ JB (2)TFBGA289 - 289-ball 9x9 mm0.50 mm pitch15.915.9°C/W
Θ JB (2)TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch16.916.9°C/W
Θ JC (3)LFBGA289 - 289-ball 14x14 mm0.80 mm pitch8.98.9°C/W
Θ JC (3)TFBGA289 - 289-ball 9x9 mm0.50 mm pitch8.68.6°C/W
Θ JC (3)TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch8.58.5°C/W
Ψ jb (4)LFBGA289 - 289-ball 14x14 mm0.80 mm pitch21.120.9°C/W
Ψ jb (4)TFBGA289 - 289-ball 9x9 mm0.50 mm pitch15.915.8°C/W
Ψ jb (4)TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch16.916.8°C/W
Ψ jt (5)LFBGA289 - 289-ball 14x14 mm0.80 mm pitch0.210.29°C/W
Ψ jt (5)TFBGA289 - 289-ball 9x9 mm0.50 mm pitch0.180.26°C/W
Ψ jt (5)TFBGA320 - 320-ball 11x11 mm 0.50 mm pitch0.180.26°C/W
  1. Per JEDEC JESD51-9
  2. Per JEDEC JESD51-8
  3. Per JEDEC JESD51-12 best practice guidelines
  4. Per JEDEC JESD51-12.
  5. Per JEDEC JESD51-12.

STM32MP135DAG Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

Variants on the same datasheet

These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.

Part NumberManufacturerPackage
STM32MP135STMicroelectronics—
STM32MP135ASTMicroelectronics—
STM32MP135A/DSTMicroelectronics—
STM32MP135AAESTMicroelectronics—
STM32MP135AAFSTMicroelectronics—
STM32MP135AAGSTMicroelectronics—
STM32MP135DSTMicroelectronics—
STM32MP135DAESTMicroelectronics—
STM32MP135DAFSTMicroelectronics—
STM32MP135DAF7STMicroelectronics320-TFBGA

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