STM32H743ZIT6

Part: STM32H743xI family (variants: STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI, STM32H743AI)

Type: 32-bit Arm® Cortex®-M7 MCU

Key Specs:

• Core Frequency: 400 MHz
• Flash Memory: Up to 2 Mbytes
• RAM: 1 Mbyte
• I/O Ports: Up to 168
• Supply Voltage: 1.62 to 3.6 V
• Low-power consumption: Down to 4 μA
• ADC Resolution: 16-bit max. (14 bits 4 MSPS, 16 bits 3.6 MSPS)
• DMIPS: 856 DMIPS

Features:

• 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache
• Read-while-write Flash support
• Dual mode Quad-SPI memory interface up to 133 MHz
• Flexible external memory controller with up to 32-bit data bus
• ROP, PC-ROP, active tamper security
• Up to 168 I/O ports with interrupt capability, up to 164 5 V-tolerant I/Os
• 3 separate power domains (D1, D2, D3)
• Embedded regulator (LDO) with configurable scalable output
• Low-power modes: Sleep, Stop, Standby and VBAT
• Internal oscillators (64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 40 kHz LSI)
• External oscillators (4-48 MHz HSE, 32.768 kHz LSE)
• 3× PLLs with fractional mode
• 3 bus matrices (1 AXI and 2 AHB)
• 4 DMA controllers (MDMA, dual-port DMAs, basic DMA)
• Up to 35 communication peripherals (e.g., 4x I2C FM+, 4x USART/4x UARTs, 6x SPIs, 2x CAN FD, 2x USB OTG, Ethernet MAC)
• 11 analog peripherals (e.g., 3x ADCs, 1x temperature sensor, 2x 12-bit DACs, 2x comparators, 2x operational amplifiers)
• Graphics: LCD-TFT controller up to XGA resolution, Chrom-ART graphical hardware Accelerator™, Hardware JPEG Codec
• Up to 22 timers and watchdogs (e.g., high-resolution timer, 32-bit timers, advanced motor control timers, low-power timers)
• SWD & JTAG interfaces, 4 Kbyte Embedded Trace Buffer
• True random number generators (3 oscillators each)
• 96-bit unique ID
• ECOPACK®2 compliant packages

Applications:

• null

Package:

• null

{
  "manufacturer":

Core

• 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing one cache line to be filled in a single access from the 256-bit embedded Flash memory; frequency up to 400 MHz, MPU, 856 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

Memories

• Up to 2 Mbytes of Flash memory with readwhile-write support
• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
• Dual mode Quad-SPI memory interface running up to 133 MHz
• Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash clocked up to 133 MHz in synchronous mode
• CRC calculation unit

Security

• ROP, PC-ROP, active tamper

General-purpose input/outputs

• Up to 168 I/O ports with interrupt capability
  • Fast I/Os capable of up to 133 MHz
  • Up to 164 5 V-tolerant I/Os

Reset and power management

• 3 separate power domains which can be independently clock gated or switched off to maximize power efficiency:

• D1: high-performance capabilities for high bandwidth peripherals
• D2: communication peripherals and timers
• D3: reset/clock control/power management
• 1.62 to 3.6 V application supply and I/Os
• POR, PDR, PVD and BOR
• Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
• Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
• Voltage scaling in Run and Stop mode (5 configurable ranges)
• Backup regulator (~0.9 V)
• Voltage reference for analog peripheral/VREF+
• Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging

Low-power consumption

• Total current consumption down to 4 μA

Clock management

• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 40 kHz LSI
• External oscillators: 4-48 MHz HSE, 32.768 kHz LSE
• 3× PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode

October 2017 DocID030538 Rev 3 1/226

This is information on a product in full production.

Interconnect matrix

• 3 bus matrices (1 AXI and 2 AHB)
• Bridges (5× AHB2-APB, 2× AXI2-AHB)

4 DMA controllers to unload the CPU

• 1× high-speed general-purpose master direct memory access controller (MDMA) with linked list support
• 2× dual-port DMAs with FIFO and request router capabilities
• 1× basic DMA with request router capabilities

Up to 35 communication peripherals

• 4× I2C FM+ interfaces (SMBus/PMBus)
• 4× USART/4x UARTs (ISO7816 interface, LIN, IrDA, modem control, up to 12.5 Mbit/s) and 1x LPUART
• 6× SPIs, including 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 133 MHz)
• 4x SAIs (serial audio interface)
• SPDIFRX interface
• SWPMI single-wire protocol master I/F
• MDIO Slave interface
• 2× SD/SDIO/MMC interfaces (up to 125 MHz)
• 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
• 2× USB OTG interfaces (1FS, 1HS/FS)
• Ethernet MAC interface with DMA controller
• HDMI-CEC
• 8- to 14-bit camera interface (up to 80 MHz)

11 analog peripherals

• 3× ADCs with 16-bit max. resolution (14 bits 4 MSPS, 16 bits 3.6 MSPS)

• 1× temperature sensor
• 2× 12-bit D/A converters (1 MHz)
• 2× ultra-low-power comparators
• 2× operational amplifiers (8 MHz bandwidth)
• 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters

Graphics

• LCD-TFT controller up to XGA resolution
• Chrom-ART graphical hardware Accelerator™ (DMA2D) to reduce CPU load
• Hardware JPEG Codec

Up to 22 timers and watchdogs

• 1× high-resolution timer (2.5 ns max resolution)
• 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 200 MHz)
• 2× 16-bit advanced motor control timers (up to 200 MHz)
• 10× 16-bit general-purpose timers (up to 200 MHz)
• 5× 16-bit low-power timers (up to 200 MHz)
• 2× watchdogs (independent and window)
• 1× SysTick timer
• RTC with sub-second accuracy & HW calendar

Debug mode

• SWD & JTAG interfaces
• 4 Kbyte Embedded Trace Buffer

True random number generators (3 oscillators each)

96-bit unique ID

All packages are ECOPACK®2 compliant

Table 1. Device summary

Reference	Part number
STM32H743xI	STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI, STM32H743AI

Figure 3. LQFP100 pinout

1. The above figure shows the package top view.

	1	2	3	4	5	6	7	8	9	10
A	PC14- OSC32_IN (PC14)	PC13	PE2	PB9	PB7	PB4 (NJTRST)	PB3(JTDO/ TRACESWO) PA15(JTDI)	PB2	PA14(JTCK SWCLK)	PA13(JTMS SWDIO)
B	PC15- OSC32_OUT (PC15)	VBAT	PE3	PB8	PB6	PD5	PD2	PC11	PC10	PA12
C	PH0- OSC_IN(PH0)	VSS	PE4	PE1	PB5	PD6	PD3	PC12	PA9	PA11
D	PH1- OSC_OUT (PH1)	VDD	PE5	PE0	BOOT0	PD7	PD4	PD0	PA8	PA10
E	NRST	PC2_C	PE6	VSS	VSS	VSS	VCAP2	PD1	PC9	PC7
F	PC0	PC1	PC3_C	VDDLDO3	VDD	VDD33USB	PDR_ON	VCAP1	PC8	PC6
G	VSSA	PA0- WKUP(PA0)	PA4	PC4	PB2	PE10	PE14	PD15	PD11	PB15
H	VDDA	PA1	PA5	PC5	PE7	PE11	PE15	PD14	PD10	PB14
J	VSS	PA2	PA6	PB0	PE8	PE12	PB10	PB13	PD9	PD13
K	VDD	PA3	PA7	PB1	PE9	PE13	PB11	PB12	PD8	PD12

	1	2	3	4	5	6	7	8	9	10	11	12	13
A	PE4	PE2	VDD	PI6	PB6	PI2	VDD	PG10	PD5	VDD	PC12	PC10	PI0
B	PC15- OSC32_ OUT	PE3	VSS	VDDLDO3	PB8	PB4	PI3	PG11	PD6	VSS	PC11	PA14	PI1
C	PC14- OSC32_ IN	PE6	PE5	PDR_ON	PB9	PB5	PG14	PG9	PD4	PD1	PA15	VSS	VDD
D	VDD	VSS	PC13	PE1	PE0	PB7	PG13	PD7	PD3	PD0	PA13	VDDLDO2	VCAP2
E	PI11	PI7	VBAT	PF1	PF3	BOOT0	PG15	PG12	PD2	PA10	PA9	PA8	PA12
F	PI13	PI12	PF0	PF2	PF5	PF7	PB3	PG4	PC6	PC7	PC9	PC8	PA11
G	VDD	VSS	PF4	PF6	PF9	NRST	PF13	PE7	PG6	PG7	PG8	VDD50_ USB	VDD33_ USB
H	PH0- OSCIN	PH1- OSCOUT	PF10	PF8	PJ1	PA4	PF14	PE8	PG2	PG3	PG5	VSS	VDD
J	PC0	PC1	VSSA	PJ0	PA0- WKUP	PA7	PF15	PE9	PE14	PD11	PD13	PD15	PD14
K	PC3_C	PC2_C	PH4	PA1	PA6	PC4	PG0	PE13	PH10	PH12	PD9	PD10	PD12
L	VDDA	VREF+	PH5	PA5	PB1	PB2	PG1	PE12	PB10	PH11	PB13	VSS	VDD
M	VDD	VSS	PH3	VSS	PB0	PF11	VSS	PE10	PB11	VDDLDO1	VSS	PD8	PB15
N	PA2	PH2	PA3	VDD	PC5	PF12	VDD	PE11	PE15	VCAP1	VDD	PB12	PB14

Figure 6. UFBGA169 ballout

1. The above figure shows the package top view.

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
A	PE3	PE2	PE1	PE0	PB8	PB5	PG14	PG13	PB4	PB3	PD7	PC12	PA15	PA14	PA13
B	PE4	PE5	PE6	PB9	PB7	PB6	PG15	PG12	PG11	PG10	PD6	PD0	PC11	PC10	PA12
C	VBAT	PI7	PI6	PI5	VDD	PDR_ON	VDD	VDD	VDD	PG9	PD5	PD1	PI3	PI2	PA11
D	PC13	PI8	PI9	PI4	VSS	BOOT0	VSS	VSS	VSS	PD4	PD3	PD2	PH15	PI1	PA10
E	PC14- OSC32_ IN	PF0	PI10	PI11							PH13	PH14	PI0	PA9
F	PC15- OSC32_ OUT	VSS	VDD	PH2		VSS	VSS	VSS	VSS	VSS		VSS	VCAP2	PC9	PA8
G	PH0- OSC_IN	VSS	VDD	PH3		VSS	VSS	VSS	VSS	VSS		VSS	VDD	PC8	PC7
H	PH1- OSC_ OUT	PF2	PF1	PH4		VSS	VSS	VSS	VSS	VSS		VSS	VDD 3.3USB	PG8	PC6
J	NRST	PF3	PF4	PH5		VSS	VSS	VSS	VSS	VSS		VDD	VDD	PG7	PG6
K	PF7	PF6	PF5	VDD		VSS	VSS	VSS	VSS	VSS		PH12	PG5	PG4	PG3
L	PF10	PF9	PF8	VSS								PH11	PH10	PD15	PG2
M	VSSA	PC0	PC1	PC2_C	PC3_C	PB2	PG1	VSS	VSS

	Figure 8. UFBGA176+25 ballout
--	-------------------------------

Figure 9. LQFP208 pinout

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17
A	VSS	PI6	PI5	PI4	PB5	VDD LDO3	VCAP3	PK5	PG10	PG9	PD5	PD4	PC10	PA15	PI1	PI0	VSS
B	VBAT	VSS	PI7	PE1	PB6	VSS	PB4	PK4	PG11	PJ15	PD6	PD3	PC11	PA14	PI2	PH15	PH14
C	PC15- OSC32_ OUT	PC14- OSC32_ IN	PE2	PE0	PB7	PB3	PK6	PK3	PG12	VSS	PD7	PC12	VSS	PI3	PA13	VSS	VDD LDO2
D	PE5	PE4	PE3	PB9	PB8	PG15	PK7	PG14	PG13	PJ14	PJ12	PD2	PD0	PA10	PA9	PH13	VCAP2
E	NC	PI9	PC13	PI8	PE6	VDD	PDR_ ON	BOO T0	VDD	PJ13	VDD	PD1	PC8	PC9	PA8	PA12	PA11
F	NC	NC	PI10	PI11	VDD								PC7	PC6	PG8	PG7	VDD33 USB
G	PF2	NC	PF1	PF0	VDD		VSS	VSS	VSS	VSS	VSS		VDD	PG5	PG6	VSS	VDD50 USB
H	PI12	PI13	PI14	PF3	VDD		VSS	VSS	VSS	VSS	VSS		VDD	PG4	PG3	PG2	PK2
J	PH0- OSC_ OUT	PH0- OSC_IN	VSS	PF5	PF4		VSS	VSS	VSS	VSS	VSS		VDD	PK0	PK1	VSS	VSS
K	NRST	PF6	PF7	PF8	VDD		VSS	VSS	VSS	VSS	VSS		VDD	PJ11	VSS	NC	NC
L	VDDA	PC0	PF10	PF9	VDD		VSS	VSS	VSS	VSS	VSS		VDD	PJ10	VSS	NC	NC
M	VREF+	PC1	PC2	PC3	VDD								VDD	PJ9	VSS	NC	NC
N	VREF-	PH2	PA2	PA1	PA0	PJ0	VDD	VDD	PE10	VDD	VDD	VDD	PJ8	PJ7	PJ6	VSS	NC
P	VSSA	PH3	PH4	PH5	PI15	PJ1	PF13	PF14	PE9	PE11	PB10	PB11	PH10	PH11	PD15	PD14	VDD
R	PC2_C	PC3_C	PA6	VSS	PA7	PB2	PF12	VSS	PF15	PE12	PE15	PJ5	PH9	PH12	PD11	PD12	PD13
T	PA0_C	PA1_C	PA5	PC4	PB1	PJ2	PF11	PG0	PE8	PE13	PH6	VSS	PH8	PB12	PB15	PD10	PD9
U	VSS	PA3	PA4	PC5	PB0	PJ3	PJ4	PG1	PE7	PE14	VCAP1	VDD LDO1	PH7	PB13	PB14	PD8	VSS

Figure 10. TFBGA240+25 ballout

1. The above figure shows the package top view.

Name	Abbreviation	Definition
Pin name		Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
	S	Supply pin
	I	Input only pin
Pin type	I/O	Input / output pin
	ANA	Analog-only Input
	FT	5 V tolerant I/O
	TT	3.3 V tolerant I/O
	B	Dedicated BOOT0 pin
	RST	Bidirectional reset pin with embedded weak pull-up resistor
I/O structure	Option for TT and FT I/Os
	_f	I2C FM+ option
	_a	analog option (supplied by VDDA)
	_u	USB option (supplied by VDD33USB)
	_h	High Speed Low Voltage
Notes		Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.
Pin functions	Alternate functions	Functions selected through GPIOx_AFR registers
	Additional functions	Functions directly selected/enabled through peripheral registers

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-	M4	H10
-	-	-	A3	-
6	B2	6	E3	C1
-	-	-	-	J6
-	-	-	-	D2
7	A2	7	D3	D1
-	-	-	-	J7

	Table 8. STM32H743xI pin/ball definition
--	------------------------------------------

• LQFP100
• 8
• 9

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
10	-	16	B10	G2
11	-	17	G1	G3
-	-	18	G4	K2
-	-	19	F6	K1
-	-	20	H4	L3
-	-	21	G5	L2
-	-	22	H3	L1
12	C1	23	H1	G1
13	D1	24	H2	H1
14	E1	25	G6	J1
15	F1	26	J1	M2

Table 8. STM32H743xI pin/ball definition (continued)

58/226 DocID030538 Rev 3

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
23	H2	35	K4	N2
-	-	-	-	-
24	J2	36	N1	P2
-	-	-	N2	F4
-	K1	-	M1	-
-	J1	-	M7	J8
-	-	-	M3	G4
-	-	-	K3	H4
-	-	-	L3	J4
25	K2	37	N3	R2

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
26	-	38	G2	K6
-	-	-	-	L4
27	-	39	-	K4
28	G3	40	H6	N4
29	H3	41	L4	P4
30	J3	42	K5	P3
31	K3	43	J6	R3
32	G4	44	K6	N5

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
33	H4	45	N5	P5
-	-	-	N4	-
-	-	-	H12	J9
34	J4	46	M5	R5
35	K4	47	L5	R4
36	G5	48	L6	M6
-	-	-	-	-
-	-	-	J4	-
-	-	-	H5	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	49	M6	R6

	Table 8. STM32H743xI pin/ball definition (continued)
--	------------------------------------------------------

• 1
• 2
• 3
• 4
• 5
• 6
• 7

Table 8. STM32H743xI pin/ball definition (continued)

• LQFP100
• 1
• 2
• 3
• 4
• 5
• 6
• 7

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	M4	H10	-
-	-	A3	-	-
6	B2	6	E3	C1
-	-	-	J6	-
-	-	-	D2	7
7	A2	7	D3	D1
-	-	-	J7	-

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	-	K10	K12
-	-	-	-	H12
-	-	-	N11	J12
51	K8	73	N12	P12
52	J8	74	L11	P13
53	H10	75	N13	R14
54	G10	76	M13	R15

Table 8. STM32H743xI pin/ball definition (continued)

66/226 DocID030538 Rev 3

• 1
• 2
• 3
• 4
• 5
• 6
• 7

Table 8. STM32H743xI pin/ball definition (continued)

• LQFP100
• 62

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	87	H9	L15
-	-	88	H10	K15
-	-	-	-	G7
-	-	-	-	-
-	-	89	F8	K14
-	-	90	H11	K13
-	-	91	G9	J15
-	-	92	G10	J14
-	-	93	G11	H14
-	-	94	-	G12

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	-	G12	-
-	F6	95	G13	H13
-	-	-	-	-
63	F10	96	F9	H15
64	E10	97	F10	G15
65	F9	98	F12	G14
66	E9	99	F11	F14
-

Table 8. STM32H743xI pin/ball definition (continued)

• 1
• 2
• 3
• 4
• 5
• 6
• 7

Table 8. STM32H743xI pin/ball definition (continued)

| Table 8. STM32H743xl pin/ball definition | |---|---|---|---|---|---|---|---|---|---|---|---|---|---|

LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
1	A3	1	A2	A2	1	1	C3

• 1
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• 3
• 4
• 5
• 6
• 7

72/226 DocID030538 Rev 3

• 1
• 2
• 3
• 4
• 5
• 6
• 7

	Table 8. STM32H743xI pin/ball definition (continued)
--	------------------------------------------------------

Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
84	C7	117	D9	D11
85	D7	118	C9	D10
86	B6	119	A9	C11
-	-	120	-	D8
-	-	121	-	C8
87	C6	122	B9	B11
88	D6	123	D8	A11
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	H6
-	-	-	A7	-

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	124	C8	C10
-	-	125	A8	B10
-	-	126	B8	B9
-	-	127	E8	B8
-	-	128	D7	A8
-	-	129	C7	A7
-	-	130	-	D7
-	-	131	-	C7

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-	M4	H10
-	-	-	A3	-
6	B2	6	E3	C1
-	-	-	J6	-
-	-	-	D2	-
7	A2	7	D3	D1
-	-	-	J7	-

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
92	B5	136	A5	B6
93	A5	137	D6	B5
94	D5	138	E6	D6
95	B4	139	B5	A5
96	A4	140	C5	B4

Table 8. STM32H743xI pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
97	D4	141	D5	A4
98	C4	142	D4	A3
-	-	-	-	-
99	-	-	-	D5
-	F7	143	C4	C6
-	F4	-	B4	-
100	-	144	-	C5
-	-	-	-	D4
-	-	-	-	C4
-	-	-	A4	C3
-	-	-	E2	C2
-	-	-	-	H9
-	-	-	-	K9
-	-	-	-	K10

Table 8. STM32H743xI pin/ball definition (continued)

1. This ball should remain floating.

1. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.

• 3. This ball should be connected to VSS.
• 4. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits.
• 5. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits.
• 1. VREF+ pin, and consequently the internal voltage reference, are not available on the TFBGA100 package. On this package, this pin is double-bonded to VDDA which can be connected to an external reference. The internal voltage reference buffer is not available and must be kept disabled

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							Ta b le	9. Po t r	A l te a rn a	fu te t nc	io ns
		AF0	AF 1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9
	Por t	SYS	TIM 16/1 7/L 1/2/ M1/ HRT PTI IM1	SAI / 4/5/ 1/T IM3 12/ HRT IM1	LPU / TIM ART 8/ LPT / 5/H IM2 /3/4 M1/ DFS RTI DM	I2C 3/4/ USA 1/2/ / TIM RT1 15/ LPT / DFS IM2 DM /CE C	SPI 3/4/ 5/6/ 1/2/ CEC	SPI 1/ 3/I2 2/3/ SAI C4/ UAR T4/ DFS DM	6/ USA SPI 2/3/ /2/ 3/6/ RT1 T7/ SD UAR MM C1	/ 4/U SPI 6/S AI2 4/5/ 8/L ART RT/ SD PUA S PD MM C1/ IFR X	4/ FDC SAI 1/2/ TIM AN 4/Q UAD 13/1 /F MC SPI / SD C2/ LCD MM / SPD IFR X
	PA0	-	TIM H1/ TIM 2_C 2_E TR	5_C TIM H1	TIM 8_E TR	TIM 15_ BKI N	-	-	USA RT2 _ CTS _NS S	UAR T4_ TX	SD C2_ CM MM D
	PA1	-	TIM 2_C H2	TIM 5_C H2	LPT IM3 _ OU T	TIM 15_ CH 1N	-	-	USA RT2 _ RTS	UAR T4_ RX	QU AD SPI _ BK1 _IO 3
	PA2	-	TIM 2_C H3	TIM 5_C H3	LPT IM4 _ OU T	TIM 15_ CH 1	-	-	USA RT2 _ TX	SAI 2_S CK_ B	-
	PA3	-	TIM 2_C H4	TIM 5_C H4	LPT IM5 _ OU T	TIM 15_ CH 2	-	-	USA RT2 _ RX	-	LCD _B2
DocID030538 Rev 3	PA4	-	-	TIM 5_E TR	-	-	SPI SS/ I2S 1_N 1_W S	SPI SS/ I2S 3_N 3_W S	USA RT2 _ CK	SPI SS 6_N	-
	PA5	-	TIM H1/ TIM 2_C 2_E TR	-	TIM 8_ CH 1N	-	SPI CK /I2S 1_S 1_C K	-	-	SP I6_S CK	-
	PA6 A t	-	TIM 1_B KIN	TIM 3_C H1	TIM 8_B KIN	-	SPI ISO /I2S 1_M 1_S DI	-	-	SP I6_M ISO	TIM 13_ CH 1
	or P PA7	-	TIM 1_C H1N	TIM 3_C H2	8_C TIM H1 N	-	SPI OS I /I2S 1_M 1_S DO	-	-	SP I6_M OS I	CH 1 TIM 14_
	PA8	MC O1	TIM 1_C H1	HRT CH B2 IM_	TIM 8_B KIN 2	I2C 3_S CL	-	-	USA RT1 _ CK	-	-
	PA9	-	1_C TIM H2	HRT CH C1 IM_	LPU 1_ TX ART	I2C 3_S MB A	SPI CK/ I2S 2_S 2_C K	-	USA RT1 _ TX	-	CA N1_ RXF D
	PA1 0	-	TIM 1_C H3	HRT CH C2 IM_	LPU 1_ RX ART	-	-	-	USA RT1 _ RX	-	CA N1_ TXF D
	PA1 1	-	TIM 1_C H4	HRT CH D1 IM_	LPU 1_ CTS ART	-	SPI SS /I2S 2_N 2_W S	UAR T4_ RX	USA RT1 _ CTS _NS S	-	CA N1_ RX
	PA1 2	-	TIM 1_E TR	CH D2 HRT IM_	LPU 1_ RTS ART	-	SPI CK/ I2S 2_S 2_C K	UAR T4_ TX	USA RT1 _ RTS	SAI 2_F S_B	CA N1_ TX
	PA1 3	S- SW JTM DIO	-	-	-	-	-	-	-	-	-

Pin descriptions

STM32H743xI

STM32H743xI

DocID030538 Rev 3

Table 9. Port A alternate functions (continued)

Port		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
		SYS	TIM 1/2/16/1 TIM 7/LPTIM1/ HRTIM1	SAI1/TIM3/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4/ 5/HRTIM1/

Table 10. Port B alternate functions

		AF0	AF 1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF 10	AF 11	AF 12	AF 13	AF 14	AF 15
	Por t	SYS	TIM 1/2/ 16/1 7/L PTI M1/ HRT IM1	SAI 1/T IM3 / 4/5/ 12/ HRT IM1	/ LPU ART TIM 8/ LPT IM2 /3/4 /5/H RTI M1/ DFS DM	I2C 1/2/ 3/4/ USA RT1 / TIM 15/ LPT IM2 / DFS DM / CEC	SPI 1/2/ 3/4/ 5/ 6/C EC	SPI 2/3/ SAI 1 /3/I 2C4 / UAR T4/ DFS DM	SPI 2/3/ 6/ USA RT1 /2/3 /6/U ART 7/S DM MC 1	SPI 6/S AI2 / 4/U ART 4/5/ 8/L PUA RT/ SD MM C1/ SPD IFR X	SAI 4/ FDC AN 1/2/ TIM 13/1 4/ QU AD SPI / FM C/ SD MM C2/ LCD / SPD IFR X	SAI 2/4/ 8/ TIM QU AD SPI / SD MM C2/ OTG 1_H S/ OTG 2_F S/ LCD	I2C 4/ UAR T7/ SW PM I1/ TIM 1/8/ DFS DM / SD MM C2/ MD IOS / ETH	1/8/ C TIM FM /SD MM C1/ MD IOS / OTG 1_F S/ LCD	TIM 1/D CM I/LC D/ CO MP	UAR T5/ LCD	SYS
	PB0	-	TIM 1_C H2N	TIM 3_C H3	8_C H2 N TIM	-	-	DFS _CK OU DM T	-	UAR T4_ CTS	LCD _R3	OTG HS ULP 1 I_D	ETH II_ RXD _M 2	-	-	LCD _G 1	EVE NT- OU T
	PB1	-	TIM 1_C H3N	TIM 3_C H4	TIM 8_C H3 N	-	-	DFS DM _ DAT IN1	-	-	LCD _R6	OTG HS ULP I_D 2	ETH II_ RXD _M 3	-	-	LCD _G0	EVE NT- OU T
	PB2	-	-	SA I1_D 1	-	DFS DM _ CK IN1	-	SAI 1_S D_A	3_ MO SPI SI/I 2S3 _ SDO	SAI 4_S D_ A	QU AD SPI _ CLK	SAI 4_D 1	ETH TX ER	-	-	-	EVE NT- OU T
	PB3	JTD RA CES O/T WO	TIM 2_C H2	HRT IM_ FLT 4	-	-	SPI CK/ I2S 1_S 1_C K	SPI CK/ I2S 3_S 3_C K	-	SPI 6_S CK	SD MM C2_ D2	-	UAR T7_ RX	-	-	-	EVE NT- OU T
B t or P	PB4	NJT RST	TIM 16_ BKI N	TIM 3_C H1	HRT EE V6 IM_	-	SPI / I2S 1_M ISO 1_S DI	SPI / I2S 3_M ISO 3_S DI	SPI I 2S2 2_N SS/ _W S	SPI 6_ MIS O	SD MM C2_ D3	-	UAR T7_ TX	-	-	-	EVE NT- OU T
	PB5	-	TIM 17_ BKI N	TIM 3_C H2	HRT IM_ EEV 7	I2C 1_S MB A	SPI I/ I2S OS 1_M 1_S DO	I2C 4_S MB A	SPI I/ I2S OS 3_M 3_S DO	SPI 6_ MO SI	CA N2_ RX	OTG HS ULP I_D 7	S_ OU ETH _PP T	C_ SDC FM KE1	DC MI_ D1 0	UAR T5_ RX	EVE NT- OU T
	PB6	-	TIM 16_ 1 N CH	TIM 4_C H1	HRT IM_ EEV 8	I2C 1_S CL	HD MI_ CEC	I2C 4_S CL	USA RT1 _ TX	LPU 1_ TX ART	CA N2_ TX	QU AD SPI _ BK1 _NC S	DFS DM _ DAT IN5	FM C_S E 1 DN	DC MI_ D5	UAR T5_ TX	EVE NT- OU T
	PB7	-	TIM 17_ 1 N CH	TIM 4_C H2	HRT IM_ EEV 9	I2C 1_S DA	-	I2C 4_S DA	USA RT1 _ RX	LPU 1_ RX ART	CA N2_ TXF D	-	DFS DM _ CK IN5	FM C_N L	MI_ VSY DC NC	-	EVE NT- OU T
	PB8	-	CH TIM 16_ 1	4_C TIM H3	DFS DM _ CK IN7	I2C 1_S CL	-	I2C 4_S CL	SD C1_ CK MM IN	UAR T4_ RX	CA N1_ RX	SD MM C2_ D4	ETH II_ TXD _M 3	SD MM C1_ D4	DC MI_ D6	LCD _B6	EVE NT- OU T

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Unless otherwise specified, the parameters given in Table 84 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 23: General operating conditions.

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
VDDA	Analog power supply	-		1.62	-	3.6
		VDDA ≥ 2 V		2	-	VDDA
VREF+	Positive reference voltage	VDDA< 2 V		VDDA			V
VREF-	Negative reference voltage	-		VSSA
	ADC clock frequency	2 V ≤ VDDA ≤ 3.3 V	BOOST = 1	-	-	36	MHz
fADC			BOOST = 0	-	-	20
		16-bit resolution		-	-	3.60
	Sampling rate for Fast channels, BOOST = 1, fADC = 36 MHz	14-bit resolution		-	-	4.00
		12-bit resolution		-	-	4.50
		10-bit resolution 8-bit resolution		-	-	5.00 6.00
	Sampling rate for Fast channels, BOOST = 0, fADC = 20 MHz	16-bit resolution		-	-	2.00
		14-bit resolution		-	-	2.20
fS		12-bit resolution		-	-	2.50	MSPS
		10-bit resolution 8-bit resolution		-	-	2.80 3.30
	Sampling rate for Fast channels, BOOST = 0, fADC = 10 MHz	16-bit resolution		-	-	1.00
		14-bit resolution		-	-	1.00
		12-bit resolution		-	-	1.00
		10-bit resolution 8-bit resolution		-	-	1.00 1.00

Symbol	Parameter	Conditions	Min Typ Max			Unit
		fADC = 36 MHz	-	-	3.6	MHz
fTRIG	External trigger frequency	16-bit resolution	-	-	10	1/fADC
VAIN(2)	Conversion voltage range	-	0	- VREF+		V
VCMIV	Common mode input voltage	-	VREF/2- VREF/2 10%		VREF/2+ 10%
RAIN	External input impedance	See Equation 1 for details	-	- 50		㏀
CADC	Internal sample and hold capacitor	-	- 4		-	pF
tADCREG_ STUP	ADC LDO startup time	-	- 5		10	μs
tSTAB	ADC power-up time	LDO already started	1		conversion cycle
tCAL	Offset and linearity calibration time	-	16384
tOFFCAL	Offset calibration time	-	1280
	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 00	1.5	2	2.5	1/fADC
tLATR		CKMODE = 01 CKMODE = 10 CKMODE = 11	-	-	2 2.25 2.125
	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 00	2.5	3	3.5
tLATRINJ		CKMODE = 01	-	-	3
		CKMODE = 10	-	-	3.25
		CKMODE = 11	-	-	3.125
tS	Sampling time	-	1.5	-	640.5
tCONV	Total conversion time (including sampling time) Table 84. ADC characteristics(1) (continued)	N-bit resolution	tS + 0.5 + N/2 (9 to 648 cycles in 14-bit mode)
--	----------------------------------------------	--
--	----------------------------------------------	--

1. Guaranteed by design.

2. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.

Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics, Table 21: Current characteristics, and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbols	Ratings	Min	Max	Unit
VDDX - VSS	External main supply voltage (including VDD, VDDLDO, VDDA, VDD33USB, VBAT)	-0.3	4.0	V
VIN(2)	Input voltage on FT_xxx pins	VSS-0.3	Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4)	V
	Input voltage on TT_xx pins	VSS-0.3	4.0	V
	Input voltage on BOOT0 pin	VSS	9.0	V
	Input voltage on any other pins	VSS-0.3	4.0	V
∆VDDX	Variations between different VDDX power pins of the same domain	-	50	mV
VSSx-VSS	Variations between all the different ground pins	-	50	mV

Table 20. Voltage characteristics (1)

1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 57 for the maximum allowed injected current values.

3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.

4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.

Symbols	Ratings	Max	Unit
ΣIVDD	Total current into sum of all VDD power lines (source)(1)	620
ΣIVSS	Total current out of sum of all VSS ground lines (sink)(1)	620
IVDD	Maximum current into each VDD power pin (source)(1)	100
IVSS	Maximum current out of each VSS ground pin (sink)(1)	100
IIO	Output current sunk by any I/O and control pin	20
ΣI(PIN)	Total output current sunk by sum of all I/Os and control pins(2)	140	mA
	Total output current sourced by sum of all I/Os and control pins(2)	140
IINJ(PIN)(3)(4)	Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5	-5/+0
	Injected current on PA4, PA5	-0/0
ΣIINJ(PIN)	Total injected current (sum of all I/Os and control pins)(5)	±25

Table 21. Current characteristics

1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range.

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

2. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

3. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.

4. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 22. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	-65 to +150	°C
TJ	Maximum junction temperature	125	°C

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	-65 to +150	°C
TJ	Maximum junction temperature	125	°C