STM32H743ZIT6
The STM32H743ZIT6 is an electronic component from STMicroelectronics. View the full STM32H743ZIT6 datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
Manufacturer
STMicroelectronics
Category
Integrated Circuits (ICs)
Package
144-LQFP
Lifecycle
Active
Key Specifications
| Parameter | Value |
|---|---|
| Connectivity | CANbus, EBI/EMI, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, SWPMI, UART/USART, USB OTG |
| Core Processor | ARM® Cortex®-M7 |
| Core Size | 32-Bit |
| Data Converters | A/D 36x16b; D/A 2x12b |
| DigiKey Programmable | Not Verified |
| DigiKey Programmable | Not Verified |
| DigiKey Programmable | Not Verified |
| Mounting Type | Surface Mount |
| Number of I/O | 114 |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Oscillator Type | Internal |
| Oscillator Type | Internal |
| Oscillator Type | Internal |
| Package / Case | 144-LQFP |
| Packaging | Tray |
| Peripherals | Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT |
| Flash Memory Size | 2MB (2M x 8) |
| Program Memory Type | FLASH |
| RAM Size | 1M x 8 B |
| Clock Speed | 480MHz |
| Standard Pack Qty | 360 |
| Supplier Device Package | 144-LQFP (20x20) |
| Supplier Device Package | 144-LQFP (20x20) |
| Supplier Device Package | 144-LQFP (20x20) |
| Supply Voltage | 1.62V ~ 3.6V |
Overview
Part: STM32H743xI — STMicroelectronics
Type: ARM Cortex-M7 Microcontroller
Description: 32-bit ARM Cortex-M7 MCU running at up to 400 MHz with double-precision FPU, up to 2 MB Flash, 1 MB RAM, and a rich set of communication and analog interfaces.
Operating Conditions:
- Supply voltage: 1.62 to 3.6 V
- Max CPU frequency: 400 MHz
Absolute Maximum Ratings:
Key Specs:
- Core: 32-bit Arm Cortex-M7 with double-precision FPU
- Max CPU frequency: 400 MHz
- Flash memory: Up to 2 Mbytes with read-while-write support
- RAM: 1 Mbyte (192 Kbytes TCM, 864 Kbytes user SRAM, 4 Kbytes Backup SRAM)
- I/O ports: Up to 168 with interrupt capability, up to 164 5 V-tolerant
- ADC resolution: 16-bit max (14 bits 4 MSPS, 16 bits 3.6 MSPS)
- DAC resolution: 12-bit (1 MHz)
- Low-power consumption: Down to 4 μA total current consumption
Features:
- L1 cache: 16 Kbytes data, 16 Kbytes instruction
- Dual mode Quad-SPI memory interface up to 133 MHz
- Flexible external memory controller (SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash) up to 133 MHz
- 4 DMA controllers (1 MDMA, 2 dual-port DMAs, 1 basic DMA)
- Up to 35 communication peripherals (I2C, USART/UART, LPUART, SPI/I2S, SAI, SPDIFRX, SWPMI, MDIO, SD/SDIO/MMC, CAN FD, USB OTG, Ethernet MAC, HDMI-CEC, Camera interface)
- 11 analog peripherals (temperature sensor, DACs, comparators, operational amplifiers, DFSDM, ADCs)
- Graphics: LCD-TFT controller up to XGA, Chrom-ART graphical hardware Accelerator™, Hardware JPEG Codec
- Up to 22 timers and watchdogs (high-resolution, 32-bit, 16-bit advanced motor control, 16-bit general-purpose, 16-bit low-power, watchdogs, SysTick, RTC)
- Security features: ROP, PC-ROP, active tamper
- Debug mode: SWD & JTAG interfaces, 4 Kbyte Embedded Trace Buffer
- True random number generators
Applications:
Package:
- TFBGA240+25 (14x14 mm)
- TFBGA100 (8x8 mm)
- UFBGA176+25 (10x10 mm)
- UFBGA169 (7x7 mm)
- LQFP208 (28x28 mm)
- LQFP176 (24x24 mm)
- LQFP144 (20x20 mm)
- LQFP100 (14x14 mm)
Pin Configuration
Figure 3. LQFP100 pinout
- The above figure shows the package top view.
93
Figure 4. TFBGA100 pinout
- The above figure shows the package top view.
Figure 5. LQFP144 pinout
- The above figure shows the package top view.
93
Electrical Characteristics
Unless otherwise specified, the parameters given in Table 84 are derived from tests performed under the ambient temperature, f PCLK2 frequency and V DDA supply voltage conditions summarized in Table 23: General operating conditions .
Table 84. ADC characteristics (1)
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit | |
|---|---|---|---|---|---|---|---|
| V DDA | Analog power supply | - | - | 1.62 | - | 3.6 DDA | V |
| V REF+ | Positive reference voltage | V DDA ≥ 2 V | V DDA ≥ 2 V | 2 | - | V | V |
| V REF+ | Positive reference voltage | V DDA < 2 V | V DDA < 2 V | V DDA | V DDA | V DDA | V |
| V REF- | Negative reference voltage | - | - | V SSA | V SSA | V SSA | V |
| f ADC | ADC clock frequency | 2 V ≤ V DDA ≤ 3.3 V | BOOST=1 | - | - | 36 | MHz |
| f ADC | ADC clock frequency | 2 V ≤ V DDA ≤ 3.3 V | BOOST = 0 | - | - | 20 | MHz |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz | 16-bit resolution | 16-bit resolution | - | - | 3.60 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz | 14-bit resolution | 14-bit resolution | - | - | 4.00 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz | 12-bit resolution | 12-bit resolution | - | - | 4.50 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz | 10-bit resolution | 10-bit resolution | - | - | 5.00 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz | 8-bit resolution | 8-bit resolution | 6.00 | MSPS | ||
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 16-bit resolution | 16-bit resolution | - | - | 2.00 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 14-bit resolution | 14-bit resolution | - | - | 2.20 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 12-bit resolution | 12-bit resolution | - | - | 2.50 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 10-bit resolution | 10-bit resolution | - | - | 2.80 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 8-bit resolution | 8-bit resolution | 3.30 | MSPS | ||
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 10 MHz | 16-bit resolution | 16-bit resolution | - | - | 1.00 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 10 MHz | 14-bit resolution | 14-bit resolution | - | - | 1.00 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 10 MHz | 12-bit resolution | 12-bit resolution | - | - | 1.00 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 10 MHz | 10-bit resolution | 10-bit resolution | - | - | 1.00 | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 10 MHz | 8-bit resolution | 8-bit resolution | 1.00 | MSPS |
Table 84. ADC characteristics (1)
196
Table 84. ADC characteristics (1) (continued)
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| f TRIG | External trigger frequency | f ADC = 36 MHz | - | - | 3.6 | MHz |
| f TRIG | External trigger frequency | 16-bit resolution | - | - | 10 | 1/f ADC |
| V AIN (2) | Conversion voltage range | - | 0 | - | V REF+ | V |
| V CMIV | Common mode input voltage | - | V REF /2 - 10% | V REF /2 | V REF /2+ 10% | |
| R AIN | External input impedance | See Equation 1 for details | - | - | 50 | kΩ |
| C ADC | Internal sample and hold capacitor | - | - | 4 | - | pF |
| t ADCREG_ STUP | ADC LDO startup time | - | - | 5 | 10 | μs |
| t STAB | ADC power-up time | LDO already started | 1 | 1 | 1 | conversion cycle |
| t CAL | Offset and linearity calibration time | - | 16384 | 16384 | 16384 | 1/f ADC |
| t OFF_CAL | Offset calibration time | - | 1280 | 1280 | 1280 | 1/f ADC |
| t LATR | Trigger conversion latency for regular and injected channels without aborting the conversion | CKMODE = 00 | 1.5 | 2 | 2.5 | 1/f ADC |
| t LATR | Trigger conversion latency for regular and injected channels without aborting the conversion | CKMODE = 01 | - | - | 2 | 1/f ADC |
| t LATR | Trigger conversion latency for regular and injected channels without aborting the conversion | CKMODE = 10 | 2.25 | 1/f ADC | ||
| t LATR | Trigger conversion latency for regular and injected channels without aborting the conversion | CKMODE = 11 | 2.125 | 1/f ADC | ||
| t LATRINJ | Trigger conversion latency for regular and injected channels when a regular conversion is aborted | CKMODE = 00 | 2.5 | 3 | 3.5 | 1/f ADC |
| t LATRINJ | Trigger conversion latency for regular and injected channels when a regular conversion is aborted | CKMODE = 01 | - | - | 3 | 1/f ADC |
| t LATRINJ | Trigger conversion latency for regular and injected channels when a regular conversion is aborted | CKMODE = 10 | - | - | 3.25 | 1/f ADC |
| t LATRINJ | Trigger conversion latency for regular and injected channels when a regular conversion is aborted | CKMODE = 11 | - | - | 3.125 | 1/f ADC |
| t S | Sampling time | - | 1.5 | - | 640.5 | 1/f ADC |
| t CONV | Total conversion time (including sampling time) | N-bit resolution | t S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode) | t S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode) | t S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode) |
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics , Table 21: Current characteristics , and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 20. Voltage characteristics (1)
| Symbols | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DDX - V SS | External main supply voltage (including V DD , V DDLDO , V DDA , V DD33USB , V BAT ) | - 0.3 | 4.0 | V |
| V IN (2) | Input voltage on FT_xxx pins | V SS - 0.3 | Min(V DD , V DDA , V DD33USB , V BAT ) +4.0 (3)(4) | V |
| Input voltage on TT_xx pins | V SS -0.3 | 4.0 | V | |
| Input voltage on BOOT0 pin | V SS | 9.0 | V | |
| Input voltage on any other pins | V SS -0.3 | 4.0 | V | |
| \ | ∆ V DDX \ | Variations between different V DDX power pins of the same domain | - | |
| \ | V SSx -V SS \ | Variations between all the different ground pins | - |
- VIN maximum must always be respected. Refer to Table 57 for the maximum allowed injected current values.
- This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
- To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 21. Current characteristics
Table 21. Current characteristics
| Symbols | Ratings | Max | Unit |
|---|---|---|---|
| Σ IV DD | Total current into sum of all V DD power lines (source) (1) | 620 | mA |
| Σ IV SS | Total current out of sum of all V SS ground lines (sink) (1) | 620 | mA |
| IV DD | Maximum current into each V DD power pin (source) (1) | 100 | mA |
| IV SS | Maximum current out of each V SS ground pin (sink) (1) | 100 | mA |
| I IO | Output current sunk by any I/O and control pin | 20 | mA |
| Σ I (PIN) | Total output current sunk by sum of all I/Os and control pins (2) | 140 | mA |
| Σ I (PIN) | Total output current sourced by sum of all I/Os and control pins (2) | 140 | mA |
| I INJ(PIN) (3)(4) | Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5 | - 5/+0 | mA |
| I INJ(PIN) (3)(4) | Injected current on PA4, PA5 | - 0/0 | mA |
| Σ I INJ(PIN) | Total injected current (sum of all I/Os and control pins) (5) | ±25 | mA |
- All main power (V DD , V DDA , V DD33USB ) and ground (V SS , V SSA ) pins must always be connected to the external power supplies, in the permitted range.
- This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
- Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
- A positive injection is induced by V IN >V DD while a negative injection is induced by V IN <V SS . I INJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.
- When several inputs are submitted to a current injection, the maximum ∑ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).
Table 22. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | - 65 to +150 | °C |
| T J | Maximum junction temperature | 125 | °C |
196
Thermal Information
The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:
T J max = T A max + (P D max × Θ JA )
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at www.st.com. ECOPACK ® is an ST trademark.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| STM32H743AI | STMicroelectronics | — |
| STM32H743BI | STMicroelectronics | — |
| STM32H743II | STMicroelectronics | — |
| STM32H743VI | STMicroelectronics | — |
| STM32H743XI | STMicroelectronics | — |
| STM32H743XL | STMicroelectronics | TFBGA |
| STM32H743ZI | STMicroelectronics | — |
Get structured datasheet data via API
Get started free