STM32C011F6U6TR

Part: STM32C011x4/x6

Type: ARM Cortex-M0+ 32-bit MCU

Key Specs:

• Core Frequency: up to 48 MHz
• Flash Memory: up to 32 Kbytes
• SRAM: 6 Kbytes
• Voltage Range: 2.0 V to 3.6 V
• Operating Temperature: -40°C to 125°C
• ADC Resolution: 12-bit
• ADC Conversion Time: 0.4 μs
• SPI Speed: 24 Mbit/s
• I²C Speed: 1 Mbit/s

Features:

• Arm® 32-bit Cortex®-M0+ CPU
• Up to 32 Kbytes of flash memory with protection and securable area
• 6 Kbytes of SRAM with hardware parity check
• CRC calculation unit
• Power-on / power-down reset (POR/PDR)
• Programmable brownout reset (BOR)
• Low-power modes: Sleep, Stop, Standby, Shutdown
• Clock management: 4 to 48 MHz crystal oscillator, 32 kHz crystal oscillator, Internal 48 MHz RC oscillator (±1 %), Internal 32 kHz RC oscillator (±5 %)
• Up to 18 fast I/Os, all 5 V-tolerant
• 3-channel DMA controller with flexible mapping
• 12-bit, 0.4 μs ADC (up to 13 ext. channels), Conversion range: 0 to 3.6 V
• 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
• Calendar RTC

• Includes ST state-of-the-art patented technology
• Core: Arm^® 32-bit Cortex^®-M0+ CPU, frequency up to 48 MHz
• -40°C to 85°C/105°C/125°C operating temperature
• Memories
  • Up to 32 Kbytes of flash memory with protection and securable area
  • 6 Kbytes of SRAM with hardware parity check
• · CRC calculation unit
• Reset and power management
  • Voltage range: 2.0 V to 3.6 V
  • Power-on / power-down reset (POR/PDR)
  • Programmable brownout reset (BOR)
  • Low-power modes: Sleep, Stop, Standby, Shutdown
• · Clock management
  • 4 to 48 MHz crystal oscillator
  • 32 kHz crystal oscillator with calibration
  • Internal 48 MHz RC oscillator (±1 %)
  • Internal 32 kHz RC oscillator (±5 %)
• Up to 18 fast I/Os
  • All mappable on external interrupt vectors
  • All 5 V-tolerant
• 3-channel DMA controller with flexible mapping
• 12-bit, 0.4 μs ADC (up to 13 ext. channels)
  • Conversion range: 0 to 3.6 V
• 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
• · Calendar RTC with alarm

• · Communication interfaces
  • One I²C-bus interface supporting Fastmode Plus (1 Mbit/s) with extra current sink; supporting SMBus/PMBus™ and wake-up from Stop mode
  • Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wake-up feature
  • One SPI (24 Mbit/s) with 4- to 16-bit programmable bitframe, multiplexed with I²S interface; two extra SPIs through USARTs
• Development support: serial wire debug (SWD)
• SESIP3 and PSA Level 3 target certification
• All packages ECOPACK 2 compliant

Table 1. Device summary

Reference	Part number
STM32C011x4	STM32C011F4, STM32C011J4
STM32C011x6	STM32C011F6, STM32C011J6, STM32C011D6

Contents STM32C011x4/x6

Figure 3. STM32C011JxM SO8N pinout

Figure 4. STM32C011DxY WLCSP12 ballout

Figure 5. STM32C011FxP TSSOP20 pinout

Figure 6. STM32C011FxU UFQFPN20 pinout

Table 11. Terms and symbols used in the pin assignment table

	Column	Symbol	Definition
	Pin name	parenthesis under the pin name.	Terminal name corresponds to its by-default function at reset, unless otherwise specified in
		S	Supply pin
	Pin type	I	Input only pin
		I/O	Input / output pin
		FT	5 V tolerant I/O
		RST	Reset pin with embedded weak pull-up resistor
			Options for FT I/Os
		_f	I/O, Fm+ capable
	I/O structure	_a	I/O, with analog switch function
	Note		Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Pin	Alternate functions	Functions selected through GPIOx_AFR registers
functions	Additional functions		Functions directly selected/enabled through peripheral registers

Table 12. Pin assignment and description

| | Pin | |------|---------|---------|----------|--------------------------------------|----------|---------------|------|----------------------------------------------------------------------------------------------------------|-------------------------| | SO8N | WLCSP12 | TSSOP20 | UFQFPN20 | Pin name
(function upon
reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | 1 | B3 | 2 | 20 | PC14-OSCX_IN
(PC14) | I/O | FT_f | - | USART1_TX, TIM1_ETR, TIM1_BKIN2, IR_OUT,
USART2_RTS_DE_CK, TIM17_CH1, TIM3_CH2,
I2C1_SDA, EVENTOUT | OSCX_IN | | 8 | A4 | 3 | 1 | PC15-
OSCX_OUT
(PC15) | I/O | FT | - | OSC32_EN, OSC_EN, TIM1_ETR, TIM3_CH3 | OSCX_OUT | | 2 | C4 | 4 | 2 | VDD/VDDA | S | - | - | - | - | | 3 | E4 | 5 | 3 | VSS/VSSA | S | - | - | - | - | | 4 | F3 | 6 | 4 | PF2-NRST | I/O | RST,
FT | (1) | MCO, TIM1_CH4 | NRST | | 4 | F3 | 7 | 5 | PA0 | I/O | FT_a | - | USART2_CTS, TIM16_CH1, USART1_TX, TIM1_CH1 | ADC_IN0, WKUP1 |

Table 12. Pin assignment and description (continued)

| | | Pin | |------|---------|---------|----------|--------------------------------------|----------|---------------|------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------| | SO8N | WLCSP12 | TSSOP20 | UFQFPN20 | Pin name
(function upon
reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | 4 | F3 | 8 | 6 | PA1 | I/O | FT_a | - | SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK,
TIM17_CH1, USART1_RX, TIM1_CH2, I2C1_SMBA,
EVENTOUT | ADC_IN1 | | 4 | F3 | 9 | 7 | PA2 | I/O | FT_a | - | SPI1_MOSI/I2S1_SD, USART2_TX, TIM16_CH1N,
TIM3_ETR, TIM1_CH3 | ADC_IN2,
WKUP4,LSCO | | - | F1 | 10 | 8 | PA3 | I/O | FT_a | - | USART2_RX, TIM1_CH1N, TIM1_CH4, EVENTOUT | ADC_IN3 | | - | F1 | 11 | 9 | PA4 | I/O | FT_a | - | SPI1_NSS/I2S1_WS, USART2_TX, TIM1_CH2N,
TIM14_CH1, TIM17_CH1N, EVENTOUT | ADC_IN4, RTC_TS,
RTC_OUT1, WKUP2 | | - | F1 | 12 | 10 | PA5 | I/O | FT_a | - | SPI1_SCK/I2S1_CK, USART2_RX, TIM1_CH3N,
TIM1_CH1, EVENTOUT | ADC_IN5 | | - | F1 | 13 | 11 | PA6 | I/O | FT_a | - | SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN,
TIM16_CH1 | ADC_IN6 | | - | E2 | 14 | 12 | PA7 | I/O | FT_a | - | SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N,
TIM14_CH1, TIM17_CH1 | ADC_IN7 | | 5 | D1 | 15 | 13 | PA8 | I/O | FT_a | - | MCO, USART2_TX, TIM1_CH1, EVENTOUT,
SPI1_NSS/I2S1_WS, TIM1_CH2N, TIM1_CH3N,
TIM3_CH3, TIM3_CH4, TIM14_CH1, USART1_RX, MCO2 | ADC_IN8 | | - | - | - | - | PA9 | I/O | FT_f | (2) | MCO, USART1_TX, TIM1_CH2, TIM3_ETR, I2C1_SCL,
EVENTOUT | - | | - | - | - | - | PA10 | I/O | FT_f | (2) | USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN,
I2C1_SDA, EVENTOUT | - | | 5 | D1 | 16 | 14 | PA11 [PA9] | I/O | FT_a | (2) | SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4,
TIM1_BKIN2 | ADC_IN11 | | 6 | E2 | 17 | 15 | PA12 [PA10] | I/O | FT_a | (2) | SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK,
TIM1_ETR, I2S_CKIN | ADC_IN12 | | 7 | B1 | 18 | 16 | PA13 | I/O | FT_a | (3) | SWDIO, IR_OUT, TIM3_ETR, USART2_RX, EVENTOUT | ADC_IN13 | | 8 | C2 | 19 | 17 | PA14-BOOT0 | I/O | FT_a | | (3) SWCLK, USART2_TX, EVENTOUT, SPI1_NSS/I2S1_WS,
USART2_RX, TIM1_CH1, MCO2, USART1_RTS_DE_CK | ADC_IN14, BOOT0 | | 8 | A2 | 20 | 18 | PB6 | I/O | FT_f | - | USART1_TX, TIM1_CH3, TIM16_CH1N, TIM3_CH3,
USART1_RTS_DE_CK, USART1_CTS, I2C1_SCL,
I2C1_SMBA, SPI1_MOSI/I2S1_SD,
SPI1_MISO/I2S1_MCK, SPI1_SCK/I2S1_CK, TIM1_CH2,
TIM3_CH1, TIM3_CH2, TIM16_BKIN, TIM17_BKIN | WKUP3 | | 1 | D3 | 1 | 19 | PB7 | I/O | FT_f | - | USART1_RX, TIM1_CH4, TIM17_CH1N, TIM3_CH4,
I2C1_SDA, EVENTOUT, USART2_CTS, TIM16_CH1,
TIM3_CH1, I2C1_SCL | RTC_REFIN |

^1. RST I/O structure when the PF2-NRST pin is configured as reset (input or input/output mode), FT I/O structure when the PF2- NRST pin is configured as GPIO

^2. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.

^3. Upon reset, this pin is configured as SWD alternate function, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
PA0	-	USART2_CTS	TIM16_CH1	-	USART1_TX	TIM1_CH1	-	-
PA1	SPI1_SCK/I2S1_ CK	USART2_RTS_ DE_CK	TIM17_CH1	-	USART1_RX	TIM1_CH2	I2C1_SMBA	EVENTOUT
PA2	SPI1_MOSI/I2S1 _SD	USART2_TX	TIM16_CH1N	TIM3_ETR	-	TIM1_CH3	-	-
PA3	-	USART2_RX	TIM1_CH1N	-	-	TIM1_CH4	-	EVENTOUT
PA4	SPI1_NSS/I2S1_ WS	USART2_TX	TIM1_CH2N	-	TIM14_CH1	TIM17_CH1N	-	EVENTOUT
PA5	SPI1_SCK/I2S1_ CK	USART2_RX	TIM1_CH3N	-	-	TIM1_CH1	-	EVENTOUT
PA6	SPI1_MISO/I2S1 _MCK	TIM3_CH1	TIM1_BKIN	-	-	TIM16_CH1	-	-
PA7	SPI1_MOSI/I2S1 _SD	TIM3_CH2	TIM1_CH1N	-	TIM14_CH1	TIM17_CH1	-	-
PA8	MCO	USART2_TX	TIM1_CH1	-	-	-	-	EVENTOUT
PA9	MCO	USART1_TX	TIM1_CH2	TIM3_ETR	-	-	I2C1_SCL	EVENTOUT
PA10	-	USART1_RX	TIM1_CH3	MCO2	-	TIM17_BKIN	I2C1_SDA	EVENTOUT
PA11	SPI1_MISO/I2S1 _MCK	USART1_CTS	TIM1_CH4	-	-	TIM1_BKIN2	-	-
PA12	SPI1_MOSI/I2S1 _SD	USART1_RTS_ DE_CK	TIM1_ETR	-	-	I2S_CKIN	-	-
PA13	SWDIO	IR_OUT	-	TIM3_ETR	USART2_RX	-	-	EVENTOUT
PA14	SWCLK	USART2_TX	-	-	-	-	-	EVENTOUT

	ζ		J
1	Ć	1	)
	_		Ĺ
,	c	,	2
1	Č	χ	2
1	C	)	)
1	C	)	)
	_
	1	٩	J
1	(	D
	<
	C	5	1

STM32C011x4/x6
A F 9 1_ W 2 S C T I M 1_ H 2 N S 1_ W 2 U S A R T 2_ R X
-----------------------------------------------------------------------------------------------------------------------------------
A F 1
X T I M 1_ C H 3
X T I M 1_ C H 4
Port
------
PB6
PB7

	S D _	S P I 1_ M I S O / I 2 S 1 M C K _	S P I 1_ S 1_ C C K / I 2 S K	T I M 1_ C H 2	T I M 3_ C H 1	T I M 3_ C H 2	T I M 1 6_ B K I N	T I M 1 7_ B K I N
P B 7	-	U S A R T 2_ C T S	T I M 1 6_ C H 1	T I M 3_ C H 1	-	-	I 2 C 1_ S C L	-

Table 17. Port C alternate function mapping (AF0 to AF7)

Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
P C 1 4	U S A R T 1_ T X	T I M 1_ E T R	T I M 1_ B K I N 2	-	-	-	-	-
P C 1 5	O S C 3 2_ E N	O S C_ E N	T I M 1_ E T R	T I M 3_ C H 3	-	-	-	-

Table 18. Port C alternate function mapping (AF8 to AF15)

Po t r	A F 8	A F 9	A F 1 0	A F 1 1	A F 1 2	A F 1 3	A F 1 4	A F 1 5
P C 1 4	I R_ O U T	U S A S_ D R T 2_ R T E_ C K	T I M 1 C H 1 7_	T I M 3_ C H 2	-	-	I 2 C 1_ S D A	E V E N T O U T

Table 19. Port F alternate function mapping

Po	A	A	A	A	A	A	A	A
t	F	F	F	F	F	F	F	F
r	0	1	2	3	4	5	6	7
P F 2	O M C	T I M 1_ C H 4	-	-	-	-	-	-

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored.

Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 7.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8.

5.1.6 Power supply scheme

Figure 9. Power supply scheme MSv57328V1 VDD RTC Kernel logic (CPU, digital and memories) Level shifter IO logic IN OUT Regulator 1 x 100 nF GPIOs + 1 x 4.7 μF VDD/VDDA VCORE VDDIO ADC VREF+ VREF-VSS/VSSA VSS VSSA VDDA VDD

Caution: Power supply pin pairs (VDD/VDDA versus VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

5.1.7 Current consumption measurement

MS55840V1 IDD VDD (VDDA) VDD/VDDA

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 20, Table 21 and Table 22 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.

All voltages are defined with respect to VSS.

Table 20. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
VDD	External supply voltage	- 0.3	4.0	V
VIN(1)	Input voltage on pin	- 0.3	VDDIO1 + 4.0(2)(3)	V

• 1. VIN maximum must always be respected. Refer to Table 21 for the maximum allowed injected current values.
• 1. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
• 1. When an FT_a pin is used by an analog peripheral such as ADC, the maximum VIN is 4 V.

Table 21. Current characteristics

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)	100	mA
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)	100	mA
	Output current sunk by any I/O and control pin	20
IIO(PIN)	Output current sourced by any I/O and control pin	20	mA
	Total output current sunk by sum of all I/Os and control pins(1)	80
∑I(PIN)	Total output current sourced by sum of all I/Os and control pins(1)	80	mA
IINJ(PIN)(1)(2)	Injected current on a FT_xx pin	-5 / NA	mA
∑IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(3)	-25	mA

^1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

Table 22. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	130	°C

^2. A positive injection is induced by VIN > VDDIO1 while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.

^3. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

5.3 Operating conditions

5.3.1 General operating conditions

Table 23. General operating conditions

Symbol	Parameter	Conditions	Min	Max	Unit
VDD	Standard operating voltage	-	2.0(1)	3.6	V
VIN	I/O input voltage	-	-0.3	Min (VDDIO1 + 3.6, 5.5)(2)	V
fHCLK	AHB clock frequency	-	-	48	MHz
fPCLK	APB clock frequency	-	-	48	MHz
		Suffix 6(4)	-40	85
TA	Ambient temperature(3)	(4) Suffix 7	-40	105	°C
		Suffix 3(4)	-40	125
		Suffix 6(4)	-40	105
TJ	Junction temperature	(4) Suffix 7	-40	125	°C
		Suffix 3(4)	-40	130
1. When RESET is released, functionality is guaranteed down to VPDR.

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 24 are derived from tests performed under the ambient temperature condition summarized in Table 23.

Table 24. Operating conditions at power-up / power-down

Symbol	Parameter	Min	Max	Unit
	VDD rise time rate	0	∞	µs/V
tVDD	VDD fall time rate	10	∞

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 25 are derived from tests performed under the ambient temperature conditions summarized in Table 23.

Table 25. Embedded reset and power control block characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tRSTTEMPO(1)	POR temporization when VDD crosses VPOR	VDD rising	-	270	500	µs
VPOR(1)	Power-on reset threshold	-	1.9	1.94	1.98	V

^2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.

^3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.6: Thermal characteristics.

^4. Temperature range digit in the order code. See Section 7: Ordering information.

Table 25. Embedded reset and power control block characteristics (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VPDR(1)	Power-down reset threshold	-	1.88	1.92	1.96	V
	Brownout reset threshold 1	VDD rising	2.05	2.10	2.18	V
VBOR1		VDD falling	1.95	2.00	2.08
	Brownout reset threshold 2	VDD rising	2.20	2.31	2.38	V
VBOR2		VDD falling	2.10	2.21	2.28
	Brownout reset threshold 3	VDD rising	2.50	2.62	2.68	V
VBOR3		VDD falling	2.40	2.52	2.58
	Brownout reset threshold 4	VDD rising	2.80	2.91	3.00	V
VBOR4		VDD falling	2.70	2.81	2.90
Vhyst_POR_PDR	Hysteresis of VPOR and VPDR	-	-	20	-	mV
Vhyst_BOR	Hysteresis of VBORx	-	-	100	-	mV
IDD(BOR)(1)	BOR consumption from VDD	-	-	2.2	2.5	µA

^1. Specified by design. Not tested in production.

5.3.4 Embedded voltage reference

The parameters given in Table 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Table 26. Embedded internal voltage reference

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VREFINT	Internal reference voltage	-	1.182	1.212	1.232	V
(1)(2) tS_vrefint	ADC sampling time when reading the internal reference voltage	-	4	-	-	µs
tstart_vrefint(2)	Start time of reference voltage buffer when ADC is enable	-	-	8	12	µs
IDD(VREFINTBUF)(2)	VREFINT buffer consumption from VDD when converted by ADC	-	9	13.5	23	µA
∆VREFINT(2)	Internal reference voltage spread over the temperature range	VDD = 3 V	-	30	50	mV
TCoeff	Averange temperature coefficient	-	-	20	70	ppm/°C
ACoeff	Long term stability	1000 hours, T = 25 °C	-	300	1000	ppm
VDDCoeff	Voltage coefficient	3.0 V < VDD < 3.6 V	-	250	1200	ppm/V

^1. The shortest sampling time can be determined in the application by multiple iterations.

^2. Specified by design. Not tested in production.

Figure 11. VREFINT vs. temperature

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 10: Current consumption measurement scheme.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table "Number of wait states according to CPU clock (HCLK) frequency" available in the RM0490 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For flash memory and shared peripherals fPCLK = fHCLK = fHCLKS

Unless otherwise stated, values given in Table 27 through Table 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Table 27. Current consumption in Run mode from flash memory at different die temperatures

| | | Con | ditions | | | Ty | /p | | | Ma | ıx ⁽¹⁾ | |-----------------------|-------------------|-----------------------------------------------------------------|-------------------|------------------------------|----------|----------|-----------|-----------|----------|----------|-------------------|-----------|------| | Symbol | Parameter | General ⁽²⁾ | f _HCLK | Fetch
from ⁽³⁾ | 25
°C | 85
°C | 105
°C | 125
°C | 25
°C | 85
°C | 105
°C | 125
°C | Unit | | | | | 48 MHz | | 3.05 | 3.15 | 3.25 | 3.35 | 3.60 | 3.80 | 4.10 | 4.60 | | | | | 32 MHz | | 2.10 | 2.15 | 2.25 | 2.35 | 2.50 | 2.70 | 3.00 | 3.50 | | | | | 24 MHz | | 1.80 | 1.85 | 1.90 | 2.05 | 2.10 | 2.40 | 2.70 | 3.20 | | | | | 16 MHz | | 1.25 | 1.30 | 1.35 | 1.45 | 1.50 | 1.70 | 2.00 | 2.50 | | | | f _HCLK = f _{HSE_bypass} | 8 MHz | | 0.655 | 0.710 | 0.765 | 0.865 | 0.790 | 1.10 | 1.40 | 1.90 | | | | ( > 32.768 kHz),
f _HCLK = f _{LSE bypass} | 4 MHz | | 0.3654 | 0.420 | 0.470 | 0.570 | 0.460 | 0.700 | 0.980 | 1.50 | | | | ( = 32.768 kHz) | 2 MHz | | 0.225 | 0.270 | 0.325 | 0.425 | 0.290 | 0.540 | 0.820 | 1.40 | | | | 1 MHz | | 0.150 | 0.200 | 0.250 | 0.350 | 0.200 | 0.450 | 0.730 | 1.30 | | | | • | 500 kHz | | 0.115 | 0.160 | 0.215 | 0.315 | 0.160 | 0.410 | 0.690 | 1.20 | | Inn(n) | Supply current in | | 125 kHz | Flash | 0.0875 | 0.135 | 0.185 | 0.285 | 0.130 | 0.380 | 0.650 | 1.20 | mA | | I _DD (Run) | Run mode | | 32.768 kHz | memory | 0.082 | 0.130 | 0.180 | 0.280 | 0.120 | 0.370 | 0.650 | 1.20 | '''' | | | | | 48 MHz | | 3.40 | 3.50 | 3.55 | 3.60 | 3.90 | 4.10 | 4.40 | 4.90 | | | | | 24 MHz | | 2.25 | 2.30 | 2.35 | 2.45 | 2.60 | 2.80 | 3.10 | 3.60 | | | | | 12 MHz | | 1.45 | 1.50 | 1.55 | 1.65 | 1.70 | 1.90 | 2.20 | 2.70 | | | | f _HCLK = f _HSI48/HSIDIV | 6 MHz | | 1.05 | 1.10 | 1.15 | 1.20 | 1.20 | 1.40 | 1.70 | 2.20 | | | | ( > 32 kHz),
f _HCLK = f _LSI | 3 MHz | | 0.855 | 0.880 | 0.925 | 1.00 | 0.960 | 1.20 | 1.50 | 2.00 | | | | ( = 32 kHz) | 1.5 MHz | | 0.750 | 0.780 | 0.825 | 0.915 | 0.840 | 1.10 | 1.40 | 1.90 | | | | | 750 kHz | | 0.700 | 0.730 | 0.775 | 0.865 | 0.780 | 1.00 | 1.30 | 1.80 | | | | | 375 kHz | _ | 0.675 | 0.705 | 0.750 | 0.840 | 0.760 | 0.970 | 1.30 | 1.80 | | | | | 32 kHz | | 0.082 | 0.130 | 0.180 | 0.280 | 0.120 | 0.370 | 0.650 | 1.20 | ^1. Evaluated by characterization. Not tested in production.

^2. $V_{DD}$ = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

^3. Prefetch disabled and cache enabled when fetching from flash memory.

Table 28. Current consumption in Run mode from SRAM at different die temperatures

| | | Cor | nditions | | | Ty | /p | | | Ma | x ⁽¹⁾ | |----------------------|----------------------|---------------------------------------------------------------|-------------------|------------------------------|----------|----------|-----------|-----------|----------|----------|------------------|-----------|------| | Symbol | Parameter | General ⁽²⁾ | f _HCLK | Fetch
from ⁽³⁾ | 25
°C | 85
°C | 105
°C | 125
°C | 25
°C | 85
°C | 105
°C | 125
°C | Unit | | | | | 48 MHz | | 2.80 | 2.90 | 2.95 | 3.05 | 3.20 | 3.40 | 3.70 | 4.20 | | | | | 32 MHz | | 1.90 | 1.95 | 2.00 | 2.10 | 2.20 | 2.40 | 2.70 | 3.20 | | | | | 24 MHz | | 1.45 | 1.50 | 1.55 | 1.65 | 1.70 | 1.90 | 2.20 | 2.70 | | | | | 16 MHz | | 0.990 | 1.05 | 1.10 | 1.20 | 1.20 | 1.40 | 1.70 | 2.20 | | | | f _HCLK = f _{HSE_bypass} | 8 MHz | | 0.535 | 0.585 | 0.635 | 0.735 | 0.630 | 0.860 | 1.20 | 1.70 | | | | (>32.768 kHz),
f _HCLK = f _{LSE_bypass} | 4 MHz | | 0.305 | 0.355 | 0.405 | 0.505 | 0.380 | 0.630 | 0.900 | 1.40 | | | | (=32.768 kHz) | 2 MHz | | 0.195 | 0.240 | 0.295 | 0.390 | 0.250 | 0.500 | 0.770 | 1.30 | | | | | 1 MHz | | 0.135 | 0.185 | 0.235 | 0.335 | 0.180 | 0.430 | 0.710 | 1.30 | | | Supply
current in | | | 500 kHz | | 0.110 | 0.155 | 0.205 | 0.305 | 0.150 | 0.400 | 0.670 | 1.20 | | laava v | | | | 125 kHz | SRAM | 0.0865 | 0.135 | 0.185 | 0.285 | 0.130 | 0.370 | 0.650 | 1.20 | | I _DD(Run) | Run mode | | 32.768 kHz | SKAW | 0.082 | 0.130 | 0.180 | 0.280 | 0.120 | 0.370 | 0.640 | 1.20 | | | | | 48 MHz | | 3.15 | 3.20 | 3.25 | 3.30 | 3.50 | 3.70 | 3.90 | 4.40 | | | | | 24 MHz | | 1.90 | 1.95 | 2.00 | 2.05 | 2.10 | 2.30 | 2.60 | 3.10 | | | | | 12 MHz | | 1.30 | 1.30 | 1.35 | 1.45 | 1.50 | 1.70 | 1.90 | 2.40 | | | | f _HCLK = f _HSI48/HSIDIV | 6 MHz | | 0.965 | 0.995 | 1.05 | 1.15 | 1.15 | 1.30 | 1.60 | 2.10 | | | | ( > 32 kHz),
f _HCLK = f _LSI | 3 MHz | | 0.810 | 0.835 | 0.880 | 0.970 | 0.900 | 1.20 | 1.40 | 1.90 | | | | ( = 32 kHz) | 1.5 MHz | | 0.730 | 0.760 | 0.800 | 0.890 | 0.810 | 1.10 | 1.30 | 1.80 | | | | | 750 kHz | | 0.690 | 0.720 | 0.765 | 0.855 | 0.770 | 0.990 | 1.30 | 1.80 | | | | | 375 kHz | | 0.670 | 0.700 | 0.745 | 0.835 | 0.750 | 0.970 | 1.30 | 1.80 | | | | | 32 kHz | | 0.082 | 0.130 | 0.180 | 0.280 | 0.120 | 0.370 | 0.640 | 1.20 | ^1. Evaluated by characterization. Not tested in production.

^2. $V_{DD}$ = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

^3. Code compiled with high optimization for space in SRAM.

Table 29. Typical current consumption in Run depending on code executed

| | | C | onditions | | Typ | | Typ | |----------------------|-------------------|-----------------------------------------------|-----------------------------|------------------------------|-------|--------|-------|---------------| | Symbol | Parameter | General ⁽¹⁾ | Code | Fetch
from ⁽²⁾ | 25 °C | Unit | 25 °C | Unit | | | | | Reduced code ⁽³⁾ | | 3.40 | | 70.8 | | | | | Coremark | Flack | 3.15 | | 65.6 | | | | | Dhrystone | Flash
memory | 3.20 | | 66.7 | | | | | Fibonacci | | 2.40 | | 50.0 | | | | f _HCLK = f _{HSE_bypass} = | WhileLoop | | 1.80 | | 37.5 | | | | 48 MHz | Reduced code ⁽³⁾ | | 2.80 | | 58.3 | | | | | Coremark | | 2.70 | | 56.3 | | | | | Dhrystone | SRAM | 2.70 | | 56.3 | | | | | Fibonacci | | 2.85 | | 59.4 | | | | | WhileLoop | | 2.15 | | 44.8 | μΑ/MHz | | | | | Reduced code ⁽³⁾ | | 1.25 | | 78.1 | μ/ 0101112 | | | | | Coremark | Floob | 1.15 | | 71.9 | | | | | Dhrystone | Flash
memory | 1.15 | | 71.9 | | | | | Fibonacci | 0.83 | 0.835 | | 52.2 | | Inn(n) | Supply current in | f _HCLK = f _{HSE_bypass} = | WhileLoop | | 0.645 | mA | 40.3 | | I _DD(Run) | Run mode | 16 MHz | Reduced code ⁽³⁾ | | 0.990 | 1117 ( | 61.9 | | | | | Coremark | | 0.950 | | 59.4 | | | | | Dhrystone | SRAM | 0.945 | | 59.1 | | | | | Fibonacci | | 1.00 | | 62.5 | | | | | WhileLoop | | 0.775 | | 48.4 | | | | | Reduced code ⁽³⁾ | | 0.225 | | 112.5 | | | | | Coremark | Floob | 0.210 | | 105.0 | | | | | Dhrystone | Flash
memory | 0.210 | | 105.0 | | | | | Fibonacci | | 0.175 | | 87.5 | | | | f _HCLK = f _{HSE_bypass} = | WhileLoop | | 0.150 | | 75.0 | μΑ/MHz | | | | 2 MHz | Reduced code ⁽³⁾ | | 0.195 | | 97.5 | Pr. 0.1111 12 | | | | | Coremark | | 0.190 | | 95.0 | | | | | Dhrystone | SRAM | 0.190 | | 95.0 | | | | | Fibonacci | | 0.195 | | 97.5 | | | | | WhileLoop | | 0.165 | | 82.5 | Table 29. Typical current consumption in Run depending on code executed (continued)

		C	onditions		Typ		Typ	-
Symbol	Parameter	General (1)	Code	Fetch from (2)	25 °C	Unit	25 °C	Unit
			Reduced code (3)		3.75		78.1
			Coremark	Floob	3.50		72.9
			Dhrystone	Flash memory	3.55		74.0
			Fibonacci		2.75		57.3
		f HCLK = f HSI48/HSIDIV = 48 MHz	WhileLoop		2.15		44.8
		(HSIDIV = 1)	Reduced code (3)		3.15		65.6
			Coremark		3.05		63.5
			Dhrystone	SRAM	3.05		63.5
			Fibonacci		3.20		66.7
			WhileLoop		2.50		52.1	μΑ/MHz
			Reduced code (3)		1.45		120.8	μ/ ν ινιι ιΖ
			Coremark	Flash	1.40		116.7
			Dhrystone	memory	1.40		116.7
			Fibonacci		1.15		95.8
	Supply	f HCLK = f HSI48/HSIDIV = 12 MHz	WhileLoop		1.00		83.3
I DD(Run)	current in Run mode	(HSIDIV = 4)	Reduced code (3)		1.30	mA	108.3
			Coremark		1.25		104.2
			Dhrystone	SRAM	1.25		104.2
			Fibonacci		1.30		108.3
			WhileLoop		1.10		91.7
			Reduced code (3)		0.855		285.0
			Coremark	Flash	0.835		278.3
			Dhrystone	memory	0.835		278.3
			Fibonacci		0.780		260.0
		f HCLK = f HSI48/HSIDIV	WhileLoop		0.745		248.3	A /B 41 1
		= 3 MHz (HSIDIV = 16)	Reduced code (3)		0.810		270.0	μΑ/MHz
		,	Coremark		0.800		266.7
			Dhrystone	SRAM	0.800		266.7
			Fibonacci	1	0.810		270.0
			WhileLoop	1	0.770		256.7
1. $V_{DD}$ = 3.0 V, all peripherals disabled

^2. Prefetch and cache enabled when fetching from flash

^3. Reduced code used for characterization results provided in Table 27.

Table 30. Current consumption in Sleep mode

| | | | Conditions | | | Ty | /p | | | Ma | ax ⁽¹⁾ | |------------------------|------------|----------------------------------------------------------------|------------------|-------------------|----------|----------|-----------|-----------|----------|----------|-------------------|-----------|-------|-------|-------|------| | Symbol | Parameter | Ge | eneral | f _HCLK | 25
°C | 85
°C | 105
°C | 125
°C | 25
°C | 85
°C | 105
°C | 125
°C | Un | | | | | | 48 MHz | 1.20 | 1.20 | 1.25 | 1.35 | 1.50 | 1.70 | 2.00 | 2.50 | | | | All peripherals | | 24 MHz | 0.92 | 0.95 | 0.99 | 1.10 | 1.10 | 1.30 | 1.60 | 2.10 | | | | disabled, | | 12 MHz | 0.79 | 0.81 | 0.86 | 0.95 | 0.91 | 1.20 | 1.40 | 1.90 | | | | $f_{HCLK} = f_{HSI48/HSIDIV}$
( > 32 kHz), | | 6 MHz | 0.72 | 0.75 | 0.79 | 0.88 | 0.82 | 1.10 | 1.30 | 1.80 | | | | $f_{HCLK} = f_{LSI}$ | | 1.5 MHz | 0.67 | 0.70 | 0.74 | 0.83 | 0.75 | 0.97 | 1.30 | 1.80 | | | | ( = 32 kHz) | | 375 kHz | 0.66 | 0.69 | 0.73 | 0.82 | 0.73 | 0.95 | 1.30 | 1.80 | | | | | | 32 kHz | 0.08 | 0.13 | 0.18 | 0.28 | 0.12 | 0.37 | 0.64 | 1.20 | | | Supply | Flash memory er | | 48 MHz | 0.820 | 0.875 | 0.930 | 1.05 | 1.20 | 1.40 | 1.70 | 2.20 | | | | | | 32 MHz | 0.575 | 0.630 | 0.680 | 0.785 | 0.800 | 1.10 | 1.40 | 1.90 | | | | | | 24 MHz | 0.450 | 0.500 | 0.555 | 0.655 | 0.630 | 0.880 | 1.20 | 1.70 | | | | Supply | | | | | | 16 MHz | 0.325 | 0.380 | 0.430 | 0.535 | 0.460 | 0.710 | 0.980 | 1.50 | | I _DD(Sleep) | current in | | | | | | 8 MHz | 0.205 | 0.250 | 0.305 | 0.405 | 0.300 | 0.540 | 0.820 | 1.40 | r | | | Sleep mode | All peripherals | | | 2 MHz | 0.110 | 0.160 | 0.210 | 0.310 | 0.170 | 0.420 | 0.690 | 1.20 | | | | disabled, | | 500 kHz | 0.0875 | 0.135 | 0.185 | 0.285 | 0.130 | 0.380 | 0.650 | 1.20 | | | | f _HCLK = f _{HSE_bypass} | | 32.768 kHz | 0.0805 | 0.125 | 0.180 | 0.280 | 0.120 | 0.370 | 0.640 | 1.20 | | | | ( > 32.768 kHz), | | 48 MHz | 0.815 | 0.870 | 0.925 | 1.05 | 1.20 | 1.40 | 1.70 | 2.20 | | | | f _HCLK = f _{LSE_bypass}
( = 32.768 kHz) | | 32 MHz | 0.570 | 0.620 | 0.675 | 0.775 | 0.790 | 1.10 | 1.40 | 1.90 | | | | ( - 02.7 00 Ki iz) | | 24 MHz | 0.445 | 0.495 | 0.545 | 0.650 | 0.630 | 0.870 | 1.20 | 1.70 | | | | Flash memory disabled (flash memory power- | 16 MHz | 0.320 | 0.375 | 0.425 | 0.525 | 0.460 | 0.700 | 0.980 | 1.50 | | | | | down sleep mode) | 8 MHz | 0.200 | 0.245 | 0.295 | 0.395 | 0.290 | 0.530 | 0.810 | 1.40 | | | | | | 2 MHz | 0.105 | 0.150 | 0.205 | 0.300 | 0.160 | 0.410 | 0.680 | 1.20 | | | | | | 500 kHz | 0.0815 | 0.130 | 0.180 | 0.280 | 0.120 | 0.370 | 0.650 | 1.20 | | | | | | 32.768 kHz | 0.0745 | 0.120 | 0.170 | 0.270 | 0.110 | 0.360 | 0.630 | 1.20 | ^1. Evaluated by characterization. Not tested in production.

Table 31. Current consumption in Stop mode

| | | Table 31. Current | | | • | /p | | | Ma | x ⁽¹⁾ | |------------------------|----------------|------------------------------------------------------------------------------------|-----------------|----------|----------|-----------|-----------|----------|----------|------------------|-----------|------| | Symbol | Parameter | Conditions | V _DD | 25
°C | 85
°C | 105
°C | 125
°C | 25
°C | 85
°C | 105
°C | 125
°C | Unit | | | | | 2 V | 79.0 | 125 | 175 | 275 | 110 | 350 | 610 | 1100 | | | | All clocks off | 2.4 V | 79.0 | 125 | 175 | 275 | 110 | 350 | 610 | 1100 | | | | | 3 V | 80.0 | 125 | 180 | 275 | 110 | 350 | 610 | 1100 | | | | | 3.6 V | 81.5 | 130 | 180 | 280 | 110 | 350 | 610 | 1100 | | | | All clocks off Flash memory in power-down stop mode RTC enabled and supplied with | 2 V | 70.5 | 120 | 170 | 270 | 97.0 | 340 | 600 | 1100 | | | | | 2.4 V | 72.0 | 120 | 170 | 270 | 98.0 | 340 | 600 | 1100 | | | | | 3 V | 73.5 | 120 | 170 | 270 | 100 | 340 | 600 | 1100 | | | | | 3.6 V | 75.0 | 120 | 175 | 270 | 110 | 340 | 600 | 1100 | | | | | 2 V | 78.0 | 125 | 175 | 275 | 110 | 350 | 610 | 1100 | | | Supply current | | 2.4 V | 78.5 | 125 | 175 | 275 | 110 | 350 | 610 | 1100 | μA | | I _DD (Stop) | in Stop mode | LSE bypass (32.768 kHz) | 3 V | 80.0 | 125 | 180 | 275 | 110 | 350 | 610 | 1100 | μΑ | | | | | 3.6 V | 82.0 | 130 | 180 | 280 | 110 | 350 | 610 | 1100 | | | | RTC enabled and supplied with | 2 V | 71.0 | 120 | 170 | 270 | 97.0 | 340 | 600 | 1100 | | | | LSE bypass (32.768 kHz) | 2.4 V | 72.5 | 120 | 170 | 270 | 98.0 | 340 | 600 | 1100 | | | | Flash memory in power-down stop | 3 V | 74.0 | 120 | 170 | 270 | 100 | 340 | 600 | 1100 | | | | mode | 3.6 V | 75.5 | 120 | 175 | 270 | 110 | 340 | 600 | 1100 | | | | | 2 V | 605 | 630 | 675 | 765 | 640 | 850 | 1100 | 1600 | | | | HSI Kornol on | 2.4 V | 605 | 630 | 675 | 765 | 640 | 850 | 1100 | 1600 | | | | HSI Kernel on | 3 V | 605 | 630 | 675 | 765 | 640 | 850 | 1200 | 1600 | | | | | 3.6 V | 605 | 635 | 680 | 770 | 640 | 850 | 1200 | 1600 | ^1. Evaluated by characterization. Not tested in production.

Table 32. Current consumption in Standby mode

| | | Conditions | | | Ty | /p | | | Ma | x ⁽¹⁾ | |-------------|------------|----------------|----------|----------|----------|-----------|-----------|----------|----------|------------------|-----------|------| | Symbol | Parameter | Conditions | $V_{DD}$ | 25
°C | 85
°C | 105
°C | 125
°C | 25
°C | 85
°C | 105
°C | 125
°C | Unit | | | | | 2 V | 6.75 | 7.70 | 8.55 | 10.5 | 7.50 | 8.90 | 11.0 | 16.0 | | | | All clocks off | 2.4 V | 7.05 | 8.00 | 8.85 | 11.0 | 7.70 | 9.10 | 11.0 | 17.0 | | | Supply | All Clocks oil | 3 V | 7.45 | 8.45 | 9.45 | 12.0 | 8.20 | 9.70 | 12.0 | 18.0 | | I | current in | İ | 3.6 V | 7.90 | 8.95 | 10.0 | 12.5 | 8.70 | 11.0 | 13.0 | 20.0 | μΑ | | DD(Standby) | Clariaby | IWDG | 2 V | 7.30 | 8.35 | 9.20 | 11.5 | 8.10 | 9.50 | 12.0 | 17.0 | μΛ | | | mode | enabled and | 2.4 V | 7.65 | 8.65 | 9.60 | 11.5 | 8.30 | 9.80 | 12.0 | 17.0 | | | | clocked by | 3 V | 8.10 | 9.20 | 10.0 | 12.5 | 8.90 | 11.0 | 13.0 | 19.0 | | | | LSI | 3.6 V | 8.60 | 9.75 | 11.0 | 13.5 | 9.50 | 12.0 | 14.0 | 21.0 | ^1. Evaluated by characterization. Not tested in production.

Table 33. Current consumption in Shutdown mode

Symbol Baramete		Conditions		Typ				Max (1)				l l m i é
Symbol Parameter 0	Conditions	$V_{DD}$	25 °C	85 °C	105 °C	125 °C	25 °C	85 °C	105 °C	125 °C	Unit
Supply		2 V	9.00	290	835	2350	55	920	2700	7600
	current in		2.4 V	13.0	320	915	2550	62	970	2900	7900	nΛ
IDD(Shutdown)	Shutdown	off	3.0 V	19.0	375	1050	2900	72	1200	3300	8900	nA
mode		3.6 V	31.0	460	1250	3350	95	1400	3800	11000
1. Evaluated by characterization. Not tested in production.

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up or pull-down resistor generate current consumption when the pin is externally held low or high, respectively. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 49: I/O static characteristics.

For the output pins, any pull-up or pull-down device (internal and external) and external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see Table 34: Current consumption of peripherals), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal and external) of the pin:

$$I_{SW} = V_{DDIO1} \times f_{SW} \times C$$

where

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load

VDDIO1 is the I/O supply voltage

fSW is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
  • when the peripheral is clocked on
  • when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 20: Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

Table 34. Current consumption of peripherals

Peripheral	Bus	Consumption in µA/MHz
IOPORT bus		0.72
GPIOA		1.64
GPIOB	IOPORT	1.64
GPIOC		0.82
GPIOF		0.74
Bus matrix		0.31
All AHB peripherals		8
DMA1	AHB	2.64
FLASH	AHB	4.56
SRAM1		0.01
CRC1		0.48
All APB peripherals		30.76
AHB to APB bridge (2)		0.32
TIM3		3.66
RTCAPB	APB	1.13
WWDG1		0.48
USART2		2.01
I2C1	APB	3.44
I2C1 independent clock domain		2.59
DBGMCU1		0.09
PWR		0.3
SYSCFG		0.4
TIM1		5.84

SPI1 APB 3.18 SPI1 independent clock domain 1.44 USART1 2.22 USART1 independent clock domain 5.77 TIM14 1.42 TIM16 2.54 TIM17 2.45 ADC1 1.92 ADC1 independent clock domain 0.12 Peripheral Bus Consumption in µA/MHz

Table 34. Current consumption of peripherals (continued)

5.3.6 Wake-up time from low-power modes

The wake-up times given in Table 35 are the latency between the event and the execution of the first user instruction.

All peripherals 43.56

Table 35. Low-power mode wake-up times

Symbol	Parameter(1)		Conditions		Max	Unit
	Wake-up time from Sleep to Run	HCLK = HSI48/4 =	Transiting to Run-mode execution in flash memory powered during Sleep mode	10	12	CPU clock cycles
tWUSLEEP	mode	12 MHz	Transiting to Run-mode execution in flash memory not powered during Sleep mode	4.75	5.02	µs
		Clock after	Transiting to Run-mode execution in flash memory powered during Stop mode	2.7	3.1
tWULPSTOP	Wake-up time from Stop mode	wake-up is HCLK = HSI48/4 = 12 MHz	Transiting to Run-mode execution in flash memory not powered during Stop mode	5.9	6.4
			Transiting to Run-mode execution in SRAM	2.5	2.9	µs
tWUSTBY	Wake-up time from Standby mode	Clock after wake up is HCLK = HSI48/4 = 12 MHz	Transiting to Run mode	23	35
tWUSHDN	Wake-up time from Shutdown mode	Clock after wake up is HCLK = HSI48/4 = 12 MHz	Transiting to Run mode	385	466
1. Evaluated by characterization. Not tested in production.

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.13. See Figure 12 for recommended clock input waveform.

Table 36. High-speed external user clock characteristics

Symbol	Parameter (1)	Conditions	Min	Typ	Max	Unit
f HSE_ext	User external clock source frequency	-	-	8	48	MHz
V HSEH	Digital OSC_IN input pin high level voltage	-	0.7 × V DD	-	V DD	V
V HSEL	Digital OSC_IN input pin low level voltage	-	V SS	-	0.3 × V DD	V
t w(HSEH) / t w(HSEL)	Digital OSC_IN high or low time	-	7	-	-	ns

^1. Specified by design. Not tested in production.

Figure 12. High-speed external clock source AC timing diagram

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.13. See Figure 13 for recommended clock input waveform.

Table 37. Low-speed external user clock characteristics

	Symbol	Parameter (1)	Conditions	Min	Typ	Max	Unit
Ī	f LSE_ext	User external clock source frequency	-	-	32.768	1000	kHz

| | rabio or zow opoda externar door olook onaractoriotica (continuou) | |------------------------------------------------|--------------------------------------------------------------------|------------|------------------------|-----|--------------------------|------|--|--| | Symbol | Parameter ⁽¹⁾ | Conditions | Min | Typ | Max | Unit | | V _LSEH | OSC32_IN input pin high level voltage | - | $0.7 \times V_{DDIO1}$ | - | V _DDIO1 | V | | $V_{LSEL}$ | OSC32_IN input pin low level voltage | - | V _SS | - | 0.3 × V _DDIO1 | V | | t _w(LSEH) /
t _w(LSEL) | OSC32_IN high or low time | - | 250 | - | - | ns | Table 37. Low-speed external user clock characteristics (continued)

^1. Specified by design. Not tested in production.

Figure 13. Low-speed external clock source AC timing diagram

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 38. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Conditions⁽²⁾ Parameter⁽¹⁾ Symbol Min Typ Max Unit Oscillator frequency 4 48 MHz f_{OSC_IN} $R_{F}$ Feedback resistor 200 kΩ

Table 38. HSE oscillator characteristics

Table 38. HSE oscillator characteristics (continued)

Symbol	Parameter(1)	Conditions(2)	Min	Typ	Max	Unit
		During startup(3)	-	-	5.5
		VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz	-	0.58	-
		VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz	-	0.59	-
IDD(HSE)	HSE current consumption	VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz	-	0.89	-	mA
		VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz	-	1.14	-
		VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz	-	1.94	-
Gm	Maximum critical crystal transconductance	Startup	-	-	1.5	mA/V
tSU(HSE)(4)	Startup time	VDD is stabilized	-	2	-	ms

• 1. Specified by design. Not tested in production.
• 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
• 1. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
• 1. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 14). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

Figure 14. Typical application with an 8 MHz crystal

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 39. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

| Symbol | Parameter | Conditions(1) | Min(2) | Typ(2) | Max(2) | Unit | |-----------------|--------------------------|--------------------------------------------|--------|--------|--------|------|--| | IDD(LSE) | | LSEDRV = 0
Medium high drive capability | - | 500 | - | | | LSE current consumption | LSEDRV = 1
High drive capability | - | 630 | - | nA | | | Maximum critical crystal | LSEDRV = 0
Medium high drive capability | - | - | 1.7 | | Gmcritmax
gm | | LSEDRV = 1
High drive capability | - | - | 2.7 | µA/V | | | tSU(LSE)(3) Startup time | VDD is stabilized | - | 2 | - | s | Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz)

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

^1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers".

^2. Specified by design. Not tested in production.

^3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Figure 15. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

5.3.8 Internal clock source characteristics

The parameters given in Table 40 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI48) RC oscillator

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI48	HSI48 Frequency	VDD=3.0 V, TA=30 °C	47.92	-	48.40	MHz
	HSI48 oscillator frequency	TA= 0 to 85 °C	-1	-	1	%
∆Temp(HSI)(1)	drift over temperature and VDD full voltage range	TA= -40 to 125 °C	-2.5	-	2	%
		From code 127 to 128	-8	-6	-4
TRIM(1)	HSI48 oscillator frequency user trimming step	From code 63 to 64 From code 191 to 192	-5.8	-3.8	-1.8	%
		For all other code increments	0.2	0.3	0.4
DHSI48(2)	Duty cycle	-	45	-	55	%
tsu(HSI48)(2)	HSI48 oscillator start-up time	-	-	1.4	1.8	μs
tstab(HSI48)(2)	HSI48 oscillator stabilization time	at 1% of target frequency	-	1.5	3.6	μs
IDD(HSI48)(1)	HSI48 oscillator power consumption	-	-	525	570	μA

Table 40. HSI48 oscillator characteristics

^1. Based on characterization results, not tested in production

^2. Specified by design. Not tested in production.

Figure 16. HSI48 frequency versus temperature

Low-speed internal (LSI) RC oscillator

Table 41. LSI oscillator characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	LSI frequency	VDD = 3.3 V, TA = 25 °C	31.04	32	32.96	kHz
fLSI		VDD = 2 V to 3.6 V, TA = -40 to 125 °C	29.5(1)	-	34(1)
tSU(LSI)(2)	LSI oscillator start-up time	-	-	80	130	μs
tSTAB(LSI)(2)	LSI oscillator stabilization time	5% of final frequency	-	125	180	μs
IDD(LSI)(2)	LSI oscillator power consumption	-	-	110	180	nA

^1. Evaluated by characterization. Not tested in production.

5.3.9 Flash memory characteristics

Table 42. Flash memory characteristics

| Symbol | Parameter(1) | Conditions | Min | Typ | Max | Unit | |------------|----------------------------|--------------------|-----|------|-------|------|--| | tprog | Word programming time | 64 bits | - | 85.0 | 125.0 | µs | | | Row (32 double word) | Normal programming | - | 2.7 | 4.6 | ms | | tprog_row | programming time | Fast programming | - | 1.7 | 2.8 | | | Page (2 Kbyte) programming | Normal programming | - | 21.8 | 36.6 | | tprog_page | time | Fast programming | - | 13.7 | 22.4 | ms | | tERASE | Page (2 Kbyte) erase time | - | - | 22.0 | 40.0 | ms | ^2. Specified by design. Not tested in production.

Table 42. Flash memory characteristics (continued)

Symbol	Parameter(1)	Conditions	Min	Typ	Max	Unit
	Bank (32 Kbyte(2))	Normal programming	-	0.4	0.6
tprog_bank	programming time	Fast programming	-	0.2	0.4	s
tME	Mass erase time	-	-	22.1	40.1	ms
		Programming	-	3.0	-
IDD(FlashA)	Average consumption from VDD	Page erase	-	3.0	-	mA
		Mass erase	-	5.0	-
IDD(FlashP)	Maximum current (peak)	Programming, 2 µs peak duration	-	7.0	-	mA
		Erase, 41 µs peak duration	-	7.0	-
1. Specified by design. Not tested in production.

Table 43. Flash memory endurance and data retention

Symbol	Parameter(1)	Conditions	Min	Unit
NEND	Endurance	TJ = -40 to +130 °C	10	kcycles
		1 kcycle(2) at TA = 85 °C	30
		1 kcycle(2) at TA = 105 °C	15
		1 kcycle(2) at TA = 125 °C	7
tRET	Data retention	10 kcycles(2) at TA = 55 °C	30	Years
		10 kcycles(2) at TA = 85 °C	15
		10 kcycles(2) at TA = 105 °C	10
1. Evaluated by characterization. Not tested in production..

^2. Values provided also apply to devices with less flash memory than one 32 Kbyte bank

^2. Cycling performed over the whole temperature range.

5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V_DD and V_SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 44. They are based on the EMS levels and classes defined in application note AN1709.

Symbol	Parameter	Conditions	Level/ Class
V FESD	Voltage limits to be applied on any I/O pin to induce a functional disturbance	$V_{DD}$ = 3.3 V, $T_{A}$ = +25 °C, $f_{HSE}$ = $f_{HCLK}$ = 48 MHz, TSSOP20, conforming to IEC 61000-4-2	2B
V FTB	Fast transient voltage burst limits to be applied through 100 pF on V DD and V SS pins to induce a functional disturbance	$V_{DD}$ = 3.3 V, $T_A$ = +25 °C, $f_{HSE}$ = $f_{HCLK}$ = 48 MHz, TSSOP20, conforming to IEC 61000-4-2	4B

Table 44. EMS characteristics

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• corrupted program counter
• unexpected reset
• critical data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

The following table gives the EMI characteristics for fHSI48 and fHCLK of 48 MHz.

Symbol	Parameter	Conditions	Monitored	Max vs. [fHSE/fCPU]	Max vs. [fHSI/fCPU]	Unit
			frequency band	48 MHz / 48 MHz	48 MHz / 48 MHz
		VDD = 3.6 V, TA = 25 °C,	0.1 MHz to 30 MHz	3	3
	Peak(1)		30 MHz to 130 MHz	5	-2
SEMI		TSSOP20 package	130 MHz to 1 GHz	1	-1	dBµV
		compliant with IEC 61967-2	1 GHz to 2 GHz	7	8
	Level(2)		0.1 MHz to 2 GHz	2	2	-

Table 45. EMI characteristics

5.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

^1. Refer to AN1709, section EMI radiated test

^2. Refer to AN1709, section EMI level classification

Symbol	Ratings	Conditions	Class	Maximum value (1)	Unit
V ESD(HBM)	Electrostatic discharge voltage (human body model)	T A = +25 °C, conforming to ANSI/ESDA/JEDEC JS-001	1C	-2000/+1500	V
V ESD(CDM)	Electrostatic discharge voltage (charge device model)	T A = +25 °C, conforming to ANSI/ESDA/JEDEC JS-002	C2a	500	V

Table 46. ESD absolute maximum ratings

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.
• A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 47. Electrical sensitivity

Symbol	Parameter	Conditions	Class
LU	Static latch-up class	T A = +125 °C conforming to JESD78	II Level A

5.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below $V_{SS}$ or above $V_{DDIO1}$ (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter: ADC error above a certain limit (higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 $\mu$ A/+0 $\mu$ A range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

^1. Evaluated by characterization. Not tested in production.

| | Description | | Functional su | |------------------|-------------------------|--------|-----------------------|--------------------|------| | Symbol | | | Negative
injection | Positive injection | Unit | | I _INJ | Injected current on pin | Any IO | 5 | NA | mA |

Table 48. I/O current injection susceptibility

5.3.13 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant.

For information on GPIO configuration, refer to the application note AN4899 STM32 GPIO configuration for hardware settings and low-power consumption, available on the ST website www.st.com.

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
V IL (1)	I/O input low level voltage	All	2.0 V < V DDIO1 < 3.6 V	-	-	0.3 × V DDIO1	V
V IH (1)	I/O input high level voltage	All	2.0 V < V DDIO1 < 3.6 V	0.7 × V DDIO1	-	-	V
V hys (2)	I/O input hysteresis	-		-	200	-	mV
		$0 < V_{IN} \le V_{DDIO1}$		-	±70	-
$I_{lkg}^{(3)}$	Input leakage current (3)	$V_{DDIO1} \le V_{IN} \le V_{DDIO1} + 1 V$		-	600	-	nA
		$V_{DDIO}$	$_1$ + 1 V $\leq$ V IN	-	150	ı
R PU	R PU Weak pull-up equivalent resistor $V_{IN} = V_{SS}$		$V_{SS}$	25	40	55	kΩ
R PD Weak pull-down equivalent resistor (4)		V IN = '	VDDIO 1	25	40	55	kΩ
C IO	I/O pin capacitance		-	-	5	-	pF

Table 49, I/O static characteristics

^1. Evaluated by characterization. Not tested in production.

^1. Refer to Figure 17: I/O input characteristics.

^2. Specified by design. Not tested in production.

^3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: $I_{Total_leak_max} = 10 \ \mu A + [number of I/Os where V_{IN} is applied on the pad] \times I_{lkg}(Max)$ .

^4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in Figure 17.

Figure 17. I/O input characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to $\pm 6$ mA, and up to $\pm 15$ mA with relaxed $V_{OI}/V_{OH}$ .

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:

• The sum of the currents sourced by all the I/Os on V_DDIO1, plus the maximum consumption of the MCU sourced on V_DD, cannot exceed the absolute maximum rating I_VDD (see Table 20: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on V_SS, plus the maximum consumption of the MCU sunk on V_SS, cannot exceed the absolute maximum rating I_VSS (see Table 20: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified).

| Table 50. Output voltage characteristics ⁽¹⁾ | |---------------------------------------------------------|------|--|--|--|--|--|--| | | • "" |

Symbol	Parameter	Conditions	Min	Max	Unit
$V_{OL}$	Output low level voltage	CMOS port (2)	-	0.4	V
V OH	Output high level voltage	I IO = 8 mA V DDIO1 ≥ 2.7 V	V DD - 0.4	-	V
V OL (3)	Output low level voltage	TTL port (2)	-	0.4	V
V OH (3)	Output high level voltage	I IO = 8 mA V DDIO1 ≥ 2.7 V	2.4	-	V
V OL (3)	Output low level voltage	All I/Os	-	1.3	V
V OH (3)	Output high level voltage	I IO = 20 mA V DDIO1 ≥ 2.7 V	V DD - 1.3	-	V
V OL (3)	Output low level voltage	I IO = 4 mA	-	0.45	V
V OH (3)	Output high level voltage	V DDIO1 ≥ 2.0 V	V DD - 0.45	-	V
V OLEM+	Output low level voltage for an FT I/O pin in FM+ mode	I IO = 20 mA V DDIO1 ≥ 2.7 V	-	0.4	V
-(3)		I IO = 10 mA V DDIO1 ≥ 2.0 V	-	0.4	V

The I_IO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20: Voltage characteristics. The sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ∑I_IO.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 18 and Table 51, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Table 51. I/O AC characteristics

| Speed | Symbol | Parameter ⁽¹⁾⁽²⁾ | Conditions | Min | Max | Unit | |-------|--------|------------------------------------------|---------------------------------------------|-----|--------|---------|--| | | | | C=50 pF, 2.7 V ≤ V _DDIO1 ≤ 3.6 V | - | 2 | | | Fmax | | C=50 pF, 2.0 V ≤ V _DDIO1 ≤ 2.7 V | - | 0.35 | MHz | | | Fillax | iviaximum frequency | C=10 pF, 2.7 V ≤ V _DDIO1 ≤ 3.6 V | - | 3.00 | IVII IZ | | 00 | | | C=10 pF, 2.0 V ≤ V _DDIO1 ≤ 2.7 V | - | 0.45 | | 00 | | | C=50 pF,2.7 V ≤ V _DDIO1 ≤ 3.6 V | - | 100.00 | | | Tr/Tf | Output rise and fall time ⁽³⁾ | C=50 pF, 2.0 V ≤ V _DDIO1 ≤ 2.7 V | - | 225.00 | | | 11/11 | Output rise and fail time. | C=10 pF, 2.7 V ≤ V _DDIO1 ≤ 3.6 V | - | 75.00 | ns | | | | | C=10 pF, 2.0 V ≤ V _DDIO1 ≤ 2.7 V | - | 150.00 | ^2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

^3. Specified by design. Not tested in production.

Table 51. I/O AC characteristics (continued)

| Speed | Symbol | Parameter(1)(2) | Conditions | Min | Max | Unit | |-------|--------|------------------------------|---------------------------------|-----|----------|------|--| | | | | C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 10.00 | | | | Maximum frequency | C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 2.00 | MHz | | | Fmax | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 15.00 | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 2.50 | | 01 | | | C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 30.00 | | | | Output rise and fall time(3) | C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 60.00 | | | Tr/Tf | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 15.00 | ns | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 30.00 | | | | | C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 30.00 | | | | Maximum frequency | C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 15.00 | | | Fmax | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 60.00(4) | MHz | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 30.00 | | 10 | | Output rise and fall time(3) | C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 11.00 | | | | | C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 22.00 | ns | | | Tr/Tf | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 4.00 | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 8.00 | | | | | C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 60.00(4) | | | | | C=30 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 30.00 | | | Fmax | Maximum frequency | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 80.00(4) | MHz | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 40.00 | | 11 | | | C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 5.50 | | | | Output rise and fall time(3) | C=30 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 11.00 | ns | | | Tr/Tf | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 2.50 | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 5.00 | ^1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the RM0490 reference manual for a description of GPIO Port configuration register.

^2. Specified by design. Not tested in production.

^3. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.

^4. This value represents the I/O capability but the maximum system frequency is limited to 48 MHz.

Figure 18. I/O AC characteristics definition(1)

1. Refer to Table 51: I/O AC characteristics.

5.3.14 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU.

Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VIL(NRST)	NRST input low level voltage	-	-	-	0.3 × VDD	V
VIH(NRST)	NRST input high level voltage	-	0.7 × VDD	-	-	V
Vhys(NRST)	NRST Schmitt trigger voltage hysteresis	-	-	200	-	mV
RPU(1)	Weak pull-up equivalent resistor(2)	VIN = VSS	25	40	55	kΩ
VF(NRST) (1)	NRST input filtered pulse	2.0 V < VDD < 3.6 V	-	-	70	ns
VNF(NRST)(1)	NRST input not filtered pulse	2.0 V < VDD < 3.6 V	350	-	-	ns

Table 52. NRST pin characteristics

^1. Specified by design. Not tested in production..

^2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).

Figure 19. Recommended NRST pin protection

• 1. The reset network protects the device against parasitic resets.
• 1. The user must ensure that, upon power-on, the level on the NRST pin can exceed the minimum VIH(NRST) level specified in Table 52: NRST pin characteristics. Otherwise, the device does not exit the power-on reset. This applies to any NRST configuration set through the NRST_MODE[1:0] bitfield, the GPIO mode inclusive.
• 1. The external capacitor on NRST must be placed as close as possible to the device.

5.3.15 Extended interrupt and event controller input (EXTI) characteristics

Table 53. EXTI input characteristics

Symbol	Parameter(1)	Conditions	Min	Typ	Max	Unit
PLEC	Pulse length to event controller	-	20	-	-	ns

^1. Specified by design. Not tested in production.

5.3.16 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 54 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 23: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

Table 54. ADC characteristics

Symbol	Parameter(1)	Conditions	Min	Typ	Max	Unit
VDDA	Analog supply voltage	-	2.0	-	3.6	V
VREF+	Positive reference voltage	-	2	-	VDD	V
fADC	ADC clock frequency	-	0.14	-	35	MHz
		12 bits	-	-	2.50
		10 bits	-	-	2.92
fs	Sampling rate	8 bits	-	-	3.50	MSps
		6 bits	-	-	4.38
Table 54. ADC characteristics (continued)

Symbol	Parameter(1)	Conditions	Min	Typ	Max	Unit
	External trigger	fADC = 35 MHz; 12 bits	-	-	2.33
fTRIG	frequency	12 bits	-	-	fADC/15	MHz
VAIN	Conversion voltage range	-	0	-	VREF+(2)	V
RAIN	External input impedance	-	-	-	50	kΩ
CADC	Internal sample and hold capacitor	-	-	5	-	pF
tSTAB	ADC power-up time	LDO already started		2		Conversion cycle
		fADC = 35 MHz		2.35		µs
tCAL	Calibration time	-	82		1/fADC
		CKMODE = 00	1.5/fADC + 2/fPCLK	-	1.5/fADC + 3/fPCLK	-
	WLATENCY ADC_DR register write latency	CKMODE = 01	4.5
		CKMODE = 10		8.5
		CKMODE = 11	2.5
	Trigger conversion	CKMODE = 00	2	-	3	1/fADC
	latency for regular and injected channels without aborting the conversion	CKMODE = 01		6.5
tLATR		CKMODE = 10		12.5
		CKMODE = 11	3.5
			0.043	-	4.59	µs
ts	Sampling time	fADC = 35 MHz	1.5	-	160.5	1/fADC
tADCVREG _STUP	ADC voltage regulator start-up time	-	-	-	20	µs
	Total conversion	fADC = 35 MHz Resolution = 12 bits	0.40	-	4.95	µs
tCONV	time (including sampling time)	Resolution = 12 bits		approximation = 14 to 173	ts + 12.5 cycles for successive	1/fADC
tIDLE	Laps of time allowed between two conversions without rearm	-	-	-	100	µs
		fs = 2.5 MSps	-	410	-
IDDA(ADC)	ADC consumption from VDDA	fs = 1 MSps	-	164	-	µA
		fs = 10 kSps	-	17	-
Table 54. ADC characteristics (continued)

Symbol	Parameter(1)	Conditions	Min	Typ	Max	Unit
		fs = 2.5 MSps	-	65	-
IDDV(ADC)	ADC consumption from VREF+	fs = 1 MSps	-	26	-	µA
		fs = 10 kSps	-	0.26	-
1. Specified by design. Not tested in production.

Table 55. Maximum ADC RAIN .

Resolution	Sampling cycle at 35 MHz	Sampling time at 35 MHz (ns)	Max. RAIN(1) (Ω)
	1.5	43	50
	3.5	100	680
	7.5	214	2200
	12.5	357	4700
12 bits	19.5	557	8200
	39.5	1129	15000
	79.5	2271	33000
	160.5	4586	50000
	1.5	43	68
	3.5	100	820
	7.5	214	3300
	12.5	357	5600
10 bits	19.5	557	10000
	39.5	1129	22000
	79.5	2271	39000
	160.5	4586	50000
	1.5	43	82
	3.5	100	1500
	7.5	214	3900
	12.5	357	6800
8 bits	19.5	557	12000
	39.5	1129	27000
	79.5	2271	50000
	160.5	4586	50000

^2. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate functions for further details.

Table 55. Maximum ADC RAIN . (continued)

Resolution	Sampling cycle at 35 MHz	Sampling time at 35 MHz (ns)	Max. RAIN(1) (Ω)
	1.5	43	390
	3.5	100	2200
	7.5	214	5600
	12.5	357	10000
6 bits	19.5	557	15000
	39.5	1129	33000
	79.5	2271	50000
	160.5	4586	50000

^1. Specified by design. Not tested in production.

Table 56. ADC accuracy

Symbol	Parameter(1)(2)	Conditions	Min	Typ	Max	Unit
Total		VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25°C	-	±3	±4	LSB
ET	unadjusted error	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±3	±6.5
EO	Offset error	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25°C	-	±1.5	±2	LSB
		2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±1.5	±4.5
EG	Gain error	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	-	±3	±3.5	LSB
		2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±3	±5
	Differential	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	-	±1.2	±1.5
ED	linearity error	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±1.2	±1.5	LSB
	Integral linearity	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	-	±2.5	±3
EL	error	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±2.5	±3	LSB
	Effective	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	10.1	10.2	-
ENOB	number of bits	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	9.6	10.2	-	bit

Symbol	Parameter (1)(2)	Conditions	Min	Typ	Max	Unit
Signal-to-noise		$V_{DDA} = V_{REF+} = 3 \text{ V}$ $f_{ADC} = 35 \text{ MHz}, f_{S} \le 2.5 \text{ Msps}, T_{A} = 25 \text{ °C}$	62.5	63	-	dB
SINAD and distortion ratio	$2 \text{ V} < \text{V}{\text{DDA}} = \text{V}{\text{REF+}} < 3.6 \text{ V}$ $f_{\text{ADC}} = 35 \text{ MHz}, f_{\text{s}} \le 2.5 \text{ Msps}, T_{\text{A}} = \text{entire range}$	59.5	63	ı	ğ
OND	Signal-to-noise	$V_{DDA} = V_{REF+} = 3 V$ $f_{ADC} = 35 \text{ MHz}, f_s \le 2.5 \text{ Msps}, T_A = 25 °C$	63	64	-	dB
SNR	ratio	$2 \text{ V} < \text{V}{\text{DDA}} = \text{V}{\text{REF+}} < 3.6 \text{ V}$ $f_{\text{ADC}} = 35 \text{ MHz}, f_{\text{s}} \le 2.5 \text{ Msps}, T_{\text{A}} = \text{entire range}$	60	64	-	uБ
Total harmonic		$V_{DDA} = V_{REF+} = 3 V$ $f_{ADC} = 35 \text{ MHz}, f_s \le 2.5 \text{ Msps}, T_A = 25 °C$	-	-74	-73	dB
THD distortion	$2 \text{ V} < \text{V}{\text{DDA}} = \text{V}{\text{REF+}} < 3.6 \text{ V}$ $f_{\text{ADC}} = 35 \text{ MHz}, f_{\text{S}} \le 2.5 \text{ Msps}, T_{\text{A}} = \text{entire range}$	-	-74	-70	ub
Table 56. ADC accuracy (continued)

• 1. Evaluated by characterization. Not tested in production.
• 1. ADC DC accuracy values are measured after internal calibration.

Output code (1) Example of an actual transfer curve(2) Ideal transfer curve(3) End-point correlation line 2ⁿ-1 2ⁿ-2 n = ADC resolution E_T = total unadjusted error: maximum deviation between the actual and ideal transfer curves E_O = offset error: maximum deviation between the first actual transition and the first ideal one E_G = gain error: deviation between the last ideal transition and the last actual one E_D = differential linearity error: maximum deviation between actual steps and the ideal one $E_L$ = integral linearity error: maximum deviation between any actual transition and the end point correlation line 1 LSB ideal $V_{REF+}(V_{DDA})$ (2^n-3/2ⁿ)*V_REF+ (2^n-2/2ⁿ)*V_REF+ (2^n-1/2ⁿ)*V_REF+ $(2^{n}/2^{n})*V_{REF+}$ (5/2ⁿ)*V_REF MSv19880V6

Figure 20. ADC accuracy characteristics

Figure 21. ADC typical connection diagram

• 1. Refer to Table 54: ADC characteristics for the values of RAIN and CADC.
• C_parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 49: I/O static characteristics for the value of the pad capacitance). A high C_parasitic value will downgrade conversion accuracy. To remedy this, f_ADC should be reduced.
• 1. Refer to Table 49: I/O static characteristics for the values of I_lkg.
• 1. Refer to Figure 2: Power supply overview.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 9: Power supply scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

5.3.17 Temperature sensor characteristics

Symbol	Parameter	Min	Typ	Max	Unit
T L (1)	V SENSE linearity with temperature	-	±1	±5	°C
Avg_Slope (2)	Average slope from V SENSE voltage	2.4	2.53	2.65	mV/°C
V 30 (3)	Voltage at 30°C (±5 °C)	0.742	0.76	0.786	V
t START(TS_BUF) (1)	Sensor Buffer Start-up time in continuous mode	1	8	15	μs
t START (1)	Start-up time when entering in continuous mode	ı	70	120	μs
t S_temp (1)	ADC sampling time when reading the temperature	5	-	-	μs
i sens (1)	Temperature sensor consumption from $V_{DD}$ , when selected by ADC	-	4.7	7.0	μΑ

Table 57. Temperature sensor characteristics

• 1. Specified by design. Not tested in production.
• 1. Evaluated by characterization. Not tested in production.
• 1. Measured at $V_{DDA}$ = 3.0 V ±10 mV. The $V_{30}$ ADC conversion result is stored in the TS_CAL1 byte.

5.3.18 Timer characteristics

The parameters given in the following tables are specified by design.

Note: TIMx is used as a general term to refer to a timer (for example, TIM1).

Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 58. TIMx characteristics

Symbol	Parameter	Conditions	Min(1)	Max(1)	Unit
		-	1	-	tTIMxCLK
tres(TIM)	Timer resolution time	fTIMxCLK = 48 MHz	20.833	-	ns
fEXT	Timer external clock frequency on CH1 to CH4	-	0	fTIMxCLK/4	MHz
ResTIM	Timer resolution TIMx - 16		bit
tCOUNTER	Counter clock period	TIMx	1	216	tTIMxCLK

^1. Specified by design. Not tested in production.

Table 59. IWDG min/max timeout period at 32 kHz LSI clock

Prescaler divider	PR[2:0] bits	Min timeout(1) RL[11:0]= 0x000	Max timeout(1) RL[11:0] = 0xFFF	Unit
/4	0	0.125	512
/8	1	0.250	1024
/16	2	0.500	2048
/32	3	1.0	4096	ms
/64	4	2.0	8192
/128	5	4.0	16384
/256	6 or 7	8.0	32768
1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an uncertainty of one RC period.

5.3.19 Characteristics of communication interfaces

I 2 C-bus interface characteristics

The I2C-bus interface meets timing requirements of the I2C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The timings are specified by design as long as the I2C peripheral is properly configured (refer to the reference manual RM0490) and when the I2CCLK frequency is greater than the minimum shown in the following table.

Symbol Parameter Condition Typ Unit fI2CCLK(min) Minimum I2CCLK frequency for correct operation of I2C peripheral Standard-mode 2 MHz Fast-mode Analog filter enabled 9 DNF = 0 Analog filter disabled 9 DNF = 1 Fast-mode Plus Analog filter enabled 19 DNF = 0 Analog filter disabled 16 DNF = 1

Table 60. Minimum I2CCLK frequency

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins support Fm+ low-level output current maximum requirement. Refer to Section 5.3.13: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its characteristics:

Symbol	Parameter(1)	Min	Max	Unit
tAF	Maximum pulse width of spikes that are suppressed by the analog filter	50(2)	100(3)	ns

Table 61. I2C analog filter characteristics

• 1. Evaluated by characterization. Not tested in production.
• 1. Spikes with widths below tAF (min) are filtered.
• 1. Spikes with widths above tAF (max) are not filtered.

USART (SPI mode) characteristics

Unless otherwise specified, the parameters given in Table 62 for USART are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions. The additional general conditions are:

• OSPEEDRy[1:0] set to 10 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 × VDD

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART).

Table 62. USART (SPI mode) characteristics

| Symbol | Parameter | Conditions | Min | Typ | Max | Unit | |----------------------|------------------------|--------------------------------------------------------|-------------------------------------|-------------------------|-------------------------|------|--| | | | Master mode
2.0 V < V _DD < 3.6 V | - | - | 6.0 | | $f_{CK}$ | USART clock frequency | Slave receiver mode
2.0 V < V _DD < 3.6 V | - | - | 16.0 | MHz | | | | Slave transmitter mode 2.0 V < V _DD < 3.6 V | - | - | 16.0 | | t _su(NSS) | NSS setup time | Slave mode | T _ker ⁽¹⁾ + 1 | - | - | ns | | t _h(NSS) | NSS hold time | Slave mode | 2 | - | - | ns | | t _w(CKH) | CK high time | - Master mode | 1 / f _CK / 2 | 1/f /2 | 1 / f _CK / 2 | ns | | t _w(CKL) | CK low time | - Iviastei mode | - 1 | 1 / f _CK / 2 | + 1 | 115 | | t | | Master mode
2.0 V < V _DD < 3.6 V | 19 | - | - | ns | | t _su(RX) | Bata input setup time | Slave mode | 1.5 | - | - | 113 | | 4 | Data input hold time | Master mode | 0 | - | - | no | | t _h(RX) | Data input noid time | Slave mode | 0 | - | - | ns | | | | Slave mode
2.0 V < V _DD < 3.6 V | - | 13.5 | 25.5 | ne | | $t_{V(TX)}$ | Data output valid time | Slave mode
2.7 V < V _DD < 3.6 V | - | 15.5 | 17.5 | ns | | | | Master mode | - | 2.0 | 4 | | t | Data output hold time | Slave mode | 11.5 | - | - | ne | | t _h(TX) | Data output noid time | Master mode | 0.5 | - | - | ns | ^1. T_ker is the usart_ker_ck_pres clock period

Figure 22. USART timing diagram in SPI master mode

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Table 63 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions. The additional general conditions are:

• OSPEEDRy[1:0] set to 11 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 × VDD

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 63. SPI characteristics

Symbol	Parameter (1)	Conditions	Min	Typ	Max	Unit
		Master mode 2 V < V DD < 3.6 V			24
	SPI clock frequency	Slave receiver mode			24
f SCK 1/t c(SCK)		Slave transmitter mode/full duplex (2) 2.7 V < V DD < 3.6 V	-	-	24	MHz
		Slave transmitter mode/full duplex (2) 2 V < V DD < 3.6 V			22
t su(NSS)	NSS setup time	Slave mode	4 * T PCLK	-	-	ns
t h(NSS)	NSS hold time	Slave mode	2 * T PCLK	-	-	ns
t w(SCKH)	SCK high and low times	Master mode	T SCK2 (3) - 1	T PCLK	T SCK2 (3) + 1	ns
t su(RX)	Data input setup time in master mode	-	4.5	-	-	ns
t su(SI)	Data input setup time in slave mode	-	2	-	-	ns
t h(MI)	Data input hold time in master mode	-	2	-	-	ns
t h(SI)	Data input hold time in slave mode	-	3	-	-	ns
t a(SO)	Data output access time in slave mode	-	9	-	34	ns
t dis(SO)	Data output disable time in slave mode	-	9	-	16	ns
		2.7 V < V DD < 3.6 V	-	10	16
t v(SO)	Data output valid time in slave mode	2 V < V DD < 3.6 V	-	10	22	ns
t v(MO)	Data output valid time in master mode	-	-	3	5.5	ns
t h(SO)	Data output hold time in slave mode	-	8	-	-	ns
t h(MO)	Data output hold time in master mode	-	1.5	-	-	ns

^1. Evaluated by characterization. Not tested in production.

Maximum frequency in Slave transmitter mode is determined by the sum of t_v(SO) and t_su(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having t_su(MI) = 0 while Duty(SCK) = 50%

^3. $T_{SCK2} = T_{PCLK} * prescaler / 2$

MSv41658V2 NSS input CPHA=0 CPOL=0 SCK input CPHA=0 CPOL=1 MISO output MOSI input tsu(SI) th(SI) tw(SCKL) tw(SCKH) tc(SCK) ^th(NSS) tdis(SO) tsu(NSS) ta(SO) tv(SO) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(SO) Last bit IN

Figure 24. SPI timing diagram - slave mode and CPHA = 0

1. Measurement points are done at 0.5 VDD and with external CL = 30 pF.

Figure 26. SPI timing diagram - master mode

1. Measurement points are done at 0.5 VDD and with external CL = 30 pF.

Table 64. I2S characteristics

Symbol	Parameter(1)	Conditions	Min	Max	Unit
fMCK	I2S main clock output	-	-	48	MHz
		Master TX	-	12
		Master RX	-	12
fCK	I2S clock frequency	Slave TX	-	15	MHz
		Slave RX	-	48
tv(WS)	WS valid time	Master mode	-	5	ns
th(WS)	WS hold time	Master mode	2	-	ns
tsu(WS)	WS setup time	Slave mode	3.5	-	ns
th(WS)	WS hold time	Slave mode	1	-	ns
tsu(SD_MR)		Master receiver	5	-	ns
tsu(SD_SR)	Data input setup time	Slave receiver	2.5	-	ns
th(SD_MR)	Data input hold time	Master receiver	1.5	-	ns
th(SD_SR)		Slave receiver	1	-	ns
tv(SD_ST)		Slave transmitter (after enable edge)	-	19.5	ns
tv(SD_MT)	Data output valid time	Master transmitter (after enable edge)	-	5	ns

Table 64. I2S characteristics

Symbol	Parameter(1) Conditions		Min	Max	Unit
th(SD_ST)		Slave transmitter (after enable edge)	8	-	ns
th(SD_MT)	Data output hold time	Master transmitter (after enable edge)	2.5	-	ns

^1. Evaluated by characterization. Not tested in production.

Figure 27. I2S slave timing diagram (Philips protocol)

• 1. Measurement points are done at CMOS levels: 0.3 × VDDIO1 and 0.7 × VDDIO1.
• 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 28. I2S master timing diagram (Philips protocol)

• 1. Evaluated by characterization. Not tested in production.
• 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Package information STM32C011x4/x6

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

6.1 Device marking

Refer to technical note "Reference device marking schematics for STM32 microcontrollers and microprocessors" (TN1433) available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the marking areas versus pin 1 / ball A1.

Parts marked as "ES", "E" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection.

6.2 SO8N package information (O7)

This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package.

Figure 29. SO8N -Outline

1. Drawing is not to scale.

Table 65. SO8N -Mechanical data

| | | millimeters | | | inches(1) | |--------|-------|-------------|-------|--------|-----------|--------| | Symbol | Min. | Typ. | Max. | Min. | Typ. | Max. | | A | - | - | 1.750 | - | - | 0.0689 | | A1 | 0.100 | - | 0.250 | 0.0039 | - | 0.0098 |

Table 65. SO8N -Mechanical data (continued)

| | | millimeters | | | inches(1) | |--------|-------|-------------|-------|--------|-----------|--------| | Symbol | Min. | Typ. | Max. | Min. | Typ. | Max. | | A2 | 1.250 | - | - | 0.0492 | - | - | | b | 0.280 | - | 0.480 | 0.0110 | - | 0.0189 | | c | 0.100 | - | 0.230 | 0.0039 | - | 0.0091 | | D(2) | 4.800 | 4.900 | 5.000 | 0.1890 | 0.1929 | 0.1969 | | E | 5.800 | 6.000 | 6.200 | 0.2283 | 0.2362 | 0.2441 | | E1(3) | 3.800 | 3.900 | 4.000 | 0.1496 | 0.1535 | 0.1575 | | e | - | 1.270 | - | - | 0.0500 | - | | h | 0.250 | - | 0.500 | 0.0098 | - | 0.0197 | | k | 0° | - | 8° | 0° | - | 8° | | L | 0.400 | - | 1.270 | 0.0157 | - | 0.0500 | | L1 | - | 1.040 | - | - | 0.0409 | - | | ccc | - | - | 0.100 | - | - | 0.0039 |

• 1. Values in inches are converted from mm and rounded to four decimal digits.
• 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side
• 1. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.

Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side.

Package information STM32C011x4/x6

0.6 (x8) 3.9 6.7

1.27

Figure 30. SO8N - Footprint example

1. Dimensions are expressed in millimeters.

O7_FP_V1

6.3 WLCSP12 package information (B0EK)

This WLCSP is a 12-ball, 1.70 x 1.42 mm, 0.35 mm pitch, wafer level chip scale package

e2 G F e1 A4 B0EK_WLCSP12_ME_V1 A2 B3 B1 C4 C2 D3 D1 E4 E2 F3 F1 (DETAIL B) DETAIL B e e (DETAIL A) bbb Z A BACKSIDE COATING SIDE VIEW BOTTOM VIEW SIDE VIEW A3 A2 D E A eee aaa TOP VIEW B1 Orientation ref 4x BUMP b (Nx) ddd Z X Y ccc A1 Z SEATING PLANE DETAIL A ROATATED 90

Figure 31. WLCSP12 – Outline

• 1. Drawing is not to scale.
• 1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
• 1. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
• 1. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.

Package information STM32C011x4/x6

Table 66. WLCSP12 – Mechanical data

| | millimeters | | | inches(1) | |--------|-------------|-------|------|-----------|--------|--------| | Symbol | Min | Typ | Max | Min | Typ | Max | | A(2) | - | - | 0.49 | - | - | 0.0193 | | A1 | - | 0.17 | - | - | 0.0067 | - | | A2 | - | 0.29 | - | - | 0.0114 | - | | A3(3) | - | 0.025 | - | - | 0.0098 | - | | Ø b(4) | 0.21 | 0.24 | 0.27 | 0.0083 | 0.0094 | 0.0106 | | D | 1.68 | 1.70 | 1.72 | 0.0661 | 0.0669 | 0.0677 | | E | 1.41 | 1.42 | 1.43 | 0.0555 | 0.0559 | 0.0563 | | e | - | 0.35 | - | - | 0.0138 | - | | e1 | - | 0.909 | - | - | 0.0358 | - | | e2 | - | 0.875 | - | - | 0.0344 | - | | F(5) | - | 0.409 | - | - | 0.0161 | - | | G(5) | - | 0.282 | - | - | 0.0111 | - | | N | 12 | | aaa | - | - | 0.10 | - | - | 0.0039 | | bbb | - | - | 0.10 | - | - | 0.0039 | | ccc(6) | - | - | 0.10 | - | - | 0.0039 | | ddd(7) | - | - | 0.05 | - | - | 0.0020 | | eee | - | - | 0.05 | - | - | 0.0020 |

• 1. Values in inches are converted from mm and rounded to 4 decimal digits.
• 1. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal and tolerances values of A1 and A2.
• 1. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.
• 1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
• 5. Calculated dimensions are rounded to the 3rd decimal place
• 1. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
• 1. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone. Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of each ball must lie simultaneously in both tolerance zones

STM32C011x4/x6 Package information

BGA_WLCSP_FT_V1 Dsm Dpad

Figure 32. WLCSP12 – Footprint example

Table 67. WLCSP12 - Example of PCB design rules

Dimension	Recommended values
Pitch	0.35 mm
Dpad	0.200 mm
Dsm	0.275 mm
Stencil thickness	0.08 mm

Marking example

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

Package information STM32C011x4/x6

Figure 33. WLCSP12 package marking example

STM32C011x4/x6 Package information

6.4 TSSOP20 package information (YA)

TSSOP20 is a 20-lead, 6.5 x 4.4 mm thin small-outline package with 0.65 mm pitch.

PIN 1 D D D D D D D D D D D D D D D D D D D

Figure 34. TSSOP20 - Outline

1. Drawing is not to scale.

Table 68. TSSOP20 - Mechanical data

| Symbol | millimeters | | | inches ⁽¹⁾ | |-------------------|-------------|-------|-------|-----------------------|--------|--------| | | Min. | Typ. | Max. | Min. | Typ. | Max. | | A | - | - | 1.200 | - | - | 0.0472 | | A1 | 0.050 | - | 0.150 | 0.0020 | - | 0.0059 | | A2 | 0.800 | 1.000 | 1.050 | 0.0315 | 0.0394 | 0.0413 | | b | 0.190 | - | 0.300 | 0.0075 | - | 0.0118 | | C | 0.090 | - | 0.200 | 0.0035 | - | 0.0079 | | D ⁽²⁾ | 6.400 | 6.500 | 6.600 | 0.2520 | 0.2559 | 0.2598 | | E | 6.200 | 6.400 | 6.600 | 0.2441 | 0.2520 | 0.2598 | | E1 ⁽³⁾ | 4.300 | 4.400 | 4.500 | 0.1693 | 0.1732 | 0.1772 | | e | - | 0.650 | - | - | 0.0256 | - | | L | 0.450 | 0.600 | 0.750 | 0.0177 | 0.0236 | 0.0295 | | L1 | - | 1.000 | - | - | 0.0394 | - | | k | 0° | - | 8° | 0° | - | 8° | | aaa | - | - | 0.100 | - | - | 0.0039 |

^1. Values in inches are converted from mm and rounded to four decimal digits.

^2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.

Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.

Package information STM32C011x4/x6

Figure 35. TSSOP20 – Footprint example

1. Dimensions are expressed in millimeters.

6.5 UFQFPN20 package information (A0A5)

This UFQFPN is a 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.

Note: Figure 36 is not to scale.

Refer to the notes section for the list of notes on Figure 36 and Table 69.

Figure 36. UFQFPN20 - Outline Pin 1 0.20 typical diameter N E A B TOP VIEW SIDE VIEW BOTTOM VIEW Odd terminal/ Side detail A 0.20 typ. (Datum A) (Datum B) A3 C SEATING PLANE A1 A C 0.05 C 0.10 2X 0.10 C 2X 0.10 C (NE - 1) X e See detail A 12x Lb Pin num. 1 W/ Protusion N N-1 e (ND - 1) X e 15 typ. 4 See detail A Terminal tip ^{4 e} 0.10 NX b 0.05 M M C C A B 8X La 10 Datum A or B 2 1 8 9

A0A5_ME_V5

Package information STM32C011x4/x6

Table 69. UFQFPN20 - Mechanical data

| Symbol | Millimeters | | | Inches | |--------|-----------------|---------------|-------|-----------------|------------|--------| | | Min | Typ | Max | Min | Typ | Max | | A | 0.500 | 0.550 | 0.600 | 0.0197 | 0.0217 | 0.0236 | | A1 | 0.000 | 0.020 | 0.050 | 0.0000 | 0.0008 | 0.0020 | | A3 | 0.152 reference | | | 0.060 reference | | D | 2.900 | 3.000 | 3.100 | 0.1142 | 0.1181 | 0.1220 | | E | 2.900 | 3.000 | 3.100 | 0.1142 | 0.1181 | 0.1220 | | θ | 0 | - | 12 | 0 | - | 0.0020 | | e | - | 0.500 BSC(11) | - | - | 0.0197 BSC | - | | b(4) | 0.180 | 0.250 | 0.300 | 0.0071 | 0.0098 | 0.0118 | | N(3) | 20 | | | 20 | | ND(5) | 5 | | | 5 | | NE(5) | 5 | | | 5 | | La | 0.300 | 0.350 | 0.400 | 0.0118 | 0.0138 | 0.0157 | | Lb | 0.500 | 0.550 | 0.600 | 0.0197 | 0.0217 | 0.0236 |

Notes:

• 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
• 1. All dimensions are in millimeters except for θ, which is in degrees. Values in inches are converted from millimeters and rounded to four decimal digits.
• 3. N is the total number of terminals.
• 4. Dimension b applies to the metallized terminal and is measured between 0.15 and 0.30 mm from the terminal tip. If the terminal has an optional radius on the other end, dimension b should not be measured in that radius area.
• 5. ND and NE refer to the number of terminals on each D and E side, respectively.
• 1. The maximum package warpage is 0.05 mm.
• 1. The maximum allowable burrs are 0.076 mm in all directions.
• 1. Pin number 1 ID on top is laser marked.
• 1. Bilateral coplanarity zone applies to the terminals.
• 1. Allow chamfered corner lead.
• 11. BSC stands for basic dimensions.

Figure 37. UFQFPN20 - Footprint example

1. Dimensions are expressed in millimeters.

6.6 Thermal characteristics

The operating junction temperature TJ must never exceed the maximum given in Table 23: General operating conditions.

The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:

$$T_J(max) = T_A(max) + P_D(max) \times \Theta_{JA}$$

where:

• TA(max) is the maximum operating ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD = PINT + PI/O,
  • PINT is power dissipation contribution from product of IDD and VDD
  • PI/O is power dissipation contribution from output ports where PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Symbol Parameter Package(1) Value Unit ΘJA Thermal resistance junction-ambient UFQFPN20 76.4 °C/W TSSOP20 88.7 WLCSP12 148 SO8N 100 ΘJB Thermal resistance junction-board UFQFPN20 30 °C/W TSSOP20 54.6 WLCSP12 116.3 SO8N 56 ΘJC Thermal resistance junction-case UFQFPN20 31 °C/W TSSOP20 25.9 WLCSP12 10.6 SO8N 46

Table 70. Thermal resistance

6.6.1 Reference documents

[1] Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) (JESD51-2A), JEDEC, January 2008. Available from www.jedec.org.

^1. Refer to Section 6: Package information for package dimensions

7 Ordering information

TR = tape and reel packing

= tray packing

other = 3-character ID incl. custom flash memory code and packing information

For a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact your nearest ST sales office.

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

• ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise.

STM32C011x4/x6 Revision history

9 Revision history

Table 71. Document revision history

| Date | Revision | Changes | |-------------|----------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--| | 30-Mar-2022 | 1 | Initial release | | 14-Sep-2022 | 2 | Fixed typo errors. | | 9-Dec-2022 | 3 | Updated:
– Table 2, Table 20, Table 27, Table 28, Table 29,
Table 30, Table 36, Table 40, Table 56
– Figure 4, Figure 9, Figure 20, Figure 21
– title of Figure 3 and Figure 4 | | 18-Jan-2024 | 4 | Updated:
– Cover page
– Section Features, Section 1: Introduction (added
reference to reference manual and errata sheet),
Section 3.5: Boot modes, Section 3.7.1: Power supply
schemes, Section 3.9: Clocks and startup,
Section 3.15.1: Advanced-control timer (TIM1)
Section 3.18: Universal synchronous/asynchronous
receiver transmitter (USART), Section 5.2: Absolute
maximum ratings, Section : USART (SPI mode)
characteristics, Section 5.3.6: Wake-up time from low
power modes, section I/O system current
consumption, section General input/output
characteristics, section USART (SPI mode)
characteristics, Section 5.3.18: Timer characteristics,
and Section 6: Package information
– Table 7, Table 12, Table 20, Table 27, Table 44,
Table 45, Table 50, Table 57, Table 62,
– Figure 1, Figure 2, Figure 18, Figure 21, Figure 24,
Figure 25
Added:
– Section 6.6: Thermal characteristics
– Figure 22 and Figure 23 | Revision history STM32C011x4/x6

Table 71. Document revision history (continued)

| Date | Revision | Changes | |-------------|----------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--| | 11-Feb-2026 | 5 | Updated:
– Cover page,
– Section 1: Introduction,
– Section 2: Description,
– Section 3.3: Embedded flash memory,
– Section 3.5: Boot modes,
– Section 3.15: Timers and watchdogs,
– Section 3.17: Inter-integrated circuit interface (I2C),
– Section : USART (SPI mode) characteristics
– Section 6: Package information,
– Figure 17, Figure 22 to Figure 28
– Table 20, Table 21, Table 23, Table 29, Table 44,
Table 44, Table 48, Table 49, Table 50, Table 51,
Table 54, Table 57, Table 58, Table 61, Table 62,
Table 70,
Added Table 53, Section 3.3.1: Securable area. |

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2026 STMicroelectronics – All rights reserved

DS13866 Rev 5 97/97

The definition and values of input/output AC characteristics are given in Figure 18 and Table 51, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Table 51. I/O AC characteristics

| Speed | Symbol | Parameter ⁽¹⁾⁽²⁾ | Conditions | Min | Max | Unit | |-------|--------|------------------------------------------|---------------------------------------------|-----|--------|---------|--| | | | | C=50 pF, 2.7 V ≤ V _DDIO1 ≤ 3.6 V | - | 2 | | | Fmax | | C=50 pF, 2.0 V ≤ V _DDIO1 ≤ 2.7 V | - | 0.35 | MHz | | | Fillax | iviaximum frequency | C=10 pF, 2.7 V ≤ V _DDIO1 ≤ 3.6 V | - | 3.00 | IVII IZ | | 00 | | | C=10 pF, 2.0 V ≤ V _DDIO1 ≤ 2.7 V | - | 0.45 | | 00 | | | C=50 pF,2.7 V ≤ V _DDIO1 ≤ 3.6 V | - | 100.00 | | | Tr/Tf | Output rise and fall time ⁽³⁾ | C=50 pF, 2.0 V ≤ V _DDIO1 ≤ 2.7 V | - | 225.00 | | | 11/11 | Output rise and fail time. | C=10 pF, 2.7 V ≤ V _DDIO1 ≤ 3.6 V | - | 75.00 | ns | | | | | C=10 pF, 2.0 V ≤ V _DDIO1 ≤ 2.7 V | - | 150.00 | ^2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

^3. Specified by design. Not tested in production.

Table 51. I/O AC characteristics (continued)

| Speed | Symbol | Parameter(1)(2) | Conditions | Min | Max | Unit | |-------|--------|------------------------------|---------------------------------|-----|----------|------|--| | | | | C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 10.00 | | | | Maximum frequency | C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 2.00 | MHz | | | Fmax | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 15.00 | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 2.50 | | 01 | | | C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 30.00 | | | | Output rise and fall time(3) | C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 60.00 | | | Tr/Tf | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 15.00 | ns | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 30.00 | | | | | C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 30.00 | | | | Maximum frequency | C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 15.00 | | | Fmax | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 60.00(4) | MHz | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 30.00 | | 10 | | Output rise and fall time(3) | C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 11.00 | | | | | C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 22.00 | ns | | | Tr/Tf | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 4.00 | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 8.00 | | | | | C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 60.00(4) | | | | | C=30 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 30.00 | | | Fmax | Maximum frequency | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 80.00(4) | MHz | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 40.00 | | 11 | | | C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 5.50 | | | | Output rise and fall time(3) | C=30 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 11.00 | ns | | | Tr/Tf | | C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V | - | 2.50 | | | | | C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V | - | 5.00 | ^1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the RM0490 reference manual for a description of GPIO Port configuration register.

^2. Specified by design. Not tested in production.

^3. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.

^4. This value represents the I/O capability but the maximum system frequency is limited to 48 MHz.

Figure 18. I/O AC characteristics definition(1)

1. Refer to Table 51: I/O AC characteristics.

Stresses above the absolute maximum ratings listed in Table 20, Table 21 and Table 22 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.

All voltages are defined with respect to VSS.

Table 20. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
VDD	External supply voltage	- 0.3	4.0	V
VIN(1)	Input voltage on pin	- 0.3	VDDIO1 + 4.0(2)(3)	V

• 1. VIN maximum must always be respected. Refer to Table 21 for the maximum allowed injected current values.
• 1. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
• 1. When an FT_a pin is used by an analog peripheral such as ADC, the maximum VIN is 4 V.

Table 21. Current characteristics

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)	100	mA
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)	100	mA
	Output current sunk by any I/O and control pin	20
IIO(PIN)	Output current sourced by any I/O and control pin	20	mA
	Total output current sunk by sum of all I/Os and control pins(1)	80
∑I(PIN)	Total output current sourced by sum of all I/Os and control pins(1)	80	mA
IINJ(PIN)(1)(2)	Injected current on a FT_xx pin	-5 / NA	mA
∑IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(3)	-25	mA

^1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

Table 22. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	130	°C

^2. A positive injection is induced by VIN > VDDIO1 while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.

^3. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

The operating junction temperature TJ must never exceed the maximum given in Table 23: General operating conditions.

The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:

$$T_J(max) = T_A(max) + P_D(max) \times \Theta_{JA}$$

where:

• TA(max) is the maximum operating ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD = PINT + PI/O,
  • PINT is power dissipation contribution from product of IDD and VDD
  • PI/O is power dissipation contribution from output ports where PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Symbol Parameter Package(1) Value Unit ΘJA Thermal resistance junction-ambient UFQFPN20 76.4 °C/W TSSOP20 88.7 WLCSP12 148 SO8N 100 ΘJB Thermal resistance junction-board UFQFPN20 30 °C/W TSSOP20 54.6 WLCSP12 116.3 SO8N 56 ΘJC Thermal resistance junction-case UFQFPN20 31 °C/W TSSOP20 25.9 WLCSP12 10.6 SO8N 46

Table 70. Thermal resistance

6.6.1 Reference documents

[1] Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) (JESD51-2A), JEDEC, January 2008. Available from www.jedec.org.

^1. Refer to Section 6: Package information for package dimensions