Overview

Part: Sitronix (Part number not specified)

Type: Display Driver IC

Key Specs:

Interface Pixel Formats: 12-bit/pixel (RGB 4-4-4-bit), 16-bit/pixel (RGB 5-6-5-bit), 18-bit/pixel (RGB 6-6-6-bit)
Color Depths: 4K-Colors, 65K-Colors, 262K-Colors
MCU Parallel Interface Bus Widths: 8-bit, 9-bit, 16-bit, 18-bit

Features:

8080 Series MCU Parallel Interface (18/16/9/8-bit Bus)
Serial Interface (3-line, 4-line, 2 data lane)
RGB Interface
Display Data RAM (DDRAM)
Vertical Scroll Mode
Tearing Effect
Power On/Off Sequence Control
Gamma Correction
Display Dimming
Content Adaptive Brightness Control (CABC)
Software Reset
Sleep In/Out Modes
Partial Display Mode
Normal Display Mode
Display Inversion
Display On/Off Control
Memory Write/Read Functions
Interface Pixel Format Selection

Applications:

null

Package:

Bare die / Chip-on-Glass (implied by "PAD ARRANGEMENT", "OUTPUT BUMP DIMENSION", "INPUT BUMP DIMENSION", "CHIP INFORMATION")

Features

Single chip TFT-LCD Controller/Driver with On-chip Frame Memory (FM)
Display Resolution: 240*RGB (H) *320(V)
Frame Memory Size: 240 x 320 x 18-bit = 1,382,400 bits
LCD Driver Output Circuits
- Source Outputs: 240 RGB Channels
- Gate Outputs: 320 Channels
- Common Electrode Output
Display Colors (Color Mode)
- Full Color: 262K, RGB=(666) max., Idle Mode Off
- Color Reduce: 8-color, RGB=(111), Idle Mode On
Programmable Pixel Color Format (Color Depth) for Various Display Data input Format
- 12-bit/pixel: RGB=(444)
- 16-bit/pixel: RGB=(565)
- 18-bit/pixel: RGB=(666)
MCU Interface
- Parallel 8080-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit)
- 6/16/18 RGB Interface(VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0])
- Serial Peripheral Interface(SPI Interface)
- VSYNC Interface
Display Features
- Programmable Partial Display Duty
- CABC for saving current consumption
- Color enhancement
On Chip Build-In Circuits
- DC/DC Converter
- Adjustable VCOM Generation
- Non-Volatile (NV) Memory to Store Initial Register Setting and Factory Default Value (Module ID, Module Version, etc)
- Timing Controller
- 4 preset Gamma curve with separated RGB Gamma setting
Build-In NV Memory for LCD Initial Register Setting
- 8-bits for ID1 setting
- 8-bits for ID2 setting
- 8-bits for ID3 setting
- 6-bits for VCOM Offset adjustment
Driving Algorithm

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Dot Inversion
Column Inversion
Wide Supply Voltage Range
- I/O Voltage (VDDI to DGND): 1.65V ~ 3.3V (VDDI VDD) ≦
- Analog Voltage (VDD to AGND): 2.4V ~ 3.3V
On-Chip Power System
- Source Voltage (VAP (GVDD) to VAN (GVCL)): +6.4~-4.6V
- VCOM level: GND
- Gate driver HIGH level (VGH to AGND): +12.2V ~ +14.97V
- Gate driver LOW level (VGL to AGND): -12.5V ~ -7.16V
Optimized layout for COG Assembly
Operate temperature range: -30°C to +85°C
Lower Power Consumption

Pin Configuration

3-line serial interface Ⅰ

Pin Name	Description

4-line serial interface Ⅰ

Pin Name	Description
CSX	Chip selection signal
	Data is regarded as a command when WRX is low
WRX	Data is regarded as a parameter or data when WRX is high
DCX	Clock signal
SDA	Serial input/output data

3-line serial interface Ⅱ

Pin Name	Description
CSX	Chip selection signal
DCX	Clock signal
SDA	Serial input data
SDO	Serial output data

4-line serial interface Ⅱ

Pin Name	Description
CSX	Chip selection signal
	Data is regarded as a command when WRX is low
WRX	Data is regarded as a parameter or data when WRX is high

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DCX	Clock signal
SDA	Serial input data
SDO	Serial output data

Table 14 pin description of serial interface

Electrical Characteristics

7.1 Absolute Operation Range

Item	Symbol	Rating	Unit
Supply Voltage	VDD	- 0.3 ~ +4.6	V
Supply Voltage (Logic)	VDDI	- 0.3 ~ +4.6	V
Driver Supply Voltage	VGH-VGL	-0.3 ~ +30.0	V
Logic Input Voltage Range	VIN	-0.3 ~ VDDI + 0.5	V
Logic Output Voltage Range	VO	-0.3 ~ VDDI + 0.5	V
Operating Temperature Range	TOPR	-30 ~ +85	°C
Storage Temperature Range	TSTG	-40 ~ +125	°C

Table 1 Absolute Operation Range

Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the recommend range.

7.2 DC Characteristics

			Specification				Related
Parameter	Symbol	Condition	MIN.	TYP.	MAX.	Unit	Pins
Power & Operation Voltage
System Voltage	VDD	Operating voltage	2.4	2.75	3.3	V
Interface Operation Voltage	VDDI	I/O Supply Voltage	1.65	1.8	3.3	V
Gate Driver High Voltage	VGH		12.2		14.97	V	Note 4
Gate Driver Low Voltage	VGL		-12.5		-7.16	V
Gate Driver Supply Voltage		VGH-VGL Input / Output	19.36		27.47	V	Note 5
Logic-High Input Voltage	VIH		0.7VDDI		VDDI	V	Note 1
Logic-Low Input Voltage	VIL		VSS		0.3VDDI	V	Note 1
Logic-High Output Voltage	VOH	IOH = -1.0mA	0.8VDDI		VDDI	V	Note 1
Logic-Low Output Voltage	VOL	IOL = +1.0mA	VSS		0.2VDDI	V	Note 1
Logic-High Input Current	IIH	VIN = VDDI			1	uA	Note 1
Logic-Low Input Current	IIL	VIN = VSS	-1			uA	Note 1
Input Leakage Current	IILK	VIN = VSS or VDDI	-0.1		+0.1	uA	Note 1
VCOM Voltage
VCOM amplitude	VCOM			VSS		V
Source Driver
Source Output Range	Vsout		VAN		VAP	V
Gamma Reference Voltage(Positive)	VAP		4.45		6.4	V	Note 6
Gamma Reference Voltage(Negative)	VAN		-4.6		-2.65	V
Source Output Settling Time	Tr	Below with 99% precision			20	us	Note 2
Output Offset Voltage	VOFFSET				35	mV	Note 3

Table 2 Basic DC Characteristics

Notes:

TA= -30 to 70 (to +85 no damage). °C °C
Source channel loading= 2KΩ+12pF/channel, Gate channel loading=5KΩ+40pF/channel.
The Max. value is between measured point of source output and gamma setting value.
When evaluating the maximum and minimum of VGH, VDD=2.8V.

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1. The maximum value of |VGH-VGL| can no over 30V.
6. Default register setting of Vcom and Vcomoffset is 20h

7.3 Power Consumption

Ta=25°C, Frame rate = 60Hz, Registers setting are IC default setting.

	Image	Current Consumption

Operation Mode		IDDI
		(mA)
Normal Mode	Black	0.005
Partial + Idle Mode (48 lines)	Black	0.005
Sleep-in Mode	N/A	0.005

Table 3 Power Consumption

Notes:

The Current Consumption is DC characteristics of ST7789VW.
Typical: VDDI=1.8V, VDD=2.75V; Maximum: VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V

7.4 AC Characteristics

VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25°C

Signal	Symbol	Parameter	Min	Unit	Description
	TAST	Address setup time	0	ns
D/CX	TAHT	Address hold time (Write/Read)	10	ns	-
	TCHW	Chip select "H" pulse width	0	ns
	TCS	Chip select setup time (Write)	15	ns
	TRCS	Chip select setup time (Read ID)	45	ns
CSX	TRCSFM	Chip select setup time (Read FM)	355	ns	-
	TCSF	Chip select wait time (Write/Read)	10	ns
	TCSH	Chip select hold time	10	ns
	TWC	Write cycle	66	ns
WRX	TWRH	Control pulse "H" duration	15	ns
	TWRL	Control pulse "L" duration	15	ns
	TRC	Read cycle (ID)	160	ns
RDX (ID)	TRDH	Control pulse "H" duration (ID)	90	ns	When read ID data
	TRDL	Control pulse "L" duration (ID)	45	ns
RDX (FM)	TRCFM	Read cycle (FM)	450	ns
	TRDHFM	Control pulse "H" duration (FM)	90	ns	When read from
	TRDLFM	Control pulse "L" duration (FM)	355	ns	frame memory
D[17:0]	TDST	Data setup time	10	ns	For CL=30pF

TDHT	Data hold time	10		ns
TRAT	Read access time (ID)		40	ns
TRATFM	Read access time (FM)		340	ns
TODH	Output disable time	20	80	ns

Figure 2 Rising and Falling Timing for I/O Signal

Figure 3 Write-to-Read and Read-to-Write Timing

Note: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.

Figure 4 3-line serial Interface Timing Characteristics

VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25°C

Signal	Symbol	Parameter	Min	Max	Unit	Description
	TCSS	Chip select setup time (write)	15		ns
	TCSH	Chip select hold time (write)	15		ns
CSX	TCSS	Chip select setup time (read)	60		ns
	TSCC	Chip select hold time (read)	65		ns
	TCHW	Chip select "H" pulse width	40		ns
	TSCYCW	Serial clock cycle (Write)	16		ns
	TSHW	SCL "H" pulse width (Write)	7		ns
	TSLW	SCL "L" pulse width (Write)	7		ns
SCL	TSCYCR	Serial clock cycle (Read)	150		ns
	TSHR	SCL "H" pulse width (Read)	60		ns
	TSLR	SCL "L" pulse width (Read)	60		ns
SDA	TSDS	Data setup time	7		ns
(DIN)	TSDH	Data hold time	7		ns
	TACC	Access time	10	50	ns	For maximum CL=30pF
DOUT	TOH	Output disable time	15	50	ns	For minimum CL=8pF

Table 5 3-line serial Interface Characteristics

Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.

7.4.3 Serial Interface Characteristics (4-line serial):

Figure 5 4-line serial Interface Timing Characteristics

VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25°C

Signal	Symbol	Parameter	MIN	MAX	Unit	Description
	TCSS	Chip select setup time (write)	15		ns
	TCSH	Chip select hold time (write)	15		ns
CSX	TCSS	Chip select setup time (read)	60		ns
	TSCC	Chip select hold time (read)	65		ns
	TCHW	Chip select "H" pulse width	40		ns
	TSCYCW	Serial clock cycle (Write)	16		ns
	TSHW	SCL "H" pulse width (Write)	7		ns	-write command & data
	TSLW	SCL "L" pulse width (Write)	7		ns	ram
SCL	TSCYCR	Serial clock cycle (Read)	150		ns
	TSHR	SCL "H" pulse width (Read)	60		ns	-read command & data
	TSLR	SCL "L" pulse width (Read)	60		ns	ram
	TDCS	D/CX setup time	10		ns
D/CX	TDCH	D/CX hold time	10		ns
SDA	TSDS	Data setup time	7		ns
(DIN)	TSDH	Data hold time	7		ns
	TACC	Access time	10	50	ns	For maximum CL=30pF
DOUT	TOH	Output disable time	15	50	ns	For minimum CL=8pF

Table 6 4-line serial Interface Characteristics

Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as

30% and 70% of VDDI for Input signals.

Figure 6 RGB Interface Timing Characteristics

VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25°C

Signal	Symbol	Parameter	MIN	MAX	Unit
HSYNC,
VSYNC	TSYNCS	VSYNC, HSYNC Setup Time	30	-	ns
ENABLE	TENS	Enable Setup Time	25	-	ns
	TENH	Enable Hold Time	25	-	ns
	PWDH	DOTCLK High-level Pulse Width	60	-	ns
	PWDL	DOTCLK Low-level Pulse Width	60	-	ns
DOTCLK	TCYCD	DOTCLK Cycle Time	120	-	ns
	Trghr, Trghf	DOTCLK Rise/Fall time	-	20	ns
DB	TPDS	PD Data Setup Time	50	-	ns
	TPDH	PD Data Hold Time	50	-	ns

Signal	Symbol	Parameter	MIN	MAX	Unit
HSYNC,
VSYNC	TSYNCS	VSYNC, HSYNC Setup Time	35	-	ns
ENABLE	TENS	Enable Setup Time	35	-	ns

	TENH	Enable Hold Time	35	-	ns
DOTCLK	PWDH	DOTCLK High-level Pulse Width	35	-	ns
	PWDL	DOTCLK Low-level Pulse Width		-	ns
	TCYCD	DOTCLK Cycle Time	80	-	ns
	Trghr, Trghf	DOTCLK Rise/Fall time	-	10	ns
	TPDS	PD Data Setup Time	35	-	ns
DB	TPDH	PD Data Hold Time	35	-	ns

7.4.5 Reset Timing:

Figure 7 Reset Timing

VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25°C

Related Pins	Symbol	Parameter	MIN	MAX	Unit

Table 9 Reset Timing

Notes:

The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NVM (or similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX.
Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below:

RESX Pulse	Action
Shorter than 5us	Reset Rejected
Longer than 9us	Reset
Between 5us and 9us	Reset starts

During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode.) and then return to Default condition for Hardware Reset.
Spike Rejection also applies during a valid reset pulse as shown below:

1. When Reset applied during Sleep In Mode.
1. When Reset applied during Sleep Out Mode.

It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec.

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

8 FUNCTION DESCRIPTION

8.1 MPU Interface Type Selection

ST7789VW supports 8/16/9/18 bit parallel data bus for 8080 series CPU, RGB serial interfaces. Selection of these interfaces are set by IM[3:0] pins as shown below.

IM3	IM2	IM1	IM0	Interface	Read Back Data Bus Selection
0	0	0	0	80-8bit parallel I/F	DB[7:0]
0	0	0	1	80-16bit parallel I/F	DB[15:0]
0	0	1	0	80-9bit parallel I/F	DB[8:0]
0	0	1	1	80-18bit parallel I/F	DB[17:0],
	0 1 0
			1	2 data lane serial I/F	SDA: in/out, WRX: in
0	1	1	0	4-line 8bit serial I/F	SDA: in/out
1	0	0	0	80-16bit parallel I/F Ⅱ	DB[17:10], DB[8:1]
1	0	0	1	80-8bit parallel I/F Ⅱ	DB[17:10]
1	0	1	0	80-18bit parallel I/F Ⅱ	DB[17:0],
1	0	1	1	80-9bit parallel I/F Ⅱ	DB[17:9]
1	1	0	1	3-line 9bit serial I/F Ⅱ SDA: in/ SDO: out
1	1	1	0	4-line 8bit serial I/F Ⅱ SDA: in/ SDO: out

8.2 8080- Series MCU Parallel Interface Ⅰ

The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low) enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write enable, RDX is the parallel data read enable and D[17:0] is parallel data bus.

The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX='1', D[17:0] bits is either display data or command parameter. When D/C='0', D[17:0] bits is command. The interface functions of 8080-series parallel interface are given in following table.

IM3	IM2	IM1	IM0	Interface	D/CX	RDX	WRX	Read back selection
					0	1	↑	Write 8-bit command (D7 to D0)
			0	8-bit	1	1	↑	Write 8-bit display data or 8-bit parameter (D7 to D0)
0	0	0		parallel	1 1	↑ ↑	1 1	Read 8-bit display data (D7 to D0) Read 8-bit parameter or status (D7 to D0)
		0	1		0	1	↑	Write 8-bit command (D7 to D0)
				16-bit	1	1	↑	Write 16-bit display data or 8-bit parameter (D15 to D0)
0	0			parallel	1 1	↑ ↑	1 1	Read 16-bit display data (D15 to D0) Read 8-bit parameter or status (D7 to D0)
0		1	0		0	1	↑	Write 8-bit command (D7 to D0)
				9-bit	1	1	↑	Write 9-bit display data or 8-bit parameter (D8 to D0)
				parallel	1 1	↑ ↑	1 1	Read 9-bit display data (D8 to D0) Read 8-bit parameter or status (D7 to D0)
0		1	1		0	1	↑	Write 8-bit command (D7 to D0)
				18-bit	1	1	↑	Write 18-bit display data or 8-bit parameter (D17 to D0)
	0			parallel	1 1	↑ ↑	1 1	Read 18-bit display data (D17 to D0) Read 8-bit parameter or status (D7 to D0)

8.2.1 Write cycle sequence

The write cycle means that the host writes information (command / data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control signals (DCX, RDX, WRX) and data signals (DB[17:0]). DCX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (='0') and vice versa it is data (='1').

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Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

Figure 8 8080-Series WRX Protocol

Note: WRX is an unsynchronized signal (It can be stopped).

Figure 9 8080-Series Parallel Bus Protocol, Write to Register or Display RAM

8.2.2 Read cycle sequence

The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX.

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

Figure 10 8080-series RDX protocol

Note: RDX is an unsynchronized signal (It can be stopped).

Figure 11 8080-series parallel bus protocol, read data from register or display RAM

8.3 8080- series MCU Parallel Interface Ⅱ

The MCU uses one of following interface: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-lines with 16-data parallel interface, or 21-lines with 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data bus.

The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX='1', D[17:0] bits is either display data or command parameter. When D/C='0', D[17:0] bits is command.

The 8080- series bi Ⅱ -directional interface can be used for communication between the micro controller and LCD driver. Interface bus width can be selected with IM3, IM2, IM1 and IM0.The interface functions of 8080- series parallel interface Ⅱ are given in Table 12 The function of 8080-Ⅱ series parallel interface.

	IM3 IM2 IM1 IM0			Interface	D/CX	RDX	WRX	Function
1		0	0	16-bit Parallel	0	1	↑	Write 8-bit command (D[8:1])
	0				1 1 1	1 ↑ ↑	↑ 1 1	Write 16-bit display data or 8-bit parameter (D[17:10], D[8:1]) Read 16-bit Display data (D[17:10], D[8:1]) Read 8-bit parameter or status (D[8:1])
		0	1	8-bit Parallel	0	1	↑	Write 8-bit command (D[17:10])
1					1	1	↑	Write 8-bit display data or 8-bit parameter (D[17:10])
	0				1 1	↑ ↑	1 1	Read 8-bit Display data (D[17:10]) Read 8-bit parameter or status (D[17:10])
			0	18-bit Parallel	0	1	↑	Write 8-bit command (D[8:1])
1	0	1			1 1 1	1 ↑ ↑	↑ 1 1	Write 18-bit display data or 8-bit parameter (D[17:0], D[8:1]) Read 18-bit Display data (D[17:0]) Read 8-bit parameter or status (D[8:1])
	0	1	1	9-bit Parallel	0	1	↑	Write 8-bit command (D[17:10])
1					1 1 1	1 ↑ ↑	↑ 1 1	Write 9-bit display data or 8-bit parameter (D[17:9]) Read 9-bit Display data (D[17:9]) Read 8-bit parameter or status (D[17:10])

Table 12 The function of 8080- series parallel interface Ⅱ

IM3	IM2	IM1	IM0	Interface	Read back selection
0	1	0	1	3-line serial interface Ⅰ
0	1	1	0	4-line serial interface Ⅰ	Via the read instruction (8-bit, 24-bit and 32-bit read
1	1	0	1	3-line serial interface Ⅱ	parameter)
1	1	1	0	4-line serial interface Ⅱ

8.4 Serial Interface

Table 13 Selection of serial interface

The serial interface is either 3-lines/9-bits or 4-lines/8-bits bi-directional interface for communication between the micro controller and the LCD driver. The 3-lines serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output), and the 4-lines serial interface use: CSX (chip enable), D/CX (data/ command flag), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary.

8.4.1 Pin description

3-line serial interface Ⅰ

Pin Name	Description

4-line serial interface Ⅰ

Pin Name	Description
CSX	Chip selection signal
	Data is regarded as a command when WRX is low
WRX	Data is regarded as a parameter or data when WRX is high
DCX	Clock signal
SDA	Serial input/output data

3-line serial interface Ⅱ

Pin Name	Description
CSX	Chip selection signal
DCX	Clock signal
SDA	Serial input data
SDO	Serial output data

4-line serial interface Ⅱ

Pin Name	Description
CSX	Chip selection signal
	Data is regarded as a command when WRX is low
WRX	Data is regarded as a parameter or data when WRX is high

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DCX	Clock signal
SDA	Serial input data
SDO	Serial output data

Table 14 pin description of serial interface

8.4.2 Command write mode

The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data packet contains a control bit D/CX and a transmission byte. In 4-lines serial interface, data packet contains just transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is "low", the transmission byte is interpreted as a command byte. If D/CX is "high", the transmission byte is stored in the display data RAM (memory write command), or command register as parameter.

Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission.

Figure 12 Serial interface data stream format

When CSX is "high", SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low. SDA is sampled at the rising edge of SCL. D/CX indicates whether the byte is command (D/CX='0') or parameter/RAM data (D/CX='1'). D/CX is sampled when first rising edge of SCL (3-line serial interface) or 8th rising edge of SCL (4-line serial interface). If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-line serial interface) or D7

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(4-line serial interface) of the next byte at the next rising edge of SCL..

Figure 13 3-line serial interface write protocol (write to register with control bit in transmission)

8.4.3 Read function

The read mode of the interface means that the micro controller reads register value from the driver. To achieve read function, the micro controller first has to send a command (read ID or register command) and then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the rising edge of SCL.

After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of the last bit.

8.4.4 3-line serial interface / Ⅰ Ⅱ protocol

3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):

3-line serial protocol (for RDDID command: 24-bit read)

3-line Serial Protocol (for RDDST command: 32-bit read)

Figure 15 3-line serial interface read protocol

8.4.5 4-line serial protocol

4-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):

4-line Serial Protocol (for RDDST command: 32-bit read)

Figure 16 4-line serial interface read protocol

8.4.6 2 data lane serial Interface

Interface selection:

IM3	IM2	IM1	IM0	Interface	Read back selection
					Via the read instruction (8-bit, 24-bit and 32-bit
0	1	0	1	2 data lane serial interface	read)

Table 15 IM pin selection

2-wire data lane serial interface use: CSX (chip enable), DCX (serial clock) and SDA (serial data input/output 1), and WRX (serial data input 2). To enter this interface, command E7h need set 10h.

2 data lane hardware suggestion and Pin description:

2 data lane serial interface, IM[3:0]=0101

2 data lane serial interface

Figure 17 Hardware suggestion of 2 data lane serial interface

Pin Name	Description

Table 16 Pin description of 2 data lane serial interface

Command write mode:

The command write protocol of 2-wire data lane serial interface is the same with the 3-line serial interface, so users can ignore the input data of WRX.

Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission.

SRAM write mode:

The SRAM write mode of 2-wire data line serial interface need use SDA pin and WRX pin to be data input pins.

Read function:

The read mode of 2-wire data lane serial interface is the same with the 3-line serial interface and WRX pin can be ignored. To achieve read function, the micro controller first has to send a command (read ID or register command) and then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the rising edge of SCL.

After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of the last bit.

3-line serial interface Ⅰ/Ⅱ protocol:

3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):

3-line Serial Protocol (for RDDST command: 32-bit read)

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Figure 19 3-line serial interface read protocol

8.5 Data Transfer Break and Recovery

If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been HIGH state.

If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated.

If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below.

Figure 20 Write interrupts recovery (serial interface)

If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value.

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

Figure 21 Write interrupts recovery (both serial and parallel Interface)

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8.6 Data Transfer Pause

It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then the display module will receive either the command's parameters (if appropriate) or a new command when the chip select line is next enabled as shown below.

This applies to the following 4 conditions:

1. Command-Pause-Command
1. Command-Pause-Parameter
1. Parameter-Pause-Command
1. Parameter-Pause-Parameter

8.6.1 Parallel interface pause

Figure 22 Parallel bus pause protocol (paused by CSX)

8.7 Data Transfer Mode

The module has three kinds color modes for transferring data to the display RAM. These are 12-bit color per pixel, 16-bit color per pixel and 18-bit color per pixel. The data format is described for each interface. Data can be downloaded to the frame memory by 2 methods.

8.7.1 Method 1

The image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame memory pointer is reset to the start point and the next frame is written.

8.7.2 Method 2

The image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write. Then start memory write command is sent, and a new frame is downloaded.

Start frame Frame 1 Memory write Image data			Any command	Start frame Memory write	Frame 2 Image data	Any command
	Stop Any command

Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in

the frame memory.

8.8 Data Color Coding

8.8.1 8080- series Ⅰ 8-bit Parallel Interface

The 8080- series 8 Ⅰ -bit parallel interface of ST7789VW can be used by setting IM[3:0]="0000b". Different display data formats are available for three Colors depth supported by listed below.

4k colors, RGB 4,4,4-bit input.
65k colors, RGB 5,6,5-bit input.
262k colors, RGB 6,6,6-bit input.

8.8.2 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah="03h"

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There is 1pixel (3 sub-pixels) per 2-byte

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data.

Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.

Note 3: '-' = Don't care – Can be set to '0' or '1'

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8.8.4 8-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h"

There is 1pixel (3 sub-pixels) per 3-bytes.

Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

8.8.5 8080- series Ⅱ 8-bit Parallel Interface

The 8080- series 8 Ⅱ -bit parallel interface of ST7789VW can be used by setting IM[3:0]="1001b". Different display data formats are available for three Colors depth supported by listed below.

65k colors, RGB 5,6,5-bit input.
262k colors, RGB 6,6,6-bit input.

8.8.6 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3Ah="05h"

Note 1: The data order is as follows, MSB=D17, LSB=D10 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data.

Note 2: 2-times transfer transmit 1 pixel data with the 16-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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Note 1: The data order is as follows, MSB=D17, LSB=D10 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

8.8.8 8080- series 16 Ⅰ -Bit Parallel Interface

The 8080- series 16 Ⅰ -bit parallel interface of ST7789VW can be used by setting IM[3:0]="0001b". Different display data formats are available for three colors depth supported by listed below.

4k colors, RGB 4,4,4-bit input
65k colors, RGB 5,6,5-bit input
262k colors, RGB 6,6,6-bit input

There is 1pixel (3 sub-pixels) per 1byte

Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.

There is 1 pixel (3 sub-pixels) per 1 byte

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data.

Note 2: 1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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8.8.11 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h",

MDT[1:0]="00b"

There are 2 pixels (6 sub-pixels) per 3 bytes

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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8.8.12 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h", MDT[1:0]="01b"

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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8.8.15 8080- series 16 Ⅱ -Bit Parallel Interface

The 8080- series 16 Ⅱ -bit parallel interface of ST7789VW can be used by setting IM[3:0]="1000b". Different display data formats are available for two colors depth supported by listed below.

65k colors, RGB 5,6,5-bit input
262k colors, RGB 6,6,6-bit input

8.8.16 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input) 65K-Color, 3Ah="05h"

There is 1 pixel (3 sub-pixels) per 1 byte

Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data.

Note 2: 1-times transfer (D17~~D10, D8~~D1) is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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8.8.17 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h",

MDT[1:0]="00b"

There are 2 pixels (6 sub-pixels) per 3 bytes

Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

8.8.19 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h",

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Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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8.8.21 8080- series 9 Ⅰ -Bit Parallel Interface

The 8080- series 9 Ⅰ -bit parallel interface of ST7789VW can be used by setting IM[3:0]="0010b"Different display data formats are available for two colors depth supported by listed below.

-65k colors, RGB 5,6,5-bit input

-262k colors, RGB 6,6,6-bit input

8.8.22 Write 9-bit data for RGB 5-6-5-bit input (65K-Color), 3Ah="05h"

Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 4, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-time transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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There is 1 pixel (3 sub-pixels) per 2bytes

Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-time transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

8.8.24 Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah="06h", MDT[1:0]="01b"

Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-time transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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8.8.25 8080- series 9 Ⅱ -bit Parallel Interface

The 8080- series 9 Ⅱ -bit parallel interface of ST7789VW can be used by setting IM[3:0]="1011b"Different display data formats are available for two colors depth supported by listed below.

-65k colors, RGB 5,6,5-bit input

-262k colors, RGB 6,6,6-bit input

8.8.26 Write 9-bit data for RGB 5-6-5-bit input (65K-Color), 3Ah="05h"

Note 1: The data order is as follows, MSB=D16, LSB=D9 and picture data is MSB=Bit 4, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-time transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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There is 1 pixel (3 sub-pixels) per 2bytes

Note 1: The data order is as follows, MSB=D17, LSB=D9 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 2-time transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

8.8.28 Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah="06h", MDT[1:0]="01b"

Note 1: The data order is as follows, MSB=D16, LSB=D11 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-time transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care – Can be set to '0' or '1'

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8.8.29 8080- series 18 Ⅰ -Bit Parallel Interface

The 8080- seri Ⅰ es 18-bit parallel interface of ST7789VW can be used by setting IM[3:0]="0011b". Different display data formats are available for three colors depth supported by listed below.

4k colors, RGB 4,4,4-bit input
65k colors, RGB 5,6,5-bit input
262k colors, RGB 6,6,6-bit input.

- - - G1, Bit 3 - G1, Bit 2 - G1, Bit 1 - G1, Bit 0 - 8080-series control pins RESX CSX D/CX "1" WRX RDX "1" D15 D14 D13 D12 D11 D10 D9 D8 Pixel n Pixel n+1 12 bits 12 bits R1 G1 B1 R2 G2 B2 R3 G3 B3 18 bits Frame memory R1, Bit 3 0 R1, Bit 2 0 R1, Bit 1 1 R1, Bit 0 0 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 - - - - B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 - - - - B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 - - - - B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 - - - - B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+2 Pixel n+3 Look-Up Table for 4096 Color data mapping (12 bits to 18 bits) - - D17 - - - - - - - D16 -

There is 1 pixel (3 sub-pixels) per byte

There is one pixel (3 sub-pixels) per byte

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data.

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Note 2: 1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.

There is 1 pixel (3 sub-pixels) per byte

Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data. Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.

8.8.33 8080- series 18 Ⅱ -Bit Parallel Interface

The 8080- series 18 Ⅱ -bit parallel interface of ST7789VW can be used by setting IM[3:0]="1010b". Different display data formats are available for two colors depth supported by listed below.

65k colors, RGB 5,6,5-bit input
262k colors, RGB 6,6,6-bit input.

8.8.34 18-bit data bus for 16-bit/pixel (RGB-5-6-5-bit input), 65K-colors, 3Ah="05h"

There is one pixel (3 sub-pixels) per byte

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data.

Note 2: 1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.

- - - G1, Bit 3 - G1, Bit 2 - G1, Bit 1 - G1, Bit 0 0 8080-series control pins RESX CSX D/CX "1" WRX RDX "1" D15 D14 D13 D12 D11 D10 D9 D8 Pixel n Pixel n+1 18 bits 18 bits R1 G1 B1 R2 G2 B2 R3 G3 B3 Frame memory R1, Bit 3 0 R1, Bit 2 1 R1, Bit 1 0 R1, Bit 0 1 1 0 0 - D7 D6 D5 D4 D3 D2 D1 D0 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+2 Pixel n+3 - - D17 D16 R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4 G1, Bit 5 G1, Bit 4 G2, Bit 5 G2, Bit 4 G3, Bit 5 G3, Bit 4 G4, Bit 5 G4, Bit 4 B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4 R1, Bit 5 R2, Bit 5 R3, Bit 5 R4, Bit 5 B1, Bit 5 B2, Bit 5 B3, Bit 5 B4, Bit 5

There is 1 pixel (3 sub-pixels) per byte

Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data. Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.

8.8.36 3-Line Serial Interface

Different display data formats are available for three colors depth supported by the LCM listed below.

4k colors, RGB 4-4-4-bit input

65k colors, RGB 5-6-5-bit input

262k colors, RGB 6-6-6-bit input

8.8.37 Write data for 12-bit/pixel (RGB-4-4-4 bit input), 4K-Colors, 3Ah="03h"

Note 1: Pixel data with the 12-bit color depth information Note 2: The most significant bits are: Rx3, Gx3 and Bx3 Note 3: The least significant bits are: Rx0, Gx0 and Bx0

8.8.38 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3Ah="05h"

Note 1: Pixel data with the 16-bit color depth information Note 2: The most significant bits are: Rx4, Gx5 and Bx4 Note 3: The least significant bits are: Rx0, Gx0 and Bx0

8.8.39 Write data for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h"

Note 1: Pixel data with the 18-bit color depth information Note 2: The most significant bits are: Rx5, Gx5 and Bx5 Note 3: The least significant bits are: Rx0, Gx0 and Bx0

8.8.40 4-Line Serial Interface

Different display data formats are available for three colors depth supported by the LCM listed below.

4k colors, RGB 4-4-4-bit input

65k colors, RGB 5-6-5-bit input

262k colors, RGB 6-6-6-bit input

8.8.41 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah="03h"

Note 1. pixel data with the 12-bit color depth information Note 2. The most significant bits are: Rx3, Gx3 and Bx3 Note 3. The least significant bits are: Rx0, Gx0 and Bx0

Note 1. pixel data with the 16-bit color depth information Note 2. The most significant bits are: Rx4, Gx5 and Bx4 Note 3. The least significant bits are: Rx0, Gx0 and Bx0

Note 1. pixel data with the 18-bit color depth information Note 2. The most significant bits are: Rx5, Gx5 and Bx5 Note 3. The least significant bits are: Rx0, Gx0 and Bx0

8.9 RGB Interface

8.9.1 RGB interface Selection

The color format selection of RGB Interface for ST7789VW is selected by setting the RIM and command 3Ah, DB[6:4].

RIM	3Ah, DB[6:4]	RGB Interface Mode	Data pins

8.9.2 RGB Color Format

ST7789VW supports two kinds of RGB interface, DE mode and HV mode, and 6bit/18bit data format. When DE mode is selected and the VSYNC, HSYNC, DOTCLK, DE, D[17:0] pins can be used; when HV mode is selected and the VSYNC, HSYNC, DOTCLK, D[17:0] pins can be used. When using RGB interface, only serial interface can be selected.

16-bit RGB interface Hardware suggestion, IM[3:0]=0101.

Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors

D17	R1, Bit 4			R2, Bit 4			R3, Bit 4					R4, Bit 4	R5, Bit 4
D16	R1, Bit 3		R2, Bit 3				R3, Bit 3					R4, Bit 3	R5, Bit 3
D15	R1, Bit 2			R2, Bit 2			R3, Bit 2					R4, Bit 2	R5, Bit 2
D14	R1, Bit 1			R2, Bit 1			R3, Bit 1					R4, Bit 1	R5, Bit 1
D13	R1, Bit 0			R2, Bit 0			R3, Bit 0					R4, Bit 0	R5, Bit 0
D12	-			-				-				-	-
D11	G1, Bit 5			G2, Bit 5			G3, Bit 5					G4, Bit 5	G5, Bit 5
D10	G1, Bit 4			G2, Bit 4			G3, Bit 4					G4, Bit 4	G5, Bit 4
D9	G1, Bit 3			G2, Bit 3			G3, Bit 3					G4, Bit 3	G5, Bit 3
D8	G1, Bit 2			G2, Bit 2			G3, Bit 2					G4, Bit 2	G5, Bit 2
D7	G1, Bit 1			G2, Bit 1			G3, Bit 1					G4, Bit 1	G5, Bit 1
D6	G1, Bit 0			G2, Bit 0			G3, Bit 0					G4, Bit 0	G5, Bit 0
D5	B1, Bit 4			B2, Bit 4			B3, Bit 4					B4, Bit 4	B5, Bit 4
D4	B1, Bit 3			B2, Bit 3			B3, Bit 3					B4, Bit 3	B5, Bit 3
D3	B1, Bit 2			B2, Bit 2			B3, Bit 2					B4, Bit 2	B5, Bit 2
D2	B1, Bit 1			B2, Bit 1			B3, Bit 1					B4, Bit 1	B5, Bit 1
D1	B1, Bit 0			B2, Bit 0			B3, Bit 0					B4, Bit 0	B5, Bit 0
D0	- Pixel n	16 bits	-	Pixel n+1		16 bits	- Pixel n+2					- Pixel n+3	- Pixel n+4
Frame memory
			R1	G1	B1	R2	G2	B2	R3	G3	B3

18-bit RGB interface hardware suggestion, IM[3:0]=0101.

Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors

D17	R1, Bit 5			R2, Bit 5				R3, Bit 5				R4, Bit 5	R5, Bit 5
D16	R1, Bit 4			R2, Bit 4				R3, Bit 4				R4, Bit 4	R5, Bit 4
D15	R1, Bit 3			R2, Bit 3				R3, Bit 3				R4, Bit 3	R5, Bit 3
D14	R1, Bit 2			R2, Bit 2				R3, Bit 2				R4, Bit 2	R5, Bit 2
D13	R1, Bit 1			R2, Bit 1				R3, Bit 1				R4, Bit 1	R5, Bit 1
D12	R1, Bit 0			R2, Bit 0				R3, Bit 0				R4, Bit 0	R5, Bit 0
D11	G1, Bit 5			G2, Bit 5				G3, Bit 5				G4, Bit 5	G5, Bit 5
D10	G1, Bit 4			G2, Bit 4				G3, Bit 4				G4, Bit 4	G5, Bit 4
D9	G1, Bit 3			G2, Bit 3				G3, Bit 3				G4, Bit 3	G5, Bit 3
D8	G1, Bit 2			G2, Bit 2				G3, Bit 2				G4, Bit 2	G5, Bit 2
D7	G1, Bit 1			G2, Bit 1				G3, Bit 1				G4, Bit 1	G5, Bit 1
D6	G1, Bit 0			G2, Bit 0				G3, Bit 0				G4, Bit 0	G5, Bit 0
D5	B1, Bit 5			B2, Bit 5				B3, Bit 5				B4, Bit 5	B5, Bit 5
D4	B1, Bit 4			B2, Bit 4				B3, Bit 4				B4, Bit 4	B5, Bit 4
D3	B1, Bit 3			B2, Bit 3				B3, Bit 3				B4, Bit 3	B5, Bit 3
D2	B1, Bit 2			B2, Bit 2				B3, Bit 2				B4, Bit 2	B5, Bit 2
D1	B1, Bit 1			B2, Bit 1				B3, Bit 1				B4, Bit 1	B5, Bit 1
D0	B1, Bit 0 Pixel n Frame memory	18 bits		B2, Bit 0 Pixel n+1	18 bits			B3, Bit 0 Pixel n+2				B4, Bit 0 Pixel n+3	B5, Bit 0 Pixel n+4
			R1	G1	B1	R2	G2	B2	R3	G3	B3

6-bit RGB interface hardware suggestion, IM[3:0]=0101.

Write data for 6-bit/pixel (RGB 5-6-5-bit input), 65K-Colors

Write data for 6-bit/pixel (RGB 6-6-6-bit input), 262K-Colors

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

Figure 23 RGB Interface Data Format

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8.9.3 RGB Interface Definition

The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK signals. The data can be written only within the specified area with low power consumption by using window address function. The back porch and front porch are used to set the RGB interface timing.

Figure 24 DRAM Access Area by RGB Interface

Please refer to the following table for the setting limitation of RGB interface signals.

Parameter	Symbol	Min.	Typ.	Max.	Unit
Horizontal Sync. Width	hpw	2	10		Clock
Horizontal Sync. Back Porch	hbp	4	10	hpw+hbp=31	Clock
Horizontal Sync. Front Porch	hfp	2	38	-	Clock
Vertical Sync. Width	vs	2	4		Line
Vertical Sync. Back Porch	vbp	2	4	vs+vbp=127	Line
Vertical Sync. Front Porch	vfp	2	8	-	Line

Typical value are related to the setting of dot clock is 7MHz and frame rate is 70Hz..

If the setting of hpw is 10 dot clocks and hbp is 10 dot clocks, the setting of HBP in command B1h is 20 dot clocks

In with ram mode, hpw+hbp+hfp≧22

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6bit RGB interface:

Parameter	Symbol	Min.	Typ.	Max.	Unit
Horizontal Sync. Width	hpw	6	30		Clock
Horizontal Sync. Back Porch	hbp	12	30	hpw+hbp=93	Clock
Horizontal Sync. Front Porch	hfp	6	60	-	Clock
Vertical Sync. Width	vs	2	4		Line
Vertical Sync. Back Porch	vbp	2	4	vs+vbp=127	Line
Vertical Sync. Front Porch	vfp	2	8	-	Line

Note:

Typical value are related to the setting of dot clock is 17MHz and frame rate is 60Hz, VDD=VDDI=2.8V..

In with ram mode, hpw+hbp+hfp≧66

In without ram mode, hpw+hbp≧60

8.9.4 RGB Interface Mode Selection

ST7789VW supports two kinds of RGB interface, DE mode and HV mode. Each mode also can select with ram and without ram. The table shown below uses command B1h to select RGB interface mode.

RCM[1:0]	WO	RGB Mode	Data Path
	0		Ram
10	1	DE mode	Shift register (without Ram)
	0		Ram
11	1	HV mode	Shift register (without Ram)

8.9.5 RGB Interface Timing

The timing chart of RGB interface DE mode is shown as follows.

Note: The setting of front porch and back porch in host must match that in IC as this mode.

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

The timing chart of RGB interface HV mode is shown as follows.

Figure 26 Timing chart of RGB interface HV mod

The following are the functions not available in RGB Input Interface mode.

Function	RGB Interface	I80 System Interface

VSYNC, HSYNC, and DOTCLK signals must be supplied during a display operation period.

In RGB interface mode, the panel controlling signals are generated from DOTCLK, not the internal clock generated from the internal oscillator.

In 6-bit RGB interface mode, each of RGB dots are transferred in synchronization with DOTCLK signals. In other words, one pixel data needs to take three DOTCLKs to transfer.

In 6-bit RGB interface mode, the cycles of VSYNC, HSYNC, ENABLE, DOTCLK signals must be set correctly so that the data transfer is completed in units of pixels.

When switching between the internal operation mode and the external display interface operation mode, follow the sequences below in setting instruction.

In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame.

In RGB interface mode, a RAM address is set in the address counter every frame on the falling edge of VSYNC.

8.10 VSYNC Interface

8.10.1 18-bit RGB Interface

The ST7789VW incorporates VSYNC interface, which enables motion pictures to be displayed with only the conventional system interface and the frame synchronization signal (VSYNC). This interface requires minimal changes from the conventional system to display motion pictures.In this interface the internal display operation is synchronized with VSYNC. Data for display is written to RAM via the system interface with higher speed than for internal display operation. This method enables tearing-free display of motion pictures with the conventional interface.

Figure 28 Operation through VSYNC Interface

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

Display operation can be achieved by using the internal clock generated by the internal oscillator and the VSYNC input. Because all the data for display is written to RAM, only the data to be rewritten is transferred. This method reduces the amount of data transferred during motion picture display operation.

Figure 29 Timing Diagram of VSYNC Interface

VSYNC interface requires taking the minimum speed for RAM writing via the system interface and the frequency of the internal clock into consideration. RAM writing should be performed with higher speed than the result obtained from the calculation shown below. The internal memory writing address counter is reset by VSYNC. So, insure interval time between VSYNC falling and DRAM data writing.

Note:

VSYNC period should always be constant. If not, some degradation of display such as flicker may occur in LCD system.
Display data don't need to be written for every VSYNC period. For example, any system is working under 60Hz frame rate and 30-fps motion picture condition. So being written display data for every other frame would be enough.

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

8.10.2 VSYNC Interface Mode

Figure 30 Operation for Leading Mode of VSYNC Interface

Figure 31 Operation for Lagging Mode of VSYNC Interface

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

Notes:

When RAM writing does not start immediately after the falling edge of VSYNC, the time between the falling edge of VSYNC and the RAM writing start timing must also be considered.
The minimum DRAM write speed must be satisfied and the frequency variation must be taken into consideration.
The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an

entire display.

When switching from the internal clock operation mode to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame.
The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to "0" to transfer display data.

8.11 Display Data RAM

8.11.1 Configuration

The display module has an integrated 240x320x18-bit graphic type static RAM. This 1382400-bit memory allows storing on-chip a 240xRGBx320 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory.

Figure 32 Display data RAM organization

8.11.2 Memory to display address mapping

Data control command
Source output

8.12 Address Control

The address counter sets the addresses of the display data RAM for writing and reading.

Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the "Write access" is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=239 (Efh) and Y=0 to Y=319 (13Fh). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address.

For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=239 (Efh), YE=319 (13Fh).

In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS).

For flexibility in handling a wide variety of display architectures, the commands "CASET, RASET and MADCTL", define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Section 8.12 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM.

Condition	Column Counter	Row Counter
	Return to	Return to
When RAMWR/RAMRD command is accepted	"Start Column (XS)"	"Start Row (YS)"
Complete Pixel Read / Write action	Increment by 1 Return to	No change
The Column counter value is larger than "End Column (XE)"	"Start Column (XS)"	Increment by 1
The Column counter value is larger than "End Column (XE)"	Return to	Return to
and the Row counter value is larger than "End Row (YE)"	"Start Column (XS)"	"Start Row (YS)"

Display Data	MADCTR			Image in the Host	Image in the Driver
Direction	Parameter			(MPU)	(DDRAM)
	MV	MX	MY
Normal	0	0	0
Y-Mirror	0	0	1
X-Mirror	0	1	0
X-Mirror Y-Mirror	0	1	1
X-Y Exchange	1	0	0
X-Y Exchange Y-Mirror	1	0	1
X-Y Exchange X-Mirror	1	1	0
X-Y Exchange X-Mirror Y-Mirror	1	1	1

8.13 Normal Display On or Partial Mode On, Vertical Scroll Off

In this mode, contents of the frame memory within an area where column address is 00h to 83h and row address is 00h to

83h is displayed.

To display a dot on leftmost top corner, store the dot data at (column address, row address) = (0,0).

Example1) Normal Display On

Example2) Partial Display On: PSL[15:0] = 0004h, PEL[15:0] = 013Ch, MADCTR (ML)=0

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8.14 Vertical Scroll Mode

8.14.1 Rolling scroll

There is just one types of vertical scrolling, which are determined by the commands "Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h).

Figure 34 Rolling Scroll Definition

When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) =320. In this case, 'rolling' scrolling is applied as shown below. All the memory contents will be used.

Example1) Panel size=240 x 320, TFA =3, VSA=315, BFA=2, SSA=4, MADCTR ML=0: Rolling Scroll

Example2) Panel size=132 x 132, TFA =2, VSA=315, BFA=3, SSA=4, MADCTR ML=1: Rolling Scroll

(TFA and BFA are exchanged)

8.14.2 Vertical Scroll Example

There are 2 types of vertical scrolling, which are determined by the commands "Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h).

Case 1: TFA + VSA + BFA<320

N/A. Do not set TFA + VSA + BFA<320. In that case, unexpected picture will be shown.

Case 2: TFA + VSA + BFA=320 (Rolling Scrolling)

Example1) When MADCTR parameter ML="0", TFA=0, VSA=320, BFA=0 and VSCSAD=40.

Example2) When MADCTR parameter ML="1", TFA=10, VSA=310, BFA=0 and VSCSAD=30.

8.15 Tearing Effect

The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images.

8.15.1 Tearing effect line modes

Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:

tvdh= The LCD display is not updated from the Frame Memory tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)

Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 320 H-sync pulses per field.

thdh= The LCD display is not updated from the Frame Memory

thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)

Note: During Sleep In Mode, the Tearing Output Pin is active Low.

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8.15.2 Tearign effect line timings

The Tearing Effect signal is described below:

Symbol	Parameter	min	max	unit	description

The signal's rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.

The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:

Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image:

ST7789VW

The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer "catches" the MPU to Frame memory write position.

8.16 Power ON/OFF Sequence

VDDI and VDD can be applied in any order.

VDD and VDDI can be power down in any order.

During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX has been released.

During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has been released.

CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.

Note 1: There will be no damage to the display module if the power sequences are not met.

Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.

Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence.

Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed.

The power on/off sequence is illustrated below

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8.16.1 Uncontrolled Power Off

The uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. It will neither damage the module or the host interface.

If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the display (blank display) and remains blank until "Power On Sequence" powers it up.

8.17 Power Level Definition

8.17.1 Power Level

6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption

Normal Mode On (full display), Idle Mode Off, Sleep Out.

In this mode, the display is able to show maximum 262,144 colors.

Partial Mode On, Idle Mode Off, Sleep Out.

In this mode part of the display is used with maximum 262,144 colors.

Normal Mode On (full display), Idle Mode On, Sleep Out.

In this mode, the full display area is used but with 8 colors.

Partial Mode On, Idle Mode On, Sleep Out.

In this mode, part of the display is used but with 8 colors.

Sleep In Mode

In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe.

Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.

ST7789VW

8.18 Power Flow Chart

8.19 Gamma Correction

ST7789VW incorporate the gamma correction function to display 262,244 colors for the LCD panel. The gamma correction is performed with 3 groups of registers, which are gradient adjustment, contrast adjustment and fine- adjustment registers for positive and negative polarities, and RGB can be adjusted individually.

Figure 35 Gray scale Voltage Generation (Positive)

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Figure 36 Relationship between Source Output and VCOM

Percentage adjustment:

J0P[1:0], J1P[1:0], J0N[1:0], J1N[1:0] these register are used to adjust the voltage level of interpolation point. The following table is the detail description.

J0P[1:0]/J0N[1:0]:

	00h	01h	02h	03h
VP3/VN3	50%	56%	50%	60%
VP5/VN5	50%	44%	50%	42%
VP7/VN7	86%	71%	80%	66%
VP8/VN8	71%	57%	63%	49%
VP9/VN9	57%	40%	49%	34%
VP10/VN10	43%	29%	34%	23%
VP11/VN11	29%	17%	20%	14%
VP12/VN12	14%	6%	9%	6%

J1P[1:0]/J1N[1:0]:

	00h	01h	02h	03h
VP51/VN51	86%	86%	86%	89%
VP52/VN52	71%	71%	77%	80%
VP53/VN53	57%	60%	63%	69%
VP54/VN54	43%	46%	46%	51%
VP55/VN55	29%	34%	31%	37%
VP56/VN56	14%	17%	14%	20%
VP58/VN58	50%	56%	47%	47%
VP60/VN60	50%	50%	50%	53%

Table 18 voltage level percentage adjustment description

Source voltage of positive gamma level

Gamma level	Related Register	Formula
VP0	V0P[3:0]	(VAP-VBP)*(129R-V0P[3:0]R)/129R+VBP
VP1	V1P[5:0]	(VAP-VBP)*(128R-V1P[5:0]R)/129R+VBP
VP2	V2P[5:0]	(VAP-VBP)*(128R-V2P[5:0]R)/129R+VBP
VP3	J0P[1:0]	(VP2-VP4)*J0P[1:0]+VP4
VP4	V4P[4:0]	(VP2-VP20)*(57R-V4P[4:0])/60R+VP20
VP5	J0P[1:0]	(VP4-VP6)*J0P[1:0]+VP6
VP6	V6P[4:0]	(VP2-VP20)*(47R-V6P[4:0])/60R+VP20
VP7	J0P[1:0]	(VP6-VP13)*J0P[1:0]+VP13
VP8	J0P[1:0]	(VP6-VP13)*J0P[1:0]+VP13
VP9	J0P[1:0]	(VP6-VP13)*J0P[1:0]+VP13
VP10	J0P[1:0]	(VP6-VP13)*J0P[1:0]+VP13
VP11	J0P[1:0]	(VP6-VP13)*J0P[1:0]+VP13
VP12	J0P[1:0]	(VP6-VP13)*J0P[1:0]+VP13
VP13	V13P[3:0]	(VP2-VP20)*(21R-V13P[3:0])/60R+VP20
VP14	--	(VP13-VP20)/(20-13)*(20-14)+VP20
VP15	--	(VP13-VP20)/(20-13)*(20-15)+VP20
VP16	--	(VP13-VP20)/(20-13)*(20-16)+VP20
VP17	--	(VP13-VP20)/(20-13)*(20-17)+VP20
VP18	--	(VP13-VP20)/(20-13)*(20-18)+VP20
VP19	--	(VP13-VP20)/(20-13)*(20-19)+VP20
VP20	V20P[6:0]	(VAP-VBP)*(128R-V20P[6:0]R)/129R+VBP
VP21	--	(VP20-VP27)/(27-20)*(27-21)+VP27
VP22	--	(VP20-VP27)/(27-20)*(27-22)+VP27
VP23	--	(VP20-VP27)/(27-20)*(27-23)+VP27
VP24	--	(VP20-VP27)/(27-20)*(27-24)+VP27
VP25	--	(VP20-VP27)/(27-20)*(27-25)+VP27
VP26	--	(VP20-VP27)/(27-20)*(27-26)+VP27
VP27	V27P[2:0]	(VP20-VP43)*(20R-V27P[2:0])/25R+VP43
VP28	--	(VP27-VP36)/(36-27)*(36-28)+VP36
VP29	--	(VP27-VP36)/(36-27)*(36-29)+VP36
VP30	--	(VP27-VP36)/(36-27)*(36-30)+VP36
VP31	--	(VP27-VP36)/(36-27)*(36-31)+VP36
VP32	--	(VP27-VP36)/(36-27)*(36-32)+VP36
VP33	--	(VP27-VP36)/(36-27)*(36-33)+VP36
VP34	--	(VP27-VP36)/(36-27)*(36-34)+VP36
VP35	--	(VP27-VP36)/(36-27)*(36-35)+VP36
VP36	V36P[2:0]	(VP20-VP43)*(11R-V36P[2:0])/25R+VP43
VP37	--	(VP36-VP43)/(43-36)*(43-37)+VP43
VP38	--	(VP36-VP43)/(43-36)*(43-38)+VP43
VP39	--	(VP36-VP43)/(43-36)*(43-39)+VP43
VP40	--	(VP36-VP43)/(43-36)*(43-40)+VP43
VP41	--	(VP36-VP43)/(43-36)*(43-41)+VP43
VP42	--	(VP36-VP43)/(43-36)*(43-42)+VP43
VP43	V43P[6:0]	(VAP-VBP)*(128R-V43P[6:0]R)/129R+VBP
VP44	--	(VP43-VP50)/(50-43)*(50-44)+VP50
VP45	--	(VP43-VP50)/(50-43)*(50-45)+VP50
VP46	--	(VP43-VP50)/(50-43)*(50-46)+VP50
VP47	--	(VP43-VP50)/(50-43)*(50-47)+VP50
VP48	--	(VP43-VP50)/(50-43)*(50-48)+VP50
VP49	--	(VP43-VP50)/(50-43)*(50-49)+VP50
VP50	V50P[3:0]	(VP43-VP61)*(54R-V50P[3:0])/60R+VP61
VP51	J1P[1:0]	(V5P0-VP57)*J1P[1:0]+VP57

VP52	J1P[1:0]	(VP50-VP57)*J1P[1:0]+VP57
VP53	J1P[1:0]	(VP50-VP57)*J1P[1:0]+VP57
VP54	J1P[1:0]	(VP50-VP57)*J1P[1:0]+VP57
VP55	J1P[1:0]	(VP50-VP57)*J1P[1:0]+VP57
VP56	J1P[1:0]	(VP50-VP57)*J1P[1:0]+VP57
VP57	V57P[4:0]	(VP43-VP61)*(44R-V57P[4:0])/60R+VP61
VP58	J1P[1:0]	(VP57-VP59)*J1P[1:0]+VP59
VP59	V59P[4:0]	(VP43-VP61)*(34R-V59P[4:0])/60R+VP61
VP60	J1P[1:0]	(VP59-VP61)*J1P[1:0]+VP61
VP61	V61P[5:0]	(VAP-VBP)*(64R-V61P[5:0]R)/129R+VBP
VP62	V62P[5:0]	(VAP-VBP)*(64R-V62P[5:0]R)/129R+VBP
VP63	V63P[3:0]	(VAP-VBP)*(23R-V63P[3:0]R)/129R+VBP

Source voltage of negative gamma level

Gamma level	Related Register	Formula
VN0	V0N[3:0]	VBN-(VBN-VAN)*(129R-V0N[3:0]R)/129R
VN1	V1N[5:0]	VBN-(VBN-VAN)*(128R-V1N[5:0]R)/129R
VN2	V2N[5:0]	VBN-(VBN-VAN)*(128R-V2N[5:0]R)/129R
VN3	J0N[1:0]	(VN2-VN4)*J0N[1:0]+VN4
VN4	V4N[4:0]	(VN2-VN20)*(57R-V4N[4:0])/60R+VN20
VN5	J0N[1:0]	(VN4-VN6)*J0N[1:0]+VN6
VN6	V6N[4:0]	(VN2-VN20)*(47R-V6N[4:0])/60R+VN20
VN7	J0N[1:0]	(VN6-VN13)*J0N[1:0]+VN13
VN8	J0N[1:0]	(VN6-VN13)*J0N[1:0]+VN13
VN9	J0N[1:0]	(VN6-VN13)*J0N[1:0]+VN13
VN10	J0N[1:0]	(VN6-VN13)*J0N[1:0]+VN13
VN11	J0N[1:0]	(VN6-VN13)*J0N[1:0]+VN13
VN12	J0N[1:0]	(VN6-VN13)*J0N[1:0]+VN13
VN13	V13N[3:0]	(VN2-VN20)*(21R-V13N[3:0])/60R+VN20
VN14	--	(VN13-VN20)/(20-13)*(20-14)+VN20
VN15	--	(VN13-VN20)/(20-13)*(20-15)+VN20
VN16	--	(VN13-VN20)/(20-13)*(20-16)+VN20
VN17	--	(VN13-VN20)/(20-13)*(20-17)+VN20
VN18	--	(VN13-VN20)/(20-13)*(20-18)+VN20
VN19	--	(VN13-VN20)/(20-13)*(20-19)+VN20
VN20	V20N[6:0]	VBN-(VBN-VAN)*(128R-V20N[6:0]R)/129R
VN21	--	(VN20-VN27)/(27-20)*(27-21)+VN27
VN22	--	(VN20-VN27)/(27-20)*(27-22)+VN27
VN23	--	(VN20-VN27)/(27-20)*(27-23)+VN27
VN24	--	(VN20-VN27)/(27-20)*(27-24)+VN27
VN25	--	(VN20-VN27)/(27-20)*(27-25)+VN27
VN26	--	(VN20-VN27)/(27-20)*(27-26)+VN27
VN27	V27N[2:0]	(VN20-VN43)*(20R-V27N[2:0])/25R+VN43
VN28	--	(VN27-VN36)/(36-27)*(36-28)+VN36
VN29	--	(VN27-VN36)/(36-27)*(36-29)+VN36
VN30	--	(VN27-VN36)/(36-27)*(36-30)+VN36
VN31	--	(VN27-VN36)/(36-27)*(36-31)+VN36
VN32	--	(VN27-VN36)/(36-27)*(36-32)+VN36
VN33	--	(VN27-VN36)/(36-27)*(36-33)+VN36
VN34	--	(VN27-VN36)/(36-27)*(36-34)+VN36
VN35	--	(VN27-VN36)/(36-27)*(36-35)+VN36
VN36	V36N[2:0]	(VN20-VN43)*(11R-V36N[2:0])/25R+VN43
VN37	--	(VN36-VN43)/(43-36)*(43-37)+VN43

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VN38	--	(VN36-VN43)/(43-36)*(43-38)+VN43
VN39	--	(VN36-VN43)/(43-36)*(43-39)+VN43
VN40	--	(VN36-VN43)/(43-36)*(43-40)+VN43
VN41	--	(VN36-VN43)/(43-36)*(43-41)+VN43
VN42	--	(VN36-VN43)/(43-36)*(43-42)+VN43
VN43	V43N[6:0]	VBN-(VBN-VAN)*(128R-V43N[6:0]R)/129R
VN44	--	(VN43-VN50)/(50-43)*(50-44)+VN50
VN45	--	(VN43-VN50)/(50-43)*(50-45)+VN50
VN46	--	(VN43-VN50)/(50-43)*(50-46)+VN50
VN47	--	(VN43-VN50)/(50-43)*(50-47)+VN50
VN48	--	(VN43-VN50)/(50-43)*(50-48)+VN50
VN49	--	(VN43-VN50)/(50-43)*(50-49)+VN50
VN50	V50N[3:0]	(VN43-VN61)*(54R-V50N[3:0])/60R+VN61
VN51	J1N[1:0]	(V5N0-VN57)*J1N[1:0]+VN57
VN52	J1N[1:0]	(VN50-VN57)*J1N[1:0]+VN57
VN53	J1N[1:0]	(VN50-VN57)*J1N[1:0]+VN57
VN54	J1N[1:0]	(VN50-VN57)*J1N[1:0]+VN57
VN55	J1N[1:0]	(VN50-VN57)*J1N[1:0]+VN57
VN56	J1N[1:0]	(VN50-VN57)*J1N[1:0]+VN57
VN57	V57N[4:0]	(VN43-VN61)*(44R-V57N[4:0])/60R+VN61
VN58	J1N[1:0]	(VN57-VN59)*J1N[1:0]+VN59
VN59	V59N[4:0]	(VN43-VN61)*(34R-V59N[4:0])/60R+VN61
VN60	J1N[1:0]	(VN59-VN61)*J1N[1:0]+VN61
VN61	V61N[5:0]	VBN-(VBN-VAN)*(64R-V61N[5:0]R)/129R
VN62	V62N[5:0]	VBN-(VBN-VAN)*(64R-V62N[5:0]R)/129R
VN63	V63N[3:0]	VBN-(VBN-VAN)*(23R-V63N[3:0]R)/129R

8.20 Gray voltage generator for digital gamma correction

ST7789VW digital gamma function can implement the RGB gamma correction independently. ST7789VW utilizes look-up table of digital gamma to change ram data, and then display the changed data from source driver. The following diagram shows the data flow of digital gamma.

Figure 37 Block diagram of digital gamma

There are 2 registers and each register has 64 bytes to set R, G, B gamma independently. When bit DGMEN be set to 1, R and B gamma will be mapped via look-up table of digital gamma to gray level voltage.

8.21 Display Dimming

8.21.1 General Description

A dimming function (how fast to change the brightness from old to new level and what are brightness levels during the change) is used when changing from one brightness level to another. This dimming function curve is the same in increment and decrement. The basic idea is described below.

Dimming function can be enable and disable. See "Write CTRL Display (53h)" (bit DD) for more information.

8.21.2 Dimming Requirement

Dimming function in the display module should be implemented so that 400-600ms is used for the transition between the original brightness value and the target brightness value. The transferring time steps between these two brightness values are equal making the transition linear.

The dimming function is working similarly in both upward and downward directions.

An upward example is illustrate below

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

8.21.3 Definition of brightness transition time

Shorter transition time than 500ms.

There is some stable time between transitions. Below drawing is for transition time: 400ms.

Longer transition time than 500ms There is no any stable time between transitions. Below drawing is for transition time: 600ms.

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

8.22 Content Adaptive Brightness Control (CABC)

8.22.1 Definition of CABC

A Content Adaptive Brightness Control function can be used to reduce the power consumption of the luminance source. Content adaptation means that content gray level scale can be increased while simultaneously lowering brightness of the backlight to achieve same perceived brightness. The adjusted gray level scale and thus the power consumption reduction

Definition of Modes and target power reduction ratio:

Off mode: Content Adaptive Brightness Control functionality is totally off.
UI [User interface] image mode: Optimized for UI image. It is kept image quality as much as possible. Target power consumption reduction ratio: 10% or less.
Still picture mode: Optimized for still picture. Some image quality degradation would be acceptable. Target power consumption reduction ratio: more than 30%.
Moving image mode: Optimized for moving image. It is focused on the biggest power reduction with image quality degradation. Target power consumption reduction ratio: more than 30%.

Note 1: Updating partial area of the image data should be supported by CABC functionality. Note 2: Processing power consumption of CABC should be minimized. Note 3: Customer need program OTP GAMMA when using CABC.

The transition time for dimming function is illustrated below.

Content Adaptive Brightness Control

Display brightness is changed, according to the image contents. The following graph mentions the case of displaying three different images.

Image A: -20% brightness reduction
Image B: -30% brightness reduction
Image C: -30% brightness reduction

Transition time from the previous image to the current displayed image is "transition time A".

Manual brightness setting and Dimming function

Combine Display brightness

Green line in the following graph is for the output brightness of display. It is combined with both display brightness, which are defined in the above graphs.

Maximum transition time is transition time A+B. Display brightness

Brightness level calculates with the following formula.

Case 1
Case 2
Case 3

Transition time from the current brightness to target brightness is A+B in the worst case.

8.22.2 Minimum brightness setting of CABC function

CABC function is automatically reduced backlight brightness based on image contents. In the case of the combination with the LABC or manual brightness setting, display brightness is too dark. It must affect to image quality degradation. CABC minimum brightness setting is to avoid too much brightness reduction. When CABC is active, CABC can not reduce the display brightness to less than CABC minimum brightness setting. If CABC algorithm works without any abnormal visual effect, image processing function can operate even when the brightness can not be changed.

This function does not affect to the other function, manual brightness setting. Manual brightness can be set the display brightness to less than CABC minimum brightness. Smooth transition and dimming function can be worked as normal.

When display brightness is turned off (BCTRL=0 of "9.1.39 Write CTRL Display (53h)"), CABC minimum brightness setting is ignored. "9.1.44 Read CABC minimum brightness (5Fh)" always read the setting value of "9.1.43 Write CABC minimum brightness (5Eh)".

	WRCABC (55h)	Function	RDCABCMB (5Fh)	Image

Brightness level calculates with the following formula.

Display Output Brightness = Manual brightness setting * CABC brightness ratio

Below drawing is for the explanation of the CABC minimum brightness setting.

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

CABC minimum brightness value = 51 (33h: 20% display brightness)

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

9 COMMAND

9.1 System Function Command Table 1

Instruction		D/CX WRX RDX		D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
NOP	0	↑	1	-	0	0	0	0	0	0	0	0	(00h)	No operation
SWRESET	0	↑	1	-	0	0	0	0	0	0	0	1	(01h)	Software reset
	0	↑	1	-	0	0	0	0	0	1	0	0	(04h)	Read display ID
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
RDDID	1	1	↑	-	ID17	ID16	ID15	ID14	ID13	ID12	ID11	ID10		ID1 read
	1	1	↑	-	ID27	ID26	ID25	ID24	ID23	ID22	ID21	ID20		ID2 read
	1	1	↑	-	ID37	ID36	ID35	ID34	ID33	ID32	ID31	ID30		ID3 read
	0	↑	1	-	0	0	0	0	1	0	0	1	(09h)	Read display status
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
RDDST	1	1	↑	-	BSTON	MY	MX	MV	ML	RGB	MH	ST24		-
	1	1	↑	-	ST23	IFPF2	IFPF1	IFPF0	IDMON			PTLON SLOUT NORON		-
	1	1	↑	-	ST15	ST14	INVON	ST12	ST11	DISON	TEON	GCS2		-
	1	1	↑	-	GCS1	GCS0	TEM	ST4	ST3	ST2	ST1	ST0		-
	0	↑	1	-	0	0	0	0	1	0	1	0	(0Ah)	Read display power
RDDPM	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	BSTON	IDMON		PTLON SLPOUT NORON DISON			0	0
	0	↑	1	-	0	0	0	0	1	0	1	1	(0Bh)	Read display
RDD	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
MADCTL	1	1	↑	-	MY	MX	MV	ML	RGB	MH	0	0		-
RDD	0	↑	1	-	0	0	0	0	1	1	0	0	(0Ch)	Read display pixel
COLMOD	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	0	D6	D5	D4	0	D2	D1	D0		-
RDDIM	0	↑	1	-	0	0	0	0	1	1	0	1	(0Dh)	Read display image
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	VSSON	0	INVON	0	0	GC2	GC1	GC0		-
RDDSM	0	↑	1	-	0	0	0	0	1	1	1	0	(0Eh)	Read display signal
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read

Instruction		D/CX WRX RDX		D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
	1	1	↑	-	TEON	TEM	0	0	0	0	0	0		- Read display
	0	↑	1	-	0	0	0	0	1	1	1	1	(0Fh)	self-diagnostic
RDDSDR														result
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	D7	D6	0	0	0	0	0	0		-
SLPIN	0	↑	1	-	0	0	0	1	0	0	0	0	(10h)	Sleep in
SLPOUT	0	↑	1	-	0	0	0	1	0	0	0	1	(11h)	Sleep out
PTLON	0	↑	1	-	0	0	0	1	0	0	1	0	(12h)	Partial mode on
NORON	0	↑	1	-	0	0	0	1	0	0	1	1	(13h)	Partial off (Normal)
INVOFF	0	↑	1	-	0	0	1	0	0	0	0	0	(20h)	Display inversion off
INVON	0	↑	1	-	0	0	1	0	0	0	0	1	(21h)	Display inversion on
GAMSET	0	↑	1	-	0	0	1	0	0	0	0	1	(26h)	Display inversion
	1	↑	1	-	0	0	0	0	GC3	GC2	GC1	GC0		on
DISPOFF	0	↑	1	-	0	0	1	0	1	0	0	0	(28h)	Display off
DISPON	0	↑	1	-	0	0	1	0	1	0	0	1	(29h)	Display on
	0	↑	1	-	0	0	1	0	1	0	1	0	(2Ah)	Column address set
CASET	1	↑	1	-	XS15	XS14	XS13	XS12	XS11	XS10	XS9	XS8		X address start:
	1	↑	1		XS7	XS6	XS5	XS4	XS3	XS2	XS1	XS0		0 X ≦ ≦ XS
	1	↑	1		XE15	XE14	XE13	XE12	XE11	XE10	XE9	XE8		X address start:
	1	↑	1		XE7	XE6	XE5	XE4	XE3	XE2	XE1	XE0		S X ≦ ≦ XE
	0	↑	1	-	0	0	1	0	1	0	1	1	(2Bh)	Row address set
	1	↑	1	-	YS15	YS14	YS13	YS12	YS11	YS10	YS9	YS8		Y address start:
RASET	1	↑	1		YS7	YS6	YS5	YS4	YS3	YS2	YS1	YS0		0 Y ≦ ≦ YS
	1	↑	1		YE15	YE14	YE13	YE12	YE11	YE10	YE9	YE8		Y address start:
	1	↑	1		YE7	YE6	YE5	YE4	YE3	YE2	YE1	YE0		S Y ≦ ≦ YE
	0	↑	1	-	0	0	1	0	1	1	0	0	(2Ch)	Memory write
	1	↑	1	D1[17:8]	D1[7]	D1[6]	D1[5]	D1[4]	D1[3]	D1[2]	D1[1]	D1[0]
RAMWR	1	↑	1	Dx[17:8]	Dx[7]	Dx[6]	Dx[5]	Dx[4]	Dx[3]	Dx[2]	Dx[1]	Dx[0]		Write data
	1	↑	1	Dn[17:8]	Dn[7]	Dn[6]	Dn[5]	Dn[4]	Dn[3]	Dn[2]	Dn[1]	Dn[0]
RAMRD	0	↑	1	-	0	0	1	0	1	1	1	0	(2Eh)	Memory read

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Instruction		D/CX WRX RDX		D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	D1[17:8]	D1[7]	D1[6]	D1[5]	D1[4]	D1[3]	D1[2]	D1[1]	D1[0]
	1	1	↑	Dx[17:8]	Dx[7]	Dx[6]	Dx[5]	Dx[4]	Dx[3]	Dx[2]	Dx[1]	Dx[0]		Read data
	1	1	↑	Dn[17:8]	Dn[7]	Dn[6]	Dn[5]	Dn[4]	Dn[3]	Dn[2]	Dn[1]	Dn[0]
	0	↑	1	-	0	0	1	1	0	0	0	0	(30h)	Partial sart/end address set
	1	↑	1	-	PSL15	PSL14	PSL13	PSL12	PSL11	PSL10	PSL9	PSL8		Partial start
PTLAR	1	↑	1	-	PSL7	PSL6	PSL5	PSL4	PSL3	PSL2	PSL1	PSL0		address: (0, 1,2, P)
	1	↑	1	-	PEL15	PEL14	PEL13	PEL12	PEL11	PEL10	PEL9	PEL8		Partial end
	1	↑	1	-	PEL7	PEL6	PEL5	PEL4	PEL3	PEL2	PEL1	PEL0		address (0, 1,2, 3, , P)
	0	↑	1	-	0	0	1	1	0	0	1	1	(33h)	Vertical scrolling definition
	1	↑	1	-	TFA15	TFA14	TFA13	TFA12	TFA11	TFA10	TFA9	TFA8
VSCRDEF	1	↑	1	-	TFA7	TFA6	TFA5	TFA4	TFA3	TFA2	TFA1	TFA0
	1	↑	1	-	VSA15	VSA14	VSA13	VSA12	VSA11	VSA10	VSA9	VSA8
	1	↑	1	-	VSA7	VSA6	VSA5	VSA4	VSA3	VSA2	VSA1	VSA0
	1	↑	1	-	BFA15	BFA14	BFA13	BFA12	BFA11	BFA10	BFA9	BFA8
	1	↑	1	-	BFA7	BFA6	BFA5	BFA4	BFA3	BFA2	BFA1	BFA0		Tearing effect
TEOFF	0	↑	1	-	0	0	1	1	0	1	0	0	(34h)	line off Tearing effect
TEON	0	↑	1	-	0	0	1	1	0	1	0	1	(35h)	line on
	1	↑	1	-	-	-	-	-	-	-	-	TEM		Memory data
MADCTL	0	↑	1	-	0	0	1	1	0	1	1	0	(36h)	access control
	1	↑	1	-	MY	MX	MV	ML	RGB	0	0	0		- Vertical scrolling
	0	↑	1	-	0	0	1	1	0	1	1	1	(37h)	start address
VSCRSADD	1	↑	1	-	VSP15	VSP14	VSP13	VSP12	VSP11	VSP10	VSP9	VSP8
	1	↑	1	-	VSP7	VSP6	VSP5	VSP4	VSP3	VSP2	VSP1	VSP0
IDMOFF	0	↑	1	-	0	0	1	1	1	0	0	0	(38h)	Idle mode off
IDMON	0	↑	1	-	0	0	1	1	1	0	0	1	(39h)	Idle mode on

Instruction		D/CX WRX RDX		D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
COLMOD	0	↑	1	-	0	0	1	1	1	0	1	0	(3Ah)	Interface pixel format
	1	↑	1	-	0	D6	D5	D4	0	D2	D1	D0		Interface format
	0	↑	1	-	0	0	1	1	1	1	0	0	(3Ch)	Memory write continue
RAMWRC	1	↑	1	D1[17:8]	D1[7]	D1[6]	D1[5]	D1[4]	D1[3]	D1[2]	D1[1]	D1[0]
	1	↑	1	Dx[17:8]	Dx[7]	Dx[6]	Dx[5]	Dx[4]	Dx[3]	Dx[2]	Dx[1]	Dx[0]		Write data
	1	↑	1	Dn[17:8]	Dn[7]	Dn[6]	Dn[5]	Dn[4]	Dn[3]	Dn[2]	Dn[1]	Dn[0]
	0	↑	1	-	0	0	1	1	1	1	1	0	(3Eh)	Memory read continue
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy Read
RAMRDC	1	1	↑	D1[17:8]	D1[7]	D1[6]	D1[5]	D1[4]	D1[3]	D1[2]	D1[1]	D1[0]
	1	1	↑	Dx[17:8]	Dx[7]	Dx[6]	Dx[5]	Dx[4]	Dx[3]	Dx[2]	Dx[1]	Dx[0]
	1	1	↑	Dn[17:8]	Dn[7]	Dn[6]	Dn[5]	Dn[4]	Dn[3]	Dn[2]	Dn[1]	Dn[0]
	0	↑	1	-	0	1	0	0	0	1	0	0	(44h)	Set tear scanline
TESCAN	1	↑	1	-	N15	N14	N13	N12	N11	N10	N9	N8
	1	↑	1	-	N7	N6	N5	N4	N3	N2	N1	N0
	0	↑	1	-	0	1	0	0	0	1	0	1	(45h)	Get scanline
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy Read
RDTESCAN	1	1	↑	-	-	-	-	-	-	-	N9	N8
	1	1	↑	-	N7	N6	N5	N4	N3	N2	N1	N0
	0	↑	1	-	0	1	0	1	0	0	0	1	(51h)	Write display
WRDISBV	1	↑	1	-	DBV7	DBV6	DBV5	DBV4	DBV3	DBV2	DBV1	DBV0		brightness
	0	↑	1	-	0	1	0	1	0	0	1	0	(52h)	Read display brightness value
RDDISBV	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	DBV7	DBV6	DBV5	DBV4	DBV3	DBV2	DBV1	DBV0
WRCTRLD	0	↑	1	-	0	1	0	1	0	0	1	1	(53h)	Write CTRL display
	1	↑	1	-	0	0	BCTRL	0	DD	BL	0	0
RDCTRLD	0	↑	1	-	0	1	0	1	0	1	0	0	(54h)	Read CTRL value dsiplay
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	0	0	BCTRL	0	DD	BL	0	0

Instruction		D/CX WRX RDX		D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
WRCACE	0	↑	1	-	0	1	0	1	0	1	0	1	(55h)	Write content adaptive brightness control and Color enhancemnet
	1	↑	1	-	CECTRL	0	CE1	CE0	0	0	C1	C0
RDCABC	0	↑	1	-	0	1	0	1	0	1	1	0	(56h)	Read content adaptive brightness control
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	0	CECTRL	0	0	0	0	C1	C0
WRCABCMB	0	↑	1	-	0	1	0	1	1	1	1	0	(5Eh)	Write CABC minimum brightness
	1	↑	1	-	CMB7	CMB6	CMB5	CMB4	CMB3	CMB2	CMB1	CMB0
RDCABCMB	0	↑	1	-	0	1	0	1	1	1	1	1	(5Fh)	Read CABC minimum brightness
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	CMB7	CMB6	CMB5	CMB4	CMB3	CMB2	CMB1	CMB0
RDABCSDR	0	↑	1	-	0	1	1	0	1	0	0	0	(68h)	Read Automatic Brightness Control Self-Diagnostic Result
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	D7	D6	0	0	0	0	0	0		-
	0	↑	1	-	1	1	0	1	1	0	1	0	(DAh)	Read ID1
RDID1	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	ID17	ID16	ID15	ID14	ID13	ID12	ID11	ID10		Read parameter
	0	↑	1	-	1	1	0	1	1	0	1	1	(DBh)	Read ID2
RDID2	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑	-	ID27	ID26	ID25	ID24	ID23	ID22	ID21	ID20		Read parameter
RDID3	0	↑	1	-	1	1	0	1	1	1	0	0	(DCh)	Read ID3

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Instruction		D/CX WRX RDX		D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
	1	1	↑	-	-	-	-	-	-	-	-	-		Dummy read
	1	1	↑		ID37	ID36	ID35	ID34	ID33	ID32	ID31	ID30		Read parameter

Table 19 System Function Command List

"-": Don't care

9.1.1 NOP (00h)

00H							NOP (No Operation)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5
NOP	0	↑	1	-	0	0	0
Parameter	No Parameter	-
Description	This command is empty command.
Restriction
Register Availability			Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out		Status Sleep In
Default				Status Power On Sequence S/W Reset H/W Reset
Flow Chart

9.1.2 SWRESET (01h): Software Reset

Inst / Para
SWRESET
Parameter
Description
Restriction
Default

9.1.3 RDDID (04h): Read Display ID

04H							RDDID (Read Display ID)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5
RDDID	0	↑	1	-	0	0	0
st parameter 1	1	1	↑	-	-	-	-
nd parameter 2	1	1	↑	-	ID17	ID16	ID15
rd parameter 3	1	1	↑	-	ID27	ID26	ID25
th parameter 4	1	1	↑	-	ID37	ID36	ID35
Description		-This read byte returns 24-bit display identification information. -The 1st parameter is dummy data -The 2nd parameter (ID17 to ID10): LCD module's manufacturer ID. -The 3rd parameter (ID26 to ID20): LCD module/driver version ID -The 4th parameter (ID37 to UD30): LCD module/driver ID. -Commands RDID1/2/3(Dah, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively. "-" Don't care
Restriction
Register availability		Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes
Default				Status Power On Sequence S/W Reset H/W Reset

9.1.4 RDDST (09h): Read Display Status

09H		RDDST (Read Display Status)
Inst / Para	D/CX	WRX
RDDST	0	↑
1st parameter	1	1
2nd parameter	1	1
3rd parameter	1	1
4th parameter	1	1
5th parameter	1	1
Description	Bit
	BSTON
	MY
	MX
	MV
Scan Address Order (ML)	ML
	RGB
	MH
	ST24
	ST23
	IFPF2
	IFPF1
	IFPF0
	IDMON
Partial Mode On/Off	PTLON

	SLPOUT	Sleep In/Out	'1' = Out, "0" = In
	NORON		'1' = Normal Display,
		Display Normal Mode On/Off	'0' = Partial Display
	ST15	Vertical Scrolling Status (Not Used)
	ST14	Horizontal Scroll Status (Not Used)	'0'
	INVON	Inversion Status	'1' = On, "0" = Off
	ST12	All Pixels On (Not Used)	'0'
	ST11	All Pixels Off (Not Used)	'0'
	DISON	Display On/Off	'1' = On, "0" = Off
	TEON	Tearing effect line on/off	'1' = On, "0" = Off
	GCSEL2		"000" = GC0
	GCSEL1		"001" = GC1
		Gamma Curve Selection	"010" = GC2
	GCSEL0		"011" = GC3
	TEM	Tearing effect line mode	'0' = mode1, '1' = mode2
	ST4	For Future Use	'0'
	ST3	For Future Use	'0'
	ST2	For Future Use	'0'
	ST1	For Future Use	'0'
	ST0 "-" Don't care	For Future Use	'0'
Restriction
		Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out
Register		Partial Mode On, Idle Mode Off, Sleep Out
availability		Partial Mode On, Idle Mode On, Sleep Out
		Sleep In	Yes
	Status		Default Value (ST31 to ST0)
			ST[31-24]
Default		Power On Sequence	0000-0000
	S/W Reset		0xxx-xx00
	H/W Reset		0000-0000

	RDDPM (Read Display Power Mode)
0AH
Inst / Para	D/CX
RDDPM	0
st parameter 1	1
nd parameter 2	1

	Bit
	BSTON

	IDMON

	PTLON

Description	SLPOUT

	NORON

	DISON Display on/off

	D1
	D0
	"-" Don't care
Restriction


Register
availability

9.1.5 RDDPM (0Ah): Read Display Power Mode

0BH		RDDMADCTL (Read Display MADCTL)
Inst / Para	D/CX	WRX
RDDMADCTL	0	↑
st parameter 1	1	1
nd parameter 2	1	1
	Bit
	MY
	MX
	MV
	ML
Description
	RGB
	MH
	D1
	D0 "-" Don't care
Restriction


Register
availability

9.1.6 RDDMADCTL (0Bh): Read Display MADCTL

	Status	Default Value (D7 to D0)
Default	Power On Sequence	0000-0000 (00h)
	S/W Reset	No change
	H/W Reset	0000-0000 (00h)
Flow Chart

0CH	RDDCOLMOD (Read Display Pixel Format)
Inst / Para	D/CX
RDDCOLMOD	0
st parameter 1	1
nd parameter 2	1



	D6 '101' = 16 bit/pixel

Description	'110' = 18 bit/pixel D4





	"-" Don't care
Restriction


Register
availability



Default

	H/W Reset 0000-0110 (18 bit/pixel)

9.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format

0DH	RDDIM (Read Display Image Mode)
Inst / Para	D/CX
RDDIM	0
st parameter 1	1
nd parameter 2	1
Description
	"-" Don't care
Restriction
Register availability	Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default	Status Power On Sequence S/W Reset

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0EH	RDDSM (Read Display Signal Status)
Inst / Para	D/CX
RDDSM	0
st parameter 1	1
nd parameter 2	1
	This command indicates the current status of the display as described in the table below:
Description





Restriction
	Status Availability

Register
availability



Default

9.1.9 RDDSM (0Eh): Read Display Signal Mode

09H			RDDSDR (Read Display Self-Diagnostic Result) RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 ↑ 1 - 0 0 0 0 1 1 1 1 1 ↑ - - - - - - - - - - 1 ↑ - D7 D6 0 0 0 0 0 0 - Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes
Inst / Para	D/CX	WRX
RDDSDR	0
st parameter 1	1
nd parameter 2	1
Description	This command indicates the current status of the display self-diagnostic result after sleep out command as described below: -D7: Register loading detection -D6: Functionality detection "-" Don't care
Restriction
Register availability
Default			Status Power On Sequence S/W Reset H/W Reset

9.1.10 RDDSDR (0Fh): Read Display Self-Diagnostic Result

9.1.11 SLPIN (10h): Sleep in

10H		SLPIN (Sleep In)
Inst / Para	D/CX	WRX
SLPIN	0	↑
parameter	-This command causes the LCD module to enter the minimum power consumption mode.	No Parameter
Description	-In this mode the DC/DC converter is stopped, internal oscillator is stopped, and panel scanning is stopped. "-" Don't care	-This command has no effect when module is already in sleep in mode. Sleep in mode can only be left by the sleep out command (11h).
Restriction	-It will be necessary to wait 5msec before sending any new commands to a display module following this command to allow time for the supply voltages and clock circuits to stabilize. -It will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sending an sleep in command.
		Status

Register availability



		Status
Default

9.1.12 SLPOUT (11h): Sleep Out

11H			SLPOUT (Sleep Out)
Inst / Para	D/CX	WRX	RDX
SLPOUT	0	↑	1
parameter		No Parameter
Description			-This command turn off sleep mode.
Restriction	-This command has no effect when module is already in sleep out mode. Sleep out mode can only be left by the sleep in command (10h). -It will be necessary to wait 5msec before sending any new commands to a display module following this command to allow time for the supply voltages and clock circuits to stabilize. -It will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sending an sleep in command. -The display module runs the self-diagnostic functions after this command is received.
Register availability		Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes
Default			Status Power On Sequence S/W Reset H/W Reset

12H		PTLON (Partial Display Mode On) WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 ↑ 1 - 0 0 0 1 0 0 1 0 No Parameter "-" Don't care Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes
Inst / Para	D/CX
PTLON	0
parameter		-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h)
Description	-To leave Partial mode, the Normal Display Mode On command (13h) should be written.
Restriction		This command has no effect when partial mode is active.
Register
availability




Default


Flow Chart		See Partial Area (30h)

9.1.13 PTLON (12h): Partial Display Mode On

9.1.14 NORON (13h): Normal Display Mode On

20H	INVOFF (Display Inversion Off)									D0 HEX 0 (20h)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5	D4	D3	D2
INVOFF	0	↑	1	-	0	0	1	0	0	0
parameter	No Parameter -This command is used to recover from display inversion mode. "-" Don't care (Example)
Description	Memory Display Top-Lef t (0,0)
Restriction	This command has no effect when module is already in inversion off mode.
Register availability	Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes				Sleep In			Default Value		Yes
Default								Display inversion off
Partial Mode On, Idle Mode On, Sleep Out Status Power On Sequence S/W Reset H/W Reset		Display inversion off			Display inversion off					Yes

9.1.15 INVOFF (20h): Display Inversion Off

21H								INVON (Display Inversion On)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5	D4
INVON	0	↑	1	-	0	0	1	0
parameter	No Parameter -This command is used to recover from display inversion mode. "-" Don't care (Example) Memory Display
Description	Top-Left (0,0)
Restriction	This command has no effect when module is already in inversion on mode.		Normal Mode On, Idle Mode Off, Sleep Out		Status		Availability
Register			Normal Mode On, Idle Mode On, Sleep Out
availability			Partial Mode On, Idle Mode Off, Sleep Out Status		Sleep In	Partial Mode On, Idle Mode On, Sleep Out Yes		Default Value
Default			Power On Sequence S/W Reset H/W Reset					Display inversion off Display inversion off Display inversion off

9.1.16 INVON (21h): Display Inversion On

9.1.17 GAMSET (26h): Gamma Set

26H		GAMSET (Gamma Set)
Inst / Para	D/CX	WRX
GAMSET	0	↑
parameter	1 -This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table.	↑
		GC [7:0]
1. Description	01h
		02h
		04h
	08h Note: All other values are undefined.
Restriction	Values of GC[7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid value is received. Status Availability

Register availability



		Status
Default		Power On Sequence
		S/W Reset

9.1.18 DISPOFF (28h): Display Off

28H	DISPOFF (Display Off)
Inst / Para	D/CX
DISPOFF	0
parameter	No Parameter
	- This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and blank page inserted. - This command makes no change of contents of frame memory. - This command does not change any other status. - There will be no abnormal visible effect on the display. - Exit from this command by Display On (29h) (Example) Memory Display
Description
Restriction
Register availability
Default	Status Default Value Power On Sequence Display off S/W Reset Display off H/W Reset Display off

9.1.19 DISPON (29h): Display On

29H		DISPON (Display On)
Inst / Para	D/CX	WRX
DISPON	0	↑
parameter	No Parameter - This command is used to recover from DISPLAY OFF mode. - Output from the Frame Memory is enabled. - This command makes no change of contents of frame memory. - This command does not change any other status.
Description	(Example)

Restriction	This command has no effect when module is already in display on mode.
Register availability
Default	Status Default Value Power On Sequence Display off S/W Reset Display off H/W Reset Display off

9.1.20 CASET (2Ah): Column Address Set

2AH	CASET (Column Address Set)
Inst / Para
CASET	0
st parameter 1	1
nd parameter 2	1
rd parameter 3	1
th parameter 4	1
2. Description	-The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes. -Each value represents one column line in the Frame Memory. XS[7:0] XE[7:0]
Restriction	XS [15:0] always must be equal to or less than XE [15:0] When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored. (Parameter range: 0 < XS [15:0] < XE [15:0] < 239 (00Efh)): MV="0") (Parameter range: 0 < XS [15:0] < XE [15:0] < 319 (013Fh)): MV="1")
Register availability
Default	Status Default Value Power On Sequence XS[15:0]=0x00 XS[15:0]=0x00 S/W Reset H/W Reset XS[15:0]=0x00

9.1.21 RASET (2Bh): Row Address Set

2BH		RASET (Row Address Set)
Inst / Para
RASET	0	↑
st parameter 1	1	↑
nd parameter 2	1	↑
rd parameter 3	1	↑
th parameter 4	1	↑
3. Description	-This command is used to defined area of frame memory where MCU can access. -The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes. -Each value represents one page line in the Frame Memory. YS[15:0] YE[15:0]
Restriction	YS [15:0] always must be equal to or less than YE [15:0] When YS [15:0] or YE [15:0] is greater than maximum address like below, data of out of range will be ignored. (Parameter range: 0 < YS [15:0] < YE [15:0] < 319 (013fh)): MV="0") (Parameter range: 0 < YS [15:0] < YE [15:0] < 239 (00EFh)): MV="1")


Register availability



		Status

Default	H/W Reset YS[15:0]=0000h YE[15:0]=013Fh

9.1.22 RAMWR (2Ch): Memory Write

2CH	RAMWR (Memory Write)
Inst / Para	D/CX
RAMWR	0
st parameter 1	1
…	1
N parameter	1
Description	-This command is used to transfer data from MCU to frame memory. -When this command is accepted, the column register and the page register are reset to the start column/start page positions. -The start column/start page positions are different in accordance with MADCTL setting. -Sending any other command can stop frame write.
Restriction
Register availability
Default

9.1.23 RAMRD (2Eh): Memory Read

2EH	RAMRD (Memory Read)
Inst / Para	D/CX
RAMRD	0
st parameter 1	1
nd parameter 2	1
	1 1 ↑
(N+1)th parameter	1
Description	-This command is used to transfer data from frame memory to MCU. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTL setting. -Then D[17:0] is read back from the frame memory and the column register and the row register incremented -Frame Read can be cancelled by sending any other command. -The data color coding is fixed to 18-bit in reading function. Please see section 9.8 "Data color coding" for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data. Note1: The Command 3Ah should be set to 66h when reading pixel data from frame memory.
Restriction
Register availability	Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default	Status Default Value Power On Sequence Contents of memory is set randomly S/W Reset Contents of memory is not cleared H/W Reset Contents of memory is not cleared

9.1.24 PTLAR (30h): Partial Area

-If End Row > Start Row, when MADCTL ML='0'
Start row
Non-display area
PSL [15:0]
Description
Partial display area
PEL [15:0]
Non-display area
End row
-If End Row < Start Row, when MADCTL ML='0'
End row
Partial display area
PEL [15:0]
Non-display
area
PSL [15:0]
Start row
Partial display area

Version 1.0 Page 206 of 317 2017/09

	-If End Row = Start Row then the Partial Area will be one row deep.
Restriction
Register availability	Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default	Status Power On Sequence S/W Reset H/W Reset
Flow Chart

9.1.25 VSCRDEF (33h): Vertical Scrolling Definition

33H	(Vertical Scrolling Definition)
Inst / Para	D/CX
VSCRDEF	0
st 1	1
parameter
nd 2	1
parameter
rd 3	1
parameter
th 4	1
parameter
th 5	1
parameter
th 6	1
parameter
	-This command just defines the Vertical Scrolling Area of the display and not performs vertical scroll -When MADCTL MV=0





	Display).

Description
Restriction	The condition is TFA+VSA+BFA = 320, otherwise Scrolling mode is undefined.

Register
availability
Default

34H		TEOFF (Tearing Effect Line OFF)
Inst / Para	D/CX	WRX
TEOFF	0	↑
parameter	No Parameter
Description	-This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Restriction	This command has no effect when tearing effect output is already off
Register availability		Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default	Status Power On Sequence S/W Reset H/W Reset

9.1.26 TEOFF (34h): Tearing Effect Line OFF

9.1.27 TEON (35h): Tearing Effect Line On

35H	TEON (Tearing Effect Line On)
Inst / Para	D/CX
TEON	0
parameter	1
Description	-This command is used to turn ON the Tearing Effect output signal from the TE signal line. -This output is not affected by changing MADCTL bit ML. -The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line: -When TEM ='0': The Tearing Effect output line consists of V-Blanking information only Tvdl Tvdh Vertical time scale -When TEM ='1': The Tearing Effect output Line consists of both V-Blanking and H-Blanking information Tvdl Tvdh Vertical time scale
Restriction
Register availability
Default

36H		MADCTL (Memory Data Access Control)
Inst / Para	D/CX	WRX
MADCTL	0	↑
parameter	1 -This command defines read/ write scanning direction of frame memory.	↑

		Bit D7
		D6
		D5
		D4
		D3
	"0" = Left to Right (When MADCTL D6="0"). "1" = Right to Left (When MADCTL D6="1").	D2 Display Data Latch Order -Bit Assignment Bit D7- Page Address Order "1" = Bottom to Top (When MADCTL D7="1").
Description	Bit D5- Page/Column Order "0" = Normal Mode (When MADCTL D5="0"). "1" = Reverse Mode (When MADCTL D5="1") Note: Bits D7 to D5, alse refer to section 8.12 Address Control Bit D4- Line Address Order "0" = LCD Refresh Top to Bottom (When MADCTL D4="0") "1" = LCD Refresh Bottom to Top (When MADCTL D4="1")	Bit D3- RGB/BGR Order "0" = LCD Refresh Left to Right (When MADCTL D2="0") "1" = LCD Refresh Right to Left (When MADCTL D2="1")

9.1.28 MADCTL (36h): Memory Data Access Control

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availability			Availability
			Yes Yes Yes Yes Yes
	Status	Default Value
Default	Power On Sequence	0000h
	S/W Reset	No change
	H/W Reset	Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 0000h Legend Command MADCTL Parameter Display Action 1st parameter B[7:0] Mode Sequential transter
Flow Chart

37H								VSCSAD (Vertical Scroll Start Address of RAM)
Inst / Para				D/CX WRX RDX D17-8	D7	D6	D5	D4
VSCSAD	0	↑	1	-	0	0	1	1
ST parameter 1	1	↑	1	-	VSP15	VSP14	VSP13	VSP12
ND parameter 2	1 -This command is used together with Vertical Scrolling Definition (33h). -These two commands describe the scrolling area and the scrolling mode.	↑ will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: When ML=0 Example: When Top Fixed Area = Bottom Fixed Area = 00, vertical Scrolling Area = 320 and VSP = '3'	1	-	VSP7	VSP6	VSP5	VSP4 -The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory
Description	Example: When Top Fixed Area = Bottom Fixed Area = 00, vertical Scrolling Area = 320 and VSP = '3'	When ML=1 NOTE: When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel		Scan to avoid tearing effect.	VSP refers to the Frame Memory line Pointer			Since the value of the vertical scrolling start address is absolute (with reference to the frame memory), it must not
Restriction	the panel)							enter the fixed area (defined by Vertical Scrolling Definition (33h)- otherwise undesirable image will be displayed on
Register

9.1.29 VSCSAD (37h): Vertical Scroll Start Address of RAM

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availability		Status	Availability
		Normal Mode On, Idle Mode Off, Sleep Out	Yes
		Normal Mode On, Idle Mode On, Sleep Out	Yes
		Partial Mode On, Idle Mode Off, Sleep Out	Yes
		Partial Mode On, Idle Mode On, Sleep Out	Yes
		Sleep In	Yes
	Status	Default Value
Default	Power On Sequence	0000h
	S/W Reset	0000h
	H/W Reset	0000h
Flow Chart	See Vertical Scrolling Definition (33h) description

9.1.30 IDMOFF (38h): Idle Mode Off

38H	IDMOFF (Idle Mode Off)
Inst / Para	D/CX
IDMOFF	0
parameter
	-This command is used to recover from Idle mode on.
Description	-In the idle off mode,
	1. LCD can display 4096, 65k or 262k colors.
	2. Normal frame frequency is applied.
Restriction


Register
availability



Default

9.1.31 IDMON (39h): Idle mode on

39H	IDMON (Idle Mode On)
Inst / Para	D/CX
IDMON	0
parameter	No Parameter
Description






Restriction
Register availability	Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes

3AH							COLMOD (Interface Pixel Format)
Inst / Para				D/CX WRX RDX D17-8	D7	D6	D5
COLMOD	0	↑	1	-	0	0	1
st Parameter 1	1 1	↑ st parameter: Bit	1 D7 D6 D5	-	0 MCU interface. The formats are shown in the table:	D6 Description -	D5 RGB interface color format
Description		Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory. Note2: The Command 3Ah should be set at 55h when writing 16-bit/pixel data into frame memory, but 3Ah should be re-set to 66h when reading pixel data from frame memory.	D4 D3 D2 D1 D0			-	Control interface color format
Restriction						Status	Normal Mode On, Idle Mode Off, Sleep Out
Register							Normal Mode On, Idle Mode On, Sleep Out
availability			Status			Sleep In	Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Default Value
Default			S/W Reset H/W Reset	Power On Sequence			18bit/pixel No change 18bit/pixel
Flow Chart

9.1.32 COLMOD (3Ah): Interface Pixel Format

9.1.33 WRMEMC (3Ch): Write Memory Continue

3CH	WRMEMC (Write Memory Continue)
Inst / Para
WRMEMC	0
ST parameter 1	1
…	1
th parameter N	1

	-If MV=0:
	Data is written continuing from the pixel location after the write range of the previous memory write or write memory




Description


	continue. The page register is then incremented and pixels are written to the frame memory until the page register
	equals the end page (YE) value. The page register is then reset to YS and the column register is incremented. Pixels
	are written to the frame memory until the column register equals the end column (XE) value and the page register

	(XE-XS+1)*(YE-YS+1) the extra pixels are ignored.

Restriction


Register
availability

9.1.34 RDMEMC (3Eh): Read Memory Continue

3EH	RDMEMC (Read Memory Continue)
Inst / Para
RDMEMC	0
ST parameter 1	1
nd parameter 2	1
…	1
th parameter N	1
Description
Restriction

Register
availability



Default

44H		STE (Set Tear ScanLine )
Inst / Para	D/CX	WRX
STE	0	↑
st parameter 1	1	↑
nd parameter 2	1 -This command turns on the display module's Tearing Effect output signal on the TE signal line when the display	↑
Description	module reaches line N. The TE signal is not affected by changing MV. -The tearing effect line on has one parameter that describes the tearing effect output line mode. -The tearing effect output line consist of V-blanking information only. Vertical time scale This command takes affect on the frame following the current frame. Therefore, if the tear effect (TE) output is already on, the TE output shall continue to operate as programmed by the previous tearing effect line on or set tear scanline	Tvdl Tvdh Note that set tear scanline with N=0 is equivalent to tearing effect line on with TEM=0. The tearing effect output line shall be active low when the display module is in sleep mode
Restriction	command until the end of the frame	Status

Register
availability


		Status
Default
		S/W Reset
		H/W Reset

9.1.35 STE (44h): Set Tear Scanline

9.1.36 GSCAN (45h): Get Scanline

45H		GSCAN (Get ScanLine )
Inst / Para	D/CX	WRX
GSCAN	0	↑
st parameter 1	1	1
nd parameter 2	1	1
rd parameter 3	1	1
Description		is denoted as Line 0.
Restriction	-
Register availability
Default		Status H/W Reset

51H							WRDISBV (Write Display Brightness)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5
WRDISBV	0	↑	1	-	0	1	0
Parameter	1	↑	1	-	DBV7	DBV6	DBV5
Description				-This command is used to adjust the brightness value of the display. relationship is defined on the display module specification.
Restriction
Register availability			Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default		Status S/W Reset H/W Reset	Power On Sequence			Default Value 0000h 0000h 0000h

9.1.37 WRDISBV (51h): Write Display Brightness

52H							RDDISBV (Read Display Brightness Value )
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5
RDDISBV	0	↑	1	-	0	1	0
st parameter 1	1	1	↑	-	-	-	-
nd parameter 2	1	1	↑	-	DBV7	DBV6	DBV5
Description
Restriction	-
Register availability		-This command returns the brightness value of the display. -It should be checked what the relationship between this returned value and output brightness of the display. This relationship is defined on the display module specification is. -In principle the relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. -DBV[7:0] is reset when display is in sleep in mode. -DBV[7:0] is '0' when bit BCTRL of write CTRL display command (53h) is '0' -DBV[7:0] IS manual set brightness specified with write CTRL display command (53h) when bit BCTRL is '1' Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence 0000h S/W Reset 0000h H/W Reset
Default						0000h

9.1.38 RDDISBV (52h): Read Display Brightness Value

53H	WRCTRLD (Write CTRL Display )
Inst / Para	D/CX
WRCTRLD	0
Parameter	1

	-BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.



	DD = 0: Display Dimming is off.
Description	DD = 1: Display Dimming is on.
	-BL: Backlight Control On/Off 0 = Off (Completely turn off backlight circuit. Control lines must be low.)
	1 = On
	selected.
Restriction

Register
availability




Default

9.1.39 WRCTRLD (53h): Write CTRL Display

54H	RDCTRLD (Read CTRL value Display )
Inst / Para	D/CX
RDCTRLD	0
st parameter 1	1
nd parameter 2	1
Description	0 = Off 1 = On DD = 0 DD = 1 0 = Off 1 = On
Restriction	-
Register availability
Default

9.1.40 RDCTRLD (54h): Read CTRL Value Display

55H	WRCACE (Write Content Adaptive Brightness Control and Color Enhancement)
Inst / Para	D/CX
WRCACE	0
Parameter	1
	-This command is used to set parameters for image content based adaptive brightness control functionality and Color Enhancement function. -There is possible to used 4 different modes for content adaptive image functionality, which are defined on a table below.





Description







	'-': Don't care
Restriction

Register
availability




Default

56H								RDCABC (Read Content Adaptive Brightness Control )
Inst / Para	D/CX	WRX	RDX	D17-8	D7		D6	D5
RDCABC	0	↑	1	-	0		1	0
st parameter 1	1	1	↑	-	-		-	-
nd parameter 2	1 -This command is used to read the settings for image content based adaptive brightness control functionality. -There is possible to used 4 different modes for content adaptive image functionality, which are defined on a table below.	1	↑	-	0		0	0
Description	'-': Don't care	C1 0 0 0 1 1	C0 1	1 User Interface Mode 0			Function Off Still Picture Moving Image
Restriction	-	Status Normal Mode On, Idle Mode Off, Sleep Out
Register				Normal Mode On, Idle Mode On, Sleep Out
availability		Status		Partial Mode On, Idle Mode Off, Sleep Out	Sleep In	Partial Mode On, Idle Mode On, Sleep Out Yes Default Value
Default		S/W Reset H/W Reset	Power On Sequence			0000h 0000h 0000h

5EH									WRCABCMB (Write CABC Minimum Brightness )
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5	D4	D3
WRCABCMB	0	↑	1	-	0	1	0	1	1
Parameter	1	↑ -This command is used to set the minimum brightness value of the display for CABC function.	1	-	CMB7	CMB6	CMB5	CMB4	CMB3
Description		for CABC. '-': Don't care
Restriction				Normal Mode On, Idle Mode Off, Sleep Out	Status			Yes
Register				Normal Mode On, Idle Mode On, Sleep Out				Yes
availability		Status		Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out	Sleep In	Default Value		Yes	Yes Yes
Default		S/W Reset H/W Reset	Power On Sequence			0000h 0000h 0000h

9.1.43 WRCABCMB (5Eh): Write CABC Minimum Brightness

5FH
Inst / Para
RDCABCMB
st parameter
1
nd parameter
2
Description
Restriction
Register
availability
Default
Flow Chart

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68H								RDABCSDR (Read Automatic Brightness Control Self-Diagnostic Result)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5	D4
RDABCSDR	0	↑	1	-	0	1	1	0
st parameter 1	1	1	↑	-	-	-	-	-
nd parameter 2	1	1	↑	-	D7	D6	0	0
Description		This command indicates the current status of the display self-diagnostic results for automatic brightness control after sleep out -command as described below: -D7: Register loading detection -D6: Functionality detection "-" Don't care
Restriction
Register availability		Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes
Default			Status S/W Reset H/W Reset	Power On Sequence				Default Value 00h 00h 00h

9.1.45 RDABCSDR (68h): Read Automatic Brightness Control Self-Diagnostic Result

9.1.46 RDID1 (DAh): Read ID1

DAH	RDID1 (Read ID1)
Inst / Para	D/CX
RDID1	0
st parameter 1	1
nd parameter 2	1
Description
Restriction	-
Register availability	Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes
Default
Flow Chart

9.1.47 RDID2 (DBh): Read ID2

DBH	RDID2 (Read ID2)
Inst / Para	D/CX
RDID2	0
st parameter 1	1
nd parameter 2	1
Description	'-': Don't care.
Restriction	-
Register availability
Default
Flow Chart

9.1.48 RDID3 (DCh): Read ID3

DCH	RDID3 (Read ID3)
Inst / Para	D/CX
RDID3	0
st parameter 1	1
nd parameter 2	1
Description	This read byte identifies the LCD module/driver.
Restriction	-
Register availability	Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes
Default
Flow Chart

9.2 System Function Command Table 2

Instruction				D/CX WRX RDX D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
	0	↑	1	-	1	0	1	1	0	0	0	0	(B0h)
RAMCTRL	1	↑	1	-	0	0	0	RM	0	0	DM1	DM0		RAM
	1	↑	1	-	1	1	EPF1	EPF0	ENDIAN	RIM	MDT1	MDT0		Control
	0	↑	1	-	1	0	1	1	0	0	0	1	(B1h)
RGBCTRL	1	↑	1	-	WO	RCM1	RCM0	0	VSPL	HSPL	DPL	EPL		RGB
	1	↑	1	-	0	VBP6	VBP5	VBP4	VBP3	VBP2	VBP1	VBP0		Control
	1	↑	1	-	0	0	0	HBP4	HBP3	HBP2	HBP1	HBP0
	0	↑	1	-	1	0	1	1	0	0	1	0	(B2h)
	1	↑	1	-	0	BPA6	BPA5	BPA4	BPA3	BPA2	BPA1	BPA0
	1	↑	1	-	0	FPA6	FPA5	FPA4	FPA3	FPA2	FPA1	FPA0		Porch
PORCTRL	1	↑	1	-	0	0	0	0	0	0	0	PSEN		control
	1	↑	1		BPB3	BPB2	BPB1	BPB0	FPB3	FPB2	FPB1	FPB0
	1	↑	1		BPC3	BPC2	BPC1	BPC0	FPC3	FPC2	FPC1	FPC0
	0	↑	1	-	1	0	1	1	0	0	1	1	(B3h)
FRCTRL1	1	↑	1	-	0	0	0	FRSEN	0	0	DIV1	DIV0		Frame
	1	↑	1	-	NLB2	NLB1	NLB0	RTNB4	RTNB3	RTNB2	RTNB1	RTNB0		Rate Control 1
	1	↑	1	-	NLC2	NLC1	NLC0	RTNC4	RTNC3	RTNC2	RTNC1	RTNC0
	0	↑	1	-	1	0	1	1	0	1	0	1	(B5h)	Partial
PARCTRL	1	↑	1	-	NDL	0	0	PTGISC	ISC3	ISC2	ISC1	ISC0		control
	0	↑	1	-	1	0	1	1	0	1	1	1	(B7h)	Gate
GCTRL	1	↑	1	-	0	VGHS2	VGHS1	VGHS0	0	VGLS2	VGLS1	VGLS0		control
	0	↑	1	-	1	0	1	1	1	0	0	0	(B8h)
	1	↑	1	-	0	0	1	0	1	0	1	0		Gate on
GTADJ	1	↑	1	-	0	0	1	0	1	0	1	1		timing
	1	↑	1	-	0	0	GTA5	GTA4	GTA3	GTA2	GTA1	GTA0		adjustment
	1	↑	1	-	GOFR3	GOFR2	GOFR1	GOFR0	GOF3	GOF2	GOF1	GOF0
	0	↑	1	-	1	0	1	1	1	0	1	0	(BAh)	Digital
DGMEN	1	↑	1	-	0	0	0	0	0	DGMEN	0	0		Gamma Enable
	0	↑	1	-	1	0	1	1	1	0	1	1	(BBh)	VCOM
VCOMS	1	↑	1	-	0	0	VCOMS5	VCOMS4	VCOMS3	VCOMS2	VCOMS1	VCOMS0		Setting
	0	↑	1	-	1	0	1	1	1	1	0	0	(BCh)	Power
POWSAVE	1	↑	1	-	1	1	1	0	1	1	NS	IS		saving mode

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Instruction				D/CX WRX RDX D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
	0	↑	1	-	1	0	1	1	1	1	0	1		(BDh) Display off
DLPOFFSAVE	1	↑	1	-	1	1	1	1	1	1	1	DOFSAVE		power save
	0	↑	1	-	1	1	0	0	0	0	0	0	(C0h)	LCM
LCMCTRL	1	↑	1	-	0	XMY	XBGR	XINV	XMX	XMH	XMV	XGS		Control
	0	↑	1	-	1	1	0	0	0	0	0	1	(C1h)
	1	↑	1	-	ID17	ID16	ID15	ID14	ID13	ID12	ID11	ID10
IDSET	1	↑	1	-	ID27	ID26	ID25	ID24	ID23	ID22	ID21	ID20		ID Setting
	1	↑	1	-	ID37	ID36	ID35	ID34	ID33	ID32	ID31	ID30
	0	↑	1	-	1	1	0	0	0	0	1	0	(C2h)	VDV and
VDVVRHEN	1	↑	1	-	0	0	0	0	0	0	0	CMDEN		VRH
	1	↑	1	-	1	1	1	1	1	1	1	1		Command Enable
VRHS	0	↑	1		1	1	0	0	0	0	1	1	(C3h)	VRH Set
	1	↑	1		0	0	VRHS5	VRHS4	VRHS3	VRHS2	VRHS1	VRHS0
VDVSET	0	↑	1	-	1	1	0	0	0	1	0	0	(C4h)	VDV
	1	↑	1	-	0	0	VDVS5	VDVS4	VDVS3	VDVS2	VDVS1	VDVS0		Setting
VCMOFSET	0	↑	1	-	1	1	0	0	0	1	0	1	(C5h)	VCOM
	1	↑	1	-	0	0	VCMOFS5	VCMOFS4	VCMOFS3	VCMOFS2	VCMOFS1	VCMOFS0		Offset Set
FRCTR2	0	↑	1		1	1	0	0	0	1	1	0		(C6h) FR Control
	1	↑	1		NLA2	NLA1	NLA0	RTNA4	RTNA3	RTNA2	RTNA1	RTNA0		2
CABCCTRL	0	↑	1	-	1	1	0	0	0	1	1	1	(C7h)	CABC
	1	↑	1	-	0	0	0	0	LEDONREV	DPOFPWM	PWMFIX	PWMPOL		Control
	0	↑	1	-	1	1	0	0	1	0	0	0	(C8h)	Register
REGSEL1														value
	1	↑	1	-	0	0	0	0	1	0	0	0		selection1
	0	↑	1	-	1	1	0	0	1	0	1	0	(CAh)	Register
REGSEL2	1	↑	1	-	0	0	0	0	1	1	1	1		value selection2
	0	↑	1	-	1	1	0	0	1	1	0	0	(CCh)	PWM
PWMFRSEL														Frequency
	1	↑	1	-	0	0	CS2	CS1	CS0	CLK2	CLK1	CLK0		Selection
	0	↑	1	-	1	1	0	1	0	0	0	0	(D0h)	Power
PWCTRL1	1	↑	1	-	1	0	1	0	0	1	0	0		Control 1
	1	↑	1	-	AVDD1	AVDD0	AVCL1	AVCL0	0	0	VDS1	VDS0

Version 1.0 Page 254 of 317 2017/09

Instruction				D/CX WRX RDX D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
	0	↑	1	-	1	1	0	1	0	0	1	0	(D2h)	Enable
VAPVANEN	1	↑	1	-	0	1	0	0	1	1	0	0		VAP/VAN signal output
	0	↑	1	-	1	1	0	1	1	1	1	1	(DFh)
	1	↑	1	-	0	1	0	1	1	0	1	0	(5Ah)
CMD2EN	1	↑	1	-	0	1	1	0	1	0	0	1	(69h)	Command 2 Enable
	1	↑	1	-	0	0	0	0	0	0	1	0	(02h)
	1	↑	1	-	0	0	0	0	0	0	0	EN
	0	↑	1	-	1	1	1	0	0	0	0	0	(E0h)
	1	↑	1	-	V63P3	V63P2	V63P1	V63P0	V0P3	V0P2	V0P1	V0P0
	1	↑	1	-	0	0	V1P5	V1P4	V1P3	V1P2	V1P1	V1P0
	1	↑	1	-	0	0	V2P5	V2P4	V2P3	V2P2	V2P1	V2P0		Positive Voltage Gamma Control
	1	↑	1	-	0	0	0	V4P4	V4P3	V4P2	V4P1	V4P0
	1	↑	1	-	0	0	0	V6P4	V6P3	V6P2	V6P1	V6P0
	1	↑	1	-	0	0	J0P1	J0P0	V13P3	V13P2	V13P1	V13P0
PVGAMCTRL	1	↑	1	-	0	V20P6	V20P5	V20P4	V20P3	V20P2	V20P1	V20P0
	1	↑	1	-	0	V36P2	V36P1	V36P0	0	V27P2	V27P1	V27P0
	1	↑	1	-	0	V43P6	V43P5	V43P4	V43P3	V43P2	V43P1	V43P0
	1	↑	1	-	0	0	J1P1	J1P0	V50P3	V50P2	V50P1	V50P0
	1	↑	1	-	0	0	0	V57P4	V57P3	V57P2	V57P1	V57P0
	1	↑	1	-	0	0	0	V59P4	V59P3	V59P2	V59P1	V59P0
	1	↑	1	-	0	0	V61P5	V61P4	V61P3	V61P2	V61P1	V61P0
	1	↑	1	-	0	0	V62P5	V62P4	V62P3	V62P2	V62P1	V62P0
	0	↑	1	-	1	1	1	0	0	0	0	1	(E1h)
	1	↑	1	-	V63N3	V63N2	V63N1	V63N0	V0N3	V0N2	V0N1	V0N0		Negative
	1	↑	1	-	0	0	V1N5	V1N4	V1N3	V1N2	V1N1	V1N0		Voltage
NVGAMCTRL	1	↑	1	-	0	0	V2N5	V2N4	V2N3	V2N2	V2N1	V2N0		Gamma
	1	↑	1	-	0	0	0	V4N4	V4N3	V4N2	V4N1	V4N0		Control
	1	↑	1	-	0	0	0	V6N4	V6N3	V6N2	V6N1	V6N0

Instruction				D/CX WRX RDX D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
	1	↑	1	-	0	0	J0N1	J0N0	V13N3	V13N2	V13N1	V13N0
	1	↑	1		0	V20N6	V20N5	V20N4	V20N3	V20N2	V20N1	V20N0
	1	↑	1		0	V36N2	V36N1	V36N0	0	V27N2	V27N1	V27N0
	1	↑	1		0	V43N6	V43N5	V43N4	V43N3	V43N2	V43N1	V43N0
	1	↑	1		0	0	J1N1	J1N0	V50N3	V50N2	V50N1	V50N0
	1	↑	1		0	0	0	V57N4	V57N3	V57N2	V57N1	V57N0
	1	↑	1		0	0	0	V59N4	V59N3	V59N2	V59N1	V59N0
	1	↑	1		0	0	V61N5	V61N4	V61N3	V61N2	V61N1	V61N0
	1	↑	1		0	0	V62N5	V62N4	V62N3	V62N2	V62N1	V62N0
DGMLUTR	0 1 1 1 1 1 1 1 1	↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑	1 1 1 1 1 1 1 1 1	- - - - - - - - -	1	1 DGM_LUT_R00[7:0] DGM_LUT_R01[7:0] … … DGM_LUT_R62[7:0] DGM_LUT_R63[7:0]	1	0	0 DGM_LUT_R30[7:0] DGM_LUT_R31[7:0]	0	1	0	(E2h)	Gamma Look-up Table for
	0 1 1 1	↑ ↑ ↑ ↑	1 1 1 1	- - - -	1	1	1	0	0 DGM_LUT_B00[7:0] DGM_LUT_B01[7:0] …	0	1	1	(E3h)	Digital Gamma
DGMLUTB	1 1 1 1 1	↑ ↑ ↑ ↑ ↑	1 1 1 1 1	- - - - -					DGM_LUT_B30[7:0] DGM_LUT_B31[7:0] … DGM_LUT_B62[7:0] DGM_LUT_B63[7:0]					Look-up Table for Blue
	0	↑	1	-	1	1	1	0	0	1	0	0	(E4h)	Gate
GATECTRL	1	↑	1	-	0	0	NL5	NL4	NL3	NL2	NL1	NL0		control

Instruction				D/CX WRX RDX D17-8	D7	D6	D5	D4	D3	D2	D1	D0	Hex	Function
	1	↑	1	-	0	0	SCN5	SCN4	SCN3	SCN2	SCN1	SCN0
	1	↑	1	-	0	0	0	TMG	0	SM	0	GS
SPI2EN	0	↑	1	-	1	1	1	0	0	1	1	1	(E7h)	SPI2
	1	↑	1	-	0	0	0	SPI2EN	0	0	0	SPIRD		enable
	0	↑	1	-	1	1	1	0	1	0	0	0	(E8h)	Power
PWCTRL2	1	↑	1	-	1	0	SBCLK1	SBCLK0	0	0		STP14CK1 STP14CK0		Control 2
	0	↑	1	-	1	1	1	0	1	0	0	1	(E9h)
	1	↑	1	-	0	0	0	SEQ4	SEQ3	SEQ2	SEQ1	SEQ0		Equalize
EQCTRL	1	↑	1	-	0	0	0	SPRET4	SPRET3	SPRET2	SPRET1	SPRET0		Time Control
	1	↑	1	-	0	0	0	0	GEQ3	GEQ2	GEQ1	GEQ0
PROMCTRL	0	↑	1	-	1	1	1	0	1	1	0	0	(ECh)	Program
	1	↑	1	-	0	0	0	0	0	0	0	1		Control
	0	↑	1	-	1	1	1	1	1	0	1	0	(FAh)
	1	↑	1	-	0	1	0	1	1	0	1	0		Program
PROMEN	1	↑	1	-	0	1	1	0	1	0	0	1		Mode
	1	↑	1	-	1	1	1	0	1	1	1	0		Enable
	1	↑	1	-	0	0	0	0	0	PROMEN	0	0
	0	↑	1	-	1	1	1	1	1	1	0	0	(FCh)
NVMSET	1	↑	1	-	ADD7	ADD6	ADD5	ADD4	ADD3	ADD2	ADD1	ADD0		NVM Setting
	1	↑	1	-	D7	D6	D5	D4	D3	D2	D1	D0
	0	↑	1	-	1	1	1	1	1	1	1	0	(FEh)	Program Action
PROMACT	1	↑	1	-	0	0	0	1	1	0	0	1
	1	↑	1	-	1	0	1	0	0	1	0	1

9.2.1 RAMCTRL (B0h): RAM Control

B0H	RAMCTR (RAM Control)
Inst / Para	D/CX
RAMCTRL	0
st Parameter 1	1
nd Parameter 2	1
Description	DM[1:0] 00h 01h 10h 11h ENDIAN : 0 1

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		Normal Mode On, Idle Mode Off, Sleep Out		Yes
	Status	Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In	Default Value	Yes Yes Yes
Default		Power On Sequence S/W Reset H/W Reset	00h/F0h 00h/F0h 00h/F0h

9.2.2 RGBCTRL (B1h): RGB Interface Control

B1H	RGBCTRL (RGB Interface Control)
Inst / Para	D/CX
RGBCTRL	0
st parameter 1	1
nd parameter 2	1
rd parameter 3	1

	WO
	0
	1

	RCM[1:0]
	00
	01
	10
	11
Description	VSPL : Sets the signal polarity of the VSYNC pin. VSPL="0", Low active VSPL="1", High active HSPL : Sets the signal polarity of the HSYNC pin. HSPL="0", Low active HSPL="1", High active DPL : Sets the signal polarity of the DOTCLK pin. DPL = "0" The data is input on the positive edge of DOTCLK DPL = "1" The data is input on the negative edge of DOTCLK EPL : Sets the signal polarity of the ENABLE pin. EPL = "0" The data DB17-0 is written when ENABLE = "1". Disable data write operation when ENABLE = "0". EPL = "1" The data DB17-0 is written when ENABLE = "0". Disable data write operation when ENABLE = "1". VBP[6:0]: RGB interface Vsync back porch setting. Minimum setting is 0x02. HBP[4:0]: RGB interface Hsync back porch setting. Please refer to the section 8.9.3 for

	Status		Availability
	Normal Mode On, Idle Mode Off, Sleep Out		Yes
	Normal Mode On, Idle Mode On, Sleep Out		Yes
	Partial Mode On, Idle Mode Off, Sleep Out		Yes
	Partial Mode On, Idle Mode On, Sleep Out		Yes
	Sleep In		Yes
	Status	Default Value
Default	Power On Sequence	40h/02h/14h
	S/W Reset	40h/02h/14h
	H/W Reset	40h/02h/14h

9.2.3 PORCTRL (B2h): Porch Setting

B2H	PORCTRL (Porch Setting)
Inst / Para	D/CX
PORCTRL	0
st parameter 1	1
nd parameter 2	1
rd parameter 3	1
th parameter 4	1
th parameter 5	1
	BPA[6:0]: Back porch setting in normal mode. The minimum setting is 0x01.
	FPA[6:0]: Front porch setting in normal mode. The minimum setting is 0x01.
	PSEN: Enable separate porch control.
	PSEN
Description	0
	1 Enable separate porch control
	BPB[3:0]: Back porch setting in idle mode. The minimum setting is 0x01.
	FPB[3:0]: Front porch setting in idle mode. The minimum setting is 0x01.
	BPC[3:0]: Back porch setting in partial mode. The minimum setting is 0x01.
	FPC[3:0]: Front porch setting in partial mode. The minimum setting is 0x01.


Register
Availability



Default

9.2.4 FRCTRL1 (B3h): Frame Rate Control 1 (In partial mode/ idle colors)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX FRCTRL1 0 ↑ 1 - 1 0 1 1 0 0 1 1 (B3h) st parameter 1 1 ↑ 1 - 0 0 0 FRSEN 0 0 DIV1 DIV0 nd parameter 2 1 ↑ 1 - NLB2 NLB1 NLB0 RTNB4 RTNB3 RTNB2 RTNB1 RTNB0 rd parameter 3 1 ↑ 1 - NLC2 NLC1 NLC0 RTNC4 RTNC3 RTNC2 RTNC1 RTNC0 FRSEN: Enable separate frame rate control. When FRSEN=0, Frame rate of idle and partial mode are determined by C6h When FRSEN=1, Frame rate of idle and partial mode are determined by B3h FRSEN Mode 0 Disable separate FR control 1 Enable separate FR control DIV[1:0]: Frame rate divided control DIV[1:0] Mode 00 Divide by 1 01 Divide by 2 10 Divide by 4 11 Divide by 8 NLB[2:0]: Inversion selection in idle mode. Description 0x00: dot inversion. 0x07: column inversion. RTNB[4:0]: Frame rate control in idle mode. RTNB[4:0] FR in idle mode (Hz) RTNB[4:0] FR in idle mode (Hz) 00h 119 10h 58 01h 111 11h 57 02h 105 12h 55 03h 99 13h 53 04h 94 14h 52 05h 90 15h 50 06h 86 16h 49 07h 82 17h 48 08h 78 18h 46 09h 75 19h 45	B3H	FRCTRL1 (Frame rate control 1)

		0Ah		72	1Ah	44
		0Bh		69	1Bh	43
		0Ch		67	1Ch	42
		0Dh		64	1Dh	41
		0Eh		62	1Eh	40
	Note: 1. If FRSEN=1, Frame rate in idle mode=10MHz/(320+(FPB[3:0]+BPB[3:0])4)(250+RTNB[4:0]*16). 2. FPB[6:0] and BPB[6:0] are in command B2h 3. In this frame rate table, FPB[3:0]=03h, BPB[3:0]=03h	0Fh NLC[2:0]: Inversion setting in partial mode. 0x00: dot inversion. 0x07: column inversion.	Status	60 Normal Mode On, Idle Mode Off, Sleep Out	1Fh RTNC[4:0]: Frame rate control in partial mode. This setting is equal to RTNB.	39 Availability Yes
Register				Normal Mode On, Idle Mode On, Sleep Out		Yes
Availability		Status	Sleep In	Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Default Value		Yes Yes Yes
Default		Power On Sequence S/W Reset H/W Reset		00h/0Fh/0Fh 00h/0Fh/0Fh 00h/0Fh/0Fh

9.2.5 PARCTRL (B5h): Partial Control

B5H	PARCTRL (Partial Control)
Inst / Para	D/CX
PARCTRL	0
Parameter	1
Description	ISC[3:0] 00h 01h 02h 03h 0Fh Note:
Register Availability
Default

9.2.6 GCTRL (B7h): Gate Control

B7H	GCTRL (Gate Control)
Inst / Para	D/CX
GCTRL	0
Parameter	1
	VGHS[2:0]: VGH Setting.

	00h
	01h
	02h
	03h
	04h
	05h
	06h
	07h
Description


	00h
	01h
	02h
	03h
	04h
	05h
	06h
	07h



Register Availability

	Status	Default Value
Default	Power On Sequence	35h
	S/W Reset	35h
	H/W Reset	35h

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Register
Availability
Default

BAH	DGMEN (Digital Gamma Enable)
Inst / Para	D/CX
DGMEN	0
Parameter	1
	DGMEN:
Description	"0": disable digital gamma.




Register Availability



Default

9.2.8 DGMEN (BAh): Digital Gamma Enable

9.2.9 VCOMS (BBh): VCOM Setting

BBH			VCOMS (VCOM Setting)
Inst / Para	D/CX	WRX	RDX
VCOMS	0	↑	1
Parameter	1	↑ VCOMS[5:0]:	1














Description

		1Dh	0.825	3Dh	1.625
		1Eh	0.85	3Eh	1.65
		1Fh Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out	0.875 Status	3Fh	1.675 Availability Yes Yes
Register Availability	Status		Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Value		Yes Yes Yes
Default	S/W Reset H/W Reset	Power On Sequence	20h 20h 20h

BCH	POWSAVE (Power Saving Mode)
Inst / Para	D/CX
POWSAVE	0
Parameter	1
	NS: Power save for normal mode.
Description	When NS=0, power consumption in normal mode will be saved.
	IS: Power save for Idle mode.




Register Availability



Default

9.2.10 POWSAVE(BCh): Power Saving Mode

BDH							DLPOFFSAVE (Display off power save)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5
DLPOFFSAVE	0	↑	1	-	1	0	1
Parameter	1	↑ DOFSAVE: Power save for display off mode.	1	-	1	1	1
Description		Status Availability	Normal Mode On, Idle Mode On, Sleep Out		Normal Mode On, Idle Mode Off, Sleep Out
Register Availability		Status	Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes				Default Value
Default			S/W Reset H/W Reset	Power On Sequence		FFh FFh FFh

9.2.11 DLPOFFSAVE (BDh): Display off power save

9.2.12 LCMCTRL (C0h): LCM Control

C0H		LCMCTRL (LCM Control)
Inst / Para	D/CX	WRX
LCMCTRL	0	↑
st parameter 1	1 XMY: XOR MY setting in command 36h. XBGR: XOR RGB setting in command 36h. XREV: XOR inverse setting in command 21h	↑
Description	XMH: this bit can reverse source output order and only support for RGB interface without RAM mode XMV: XOR MV setting in command 36h XMX: XOR MX setting in command 36h.

		Normal Mode On, Idle Mode Off, Sleep Out
Register Availability

		Status
Default

9.2.13 IDSET (C1h): ID Code Setting

C1H							IDSET (ID Code Setting)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5
IDSET	0	↑	1	-	1	1	0
Parameter 1st	1	↑	1	-	ID17	ID16	ID15
Parameter 2nd	1	↑	1	-	ID27	ID26	ID25
Parameter 3rd	1	↑ ID1[7:0]: ID1 Setting.	1	-	ID37	ID36	ID35
Description	ID2[7:0]: ID2 Setting. ID3[7:0]: ID3 Setting.
Availability		Status		Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Yes	Sleep In		Default Value
Default			S/W Reset	Power On Sequence			85h/85h/52h 85h/85h/52h
Register			H/W Reset				85h/85h/52h

C2H									VDVVRHEN (VDV and VRH Command Enable)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5	D4	D3
VDVVRHEN	0	↑	1	-	1	1	0	0	0
st Parameter 1	1	↑	1	-	0	0	0	0	0
nd Parameter 2	1	↑	1	-	1	1	1	1	1
Description	CMDEN: VDV and VRH command write enable. CMDEN="0": VDV and VRH register value comes from NVM. CMDEN="1", VDV and VRH register value comes from command write.
Register Availability					Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In				Availability Yes Yes Yes Yes Yes
Default		Status	S/W Reset H/W Reset	Power On Sequence		Default Value 01h/FFh 01h/FFh 01h/FFh

9.2.14 VDVVRHEN (C2h): VDV and VRH Command Enable

9.2.15 VRHS (C3h): VRH Set

C3H	VRHS (VRH Set)
Inst / Para	D/CX
VRHS	0
st Parameter 1	1















Description













	05h

					ST7789VW
	06h	-3.85+( vcom+vcom offset-vdv)		1Bh	-4.9+( vcom+vcom offset-vdv)
	07h	-3.9+( vcom+vcom offset-vdv)		1Ch	-4.95+( vcom+vcom offset-vdv)
	08h	-3.95+( vcom+vcom offset-vdv)		1Dh	-5+( vcom+vcom offset-vdv)
	09h	-4+( vcom+vcom offset-vdv)		1Eh	-5.05+( vcom+vcom offset-vdv)
	0Ah	-4.05+( vcom+vcom offset-vdv)		1Fh	-5.1+( vcom+vcom offset-vdv)
	0Bh	-4.1+( vcom+vcom offset-vdv)		20h	-5.15+( vcom+vcom offset-vdv)
	0Ch	-4.15+( vcom+vcom offset-vdv)		21h	-5.2+( vcom+vcom offset-vdv)
	0Dh	-4.2+( vcom+vcom offset-vdv)		22h	-5.25+( vcom+vcom offset-vdv)
	0Eh	-4.25+( vcom+vcom offset-vdv)		23h	-5.3+( vcom+vcom offset-vdv)
	0Fh	-4.3+( vcom+vcom offset-vdv)		24h	-5.35+( vcom+vcom offset-vdv)
	10h	-4.35+( vcom+vcom offset-vdv)		25h	-5.4+( vcom+vcom offset-vdv)
	11h	-4.4+( vcom+vcom offset-vdv)		26h	-5.45+( vcom+vcom offset-vdv)
	12h	-4.45+( vcom+vcom offset-vdv)		27h	-5.5+( vcom+vcom offset-vdv)
	13h	-4.5+( vcom+vcom offset-vdv)		28h~3Fh	Reserved
	14h	-4.55+( vcom+vcom offset-vdv)		--	--
Register Availability	Status	Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In	Default Value		Availability Yes Yes Yes Yes Yes
Default	S/W Reset H/W Reset	Power On Sequence	0Bh 0Bh 0Bh

9.2.16 VDVS (C4h): VDV Set

C4H	VDVS (VDV Set)
Inst / Para	D/CX
VDVS	0
st Parameter 1	1















Description

		1Dh	-0.075	3Dh	0.725
		1Eh	-0.05	3Eh	0.75
		1Fh Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out	-0.025 Status	3Fh	0.775 Availability Yes Yes
Register Availability	Status	Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out	Sleep In Default Value		Yes Yes Yes
Default		Power On Sequence	20h
	S/W Reset H/W Reset		20h	20h

9.2.17 VCMOFSET (C5h): VCOM Offset Set

C5H	VCMOFSET (VCOM Offset Set)
Inst / Para	D/CX
VCMOFSET	0
st Parameter 1	1















Description

	1Dh		-0.075	3Dh	0.725
	1Eh		-0.05	3Eh	0.75
	1Fh Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out	Status	-0.025	3Fh Availability	0.775
Register Availability	Status	Sleep In	Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Default Value	Yes Yes
Default	Power On Sequence S/W Reset H/W Reset		20h 20h 20h

C6H
Inst / Para
FRCTRL2
st Parameter
1
Description
Register
Availability

	Sleep In
	Status	Default Value
Default	Power On Sequence	0Fh
	S/W Reset	0Fh
	H/W Reset	0Fh

9.2.19 CABCCTRL (C7h): CABC Control

C7H	CABCCTRL (CABC Control)
Inst / Para	D/CX
CABCCTRL	0
st Parameter 1	1
	LEDONREV: Reverse the status of LED_ON:
	"0": keep the status of LED_ON.
	"1": reverse the status of LED_ON.
	DPOFPWM: initial state control of LEDPWM.

Description	"1": The initial state of LEDPWM is high.


	"1": fix LEDPWM in "ON" status.
	PWMPOL: LEDPWM polarity control.
	"0": polarity high.




Register Availability



Default

9.2.20 REGSEL1 (C8h): Register Value Selection 1

C8H	REGSEL1 (Register Value Selection 1)
Inst / Para	D/CX
REGSEL1	0
Parameter	1
Description	Reserved for testing



Register Availability



Default

9.2.21 REGSEL2 (CAh): Register Value Selection 2

CAH	REGSEL2 (Register Value Selection 2)
Inst / Para	D/CX
REGSEL2	0
Parameter	1
Description	Reserved for testing
Register Availability	Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes
Default	Status Power On Sequence S/W Reset H/W Reset

CCH	PWMFRSEL (PWM Frequency Selection)
Inst / Para	D/CX
PWMFRSEL	0
st Parameter 1	1

	CS[2:0] CLK[2:0]
	00h
	01h
	02h
Description	03h
	04h
	05h
	06h
	07h



Register
Availability	Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out


Default

9.2.22 PWMFRSEL (CCh): PWM Frequency Selection

9.2.23 PWCTRL1 (D0h): Power Control 1

D0H	PWCTRL (Power Control)
Inst / Para	D/CX
PWCTRL	0
st Parameter 1	1
nd Parameter 2	1


	00h
	01h
	02h
	03h
Description
	00h
	01h
	02h
	03h
	VDS[1:0]:

	00h
	01h
	02h
	03h



Register Availability

	Status	Default Value
Default	Power On Sequence	A4h/A1h
	S/W Reset	A4h/A1h
	H/W Reset	A4h/A1h

D/CX	WRX	RDX	D17-8	D7	D6	D5	D4	D3	D2	D1	D0	HEX
0	↑	1	-	1	1	0	1	0	0	1	0	(D2h)
1	↑	1 - 0 1 0 0 1 1 0
Enable VAP/VAN signal output			Status S/W Reset H/W Reset		00h 00h 00h Power On Sequence	Yes Default Value Status Sleep In	Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out	Availability Yes Yes Yes Yes		VAPVANEN (Enable VAP/VAN signal output)		0

9.2.24 VAPVANEN (D2h): Enable VAP/VAN signal output

9.2.25 CMD2EN (DFh): Command 2 Enable

DFH	CMD2EN (Command 2 Enable)
Inst / Para	D/CX
CMD2EN	0
st Parameter 1	1
nd Parameter 2	1
rd Parameter 3	1
th Parameter 4	1
	EN:
Description	"0": Commands in Command table 2 cannot be executed when EXTC level is "Low".




Register Availability



Default

9.2.26 PVGAMCTRL (E0h): Positive Voltage Gamma Control

E0H							PVGAMCTRL (Positive Voltage Gamma Control)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5
PVGAMCTRL	0	↑	1	-	1	1	1
st Parameter 1	1	↑	1	-	V63P3	V63P2	V63P1
nd Parameter 2	1	↑	1	-	0	0	V1P5
rd Parameter 3	1	↑	1	-	0	0	V2P5
th Parameter 4	1	↑	1	-	0	0	0
th Parameter 5	1	↑	1	-	0	0	0
th Parameter 6	1	↑	1	-	0	0	J0P1
th Parameter 7	1	↑	1	-	0	V20P6	V20P5
th Parameter 8	1	↑	1	-	0	V36P2	V36P1
th Parameter 9	1	↑	1	-	0	V43P6	V43P5
10th Parameter	1	↑	1	-	0	0	J1P1
11th Parameter	1	↑	1	-	0	0	0
12th Parameter	1	↑	1	-	0	0	0
13th Parameter	1	↑	1	-	0	0	V61P5
14th Parameter	1 VP0[3:0] VP1[5:0] VP2[5:0] VP4[4:0] VP6[4:0]	↑ Please refer to 8.19. Default value:	1	-	0 Value(hex) 0 2C 2E 15 10	0	V62P5
Description	VP62[5:0]	VP13[3:0] VP20[6:0] VP27[2:0] VP36[2:0] VP43[6:0] VP50[3:0] VP57[4:0] VP59[4:0] VP61[5:0]			9 48 3 3 53 B 19 18 20 25

	VP63[3:0]	7
	JP0[1:0]
	JP1[1:0]



Register Availability


Default		Status
		Power On Sequence
		S/W Reset
		H/W Reset

9.2.27 NVGAMCTRL (E1h): Negative Voltage Gamma Control

E1H								NVGAMCTRL (Negative Voltage Gamma Control)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5	D4
NVGAMCTRL	0	↑	1	-	1	1	1	0
st Parameter 1	1	↑	1	-	V63N3	V63N2	V63N1	V63N0
nd Parameter 2	1	↑	1	-	0	0	V1N5	V1N4
rd Parameter 3	1	↑	1	-	0	0	V2N5	V2N4
th Parameter 4	1	↑	1	-	0	0	0	V4N4
th Parameter 5	1	↑	1	-	0	0	0	V6N4
th Parameter 6	1	↑	1	-	0	0	J0N1	J0N0
th Parameter 7	1	↑	1	-	0	V20N6	V20N5	V20N4
th Parameter 8	1	↑	1	-	0	V36N2	V36N1	V36N0
th Parameter 9	1	↑	1	-	0	V43N6	V43N5	V43N4
10th Parameter	1	↑	1	-	0	0	J1N1	J1N0
11th Parameter	1	↑	1	-	0	0	0	V57N4
12th Parameter	1	↑	1	-	0	0	0	V59N4
13th Parameter	1	↑	1	-	0	0	V61N5	V61N4
14th Parameter	1 VN0[3:0] VN1[5:0] VN2[5:0] VN4[4:0] VN6[4:0]	↑ Please refer to 8.19. Default value:	1	-	0 Value(hex) 0 2C 2E 15 10	0	V62N5	V62N4
Description	VN13[3:0] VN62[5:0]	VN20[6:0] VN27[2:0] VN36[2:0] VN43[6:0] VN50[3:0] VN57[4:0] VN59[4:0] VN61[5:0]			9 48 3 3 53 B 19 18 20 25

	VN63[3:0]		7
	JN0[1:0]		0
	JN1[1:0]		0
			Status


Register Availability

			Sleep In
Default		Status
		Power On Sequence	Refer to description
		S/W Reset
		H/W Reset	Refer to description

9.2.28 DGMLUTR (E2h): Digital Gamma Look-up Table for Red

32th Parameter
1
↑
1
-
DGM_LUT_R31[7:0]
1
↑
1
-
…
…
63th Parameter
1
↑
1
-
DGM_LUT_R62[7:0]
64th Parameter
1
↑
1
-
DGM_LUT_R63[7:0]
Please refer to 8.20.
Default value:
Value(hex)
DGM_LUT_R00[7:0]
00h
DGM_LUT_R01[7:0]
04h
Description
…
…
DGM_LUT_R30[7:0]
78h
DGM_LUT_R31[7:0]
7Ch
…
…
DGM_LUT_R62[7:0]
F8h
DGM_LUT_R63[7:0]
FCh
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Register
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Availability
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Default
Power On Sequence
Refer to description

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	H/W Reset	Refer to description

9.2.29 DGMLUTB (E3h): Digital Gamma Look-up Table for Blue

E3H	DGMLUTB (Digital Gamma Look-up Table for Blue)
Inst / Para	D/CX
DGMLUTB	0
st Parameter 1	1
nd Parameter 2	1
…	1
31th Parameter	1
32th Parameter	1
…	1
63th Parameter	1
64th Parameter	1




Description









Register Availability



Default

	H/W Reset	Refer to description

9.2.30 GATECTRL (E4h): Gate Control

E4H	GATECTRL (Gate Control)
Inst / Para	D/CX
GATECTRL	0
st Parameter 1	1
nd Parameter 2	1
rd Parameter 3	1

	NL[5:0]
	0x00
	0x01
	0x02
	…
	0x27


	0x00
Description	0x01
	…
	0x27
	TMG: Gate mirror selection TMG="0", local mirror as the number of gate line setting is not 320.
	TMG="1", full mirror as the number of gate line setting is 320.
	SM: Gate interlace mode selection


	GS: Gate scan direction




Register
Availability

	Status	Default Value
Default	Power On Sequence	27h/00h/10h
	S/W Reset	27h/00h/10h
	H/W Reset	27h/00h/10h

9.2.31 SPI2EN (E7h): SPI2 Enable

E7H	SPI2EN (SPI2 Enable)
Inst / Para	D/CX
SPI2EN	0
Parameter	1
	SPI2EN: 2 data lane enable control.
	"0": disable 2 data lane mode.
	"1": enable 2 data lane mode
	SPIRD: SPI read enable for command table 2
Description	"0": commands in command table 2 can not be read in serial interface
	"1": commands in command table 2 can be read in serial interface.
	Note:




Register Availability



Default

9.2.32 PWCTRL2 (E8h): Power Control 2

E8H	PWCTRL2 (Power Control 2)
Inst / Para	D/CX
PWCTRL2	0
Parameter	1


	00h
	01h
	02h
	03h
Description


	00h
	01h
	02h
	03h



Register Availability



Default

9.2.33 EQCTRL (E9h): Equalize time control

E9H	EQCTRL (Equalize time Control)
Inst / Para	D/CX
EQCTRL	0
st Parameter 1	1
nd Parameter 2	1
rd Parameter 3	1

	Source equalize time: SEQ[4:0]*400ns, SEQ[4:0]=0x01~0x1f







Description

	Source equalize time: SPRET[4:0]43*1period of dotclk, SPRET[4:0]=0x01~0x1f
	GEQ[3:0]: Gate Equalize Time








Register Availability

		Status	Default Value
Default		Power On Sequence	11h/11h/08h
	S/W Reset	11h/11h/08h
		H/W Reset	11h/11h/08h

ECH							PROMCTRL (Program Mode Control)
Inst / Para	D/CX	WRX	RDX	D17-8	D7	D6	D5
PROMCTRL	0	↑	1	-	1	1	1
Parameter	1	↑	1	-	0	0	0
Description	When program mode enable, this command need be set. Status Availability				Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out
Register Availability	Partial Mode On, Idle Mode On, Sleep Out Status				Partial Mode On, Idle Mode Off, Sleep Out Sleep In	Yes	Default Value
Default	Power On Sequence 00h		S/W Reset H/W Reset			00h 00h

9.2.34 PROMCTRL (ECh): Program Mode Control

9.2.35 PROMEN (FAh): Program Mode Enable

FAH	PROMEN (Program Mode Enable)
Inst / Para	D/CX
PROMEN	0
st Parameter 1	1
nd Parameter 2	1
rd Parameter 3	1
th Parameter 4	1

Description
	"1": Program mode enable


	Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes
Register Availability



Default

9.2.36 NVMSET (FCh): NVM Setting

FCH	NVMSET (NVM Setting)
Inst / Para	D/CX
NVMSET	0
st Parameter 1	1
nd Parameter 2	1

Description



Register Availability



Default

9.2.37 PROMACT (FEh): Program action

FEH		PROMACT (Program action)
Inst / Para	D/CX	WRX
PROMACT	0	↑
st Parameter 1	1	↑
nd Parameter 2	1	↑
Description		When program mode enable, this command need be set.

Register Availability

		Status
Default

		H/W Reset

10 APPLICATION

10.1 Configuration of Power Supply Circuit

Version 1.0 Page 313 of 317 2017/09

10.2 Voltage Generation

The following is the ST7789VW analog voltage pattern diagram:

Figure 38 Power Booster Level

10.3 Relationship about source voltage

The relationship about source voltage is shown as below:

Figure 39 Relationship about source voltage

Note: if VDV=0V, VBP=VBN=VCOM+VCOM OFFSET.

10.4 Applied Voltage to the TFT panel

Figure 40 Voltage Output to TFT LCD Panel

11 REVISION HISTORY

Version	Date	Description
V1.0	2017/09	First issue

Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
ST7789VW	Part number not specified	—

ST7789

Overview

Features

Pin Configuration

Electrical Characteristics

7.1 Absolute Operation Range

Table 1 Absolute Operation Range

7.2 DC Characteristics

Table 2 Basic DC Characteristics

7.3 Power Consumption

Table 3 Power Consumption

7.4 AC Characteristics

Table 5 3-line serial Interface Characteristics

Table 6 4-line serial Interface Characteristics

Figure 6 RGB Interface Timing Characteristics

7.4.5 Reset Timing:

Figure 7 Reset Timing

Table 9 Reset Timing

8 FUNCTION DESCRIPTION

8.1 MPU Interface Type Selection

8.2 8080- Series MCU Parallel Interface Ⅰ

8.2.1 Write cycle sequence

8.2.2 Read cycle sequence

Figure 10 8080-series RDX protocol

8.3 8080- series MCU Parallel Interface Ⅱ

8.4 Serial Interface

Table 13 Selection of serial interface

8.4.1 Pin description

8.4.2 Command write mode

8.4.3 Read function

8.4.4 3-line serial interface /** Ⅰ Ⅱ **protocol

8.4.5 4-line serial protocol

8.4.6 2 data lane serial Interface

2 data lane hardware suggestion and Pin description:

2 data lane serial interface

Figure 17 Hardware suggestion of 2 data lane serial interface

Command write mode:

SRAM write mode:

Read function:

3-line serial interface** Ⅰ**/**Ⅱ **protocol:

3-line Serial Protocol (for RDDST command: 32-bit read)

8.5 Data Transfer Break and Recovery

8.6 Data Transfer Pause

8.7 Data Transfer Mode

8.7.1 Method 1

8.7.2 Method 2

8.8 Data Color Coding

8.8.1 8080- series** Ⅰ **8-bit Parallel Interface

8.8.2 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah="03h"

8.8.4 8-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h"

8.8.5 8080- series** Ⅱ **8-bit Parallel Interface

8.8.8 8080- series 16** Ⅰ **-Bit Parallel Interface

8.8.11 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h",

MDT[1:0]="00b"

8.8.15 8080- series 16** Ⅱ **-Bit Parallel Interface

8.8.16 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input) 65K-Color, 3Ah="05h"

MDT[1:0]="00b"

8.8.19 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h",

Version 1.0 Page 84 of 317 2017/09

8.8.21 8080- series 9** Ⅰ **-Bit Parallel Interface

8.8.22 Write 9-bit data for RGB 5-6-5-bit input (65K-Color), 3Ah="05h"

8.8.25 8080- series 9** Ⅱ **-bit Parallel Interface

8.8.26 Write 9-bit data for RGB 5-6-5-bit input (65K-Color), 3Ah="05h"

8.8.29 8080- series 18** Ⅰ **-Bit Parallel Interface

8.8.33 8080- series 18** Ⅱ **-Bit Parallel Interface

8.8.36 3-Line Serial Interface

8.8.37 Write data for 12-bit/pixel (RGB-4-4-4 bit input), 4K-Colors, 3Ah="03h"

8.8.39 Write data for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah="06h"

8.8.40 4-Line Serial Interface

8.8.41 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah="03h"

8.9 RGB Interface

8.9.1 RGB interface Selection

8.9.2 RGB Color Format

8.9.3 RGB Interface Definition

Figure 24 DRAM Access Area by RGB Interface

8.9.4 RGB Interface Mode Selection

8.9.5 RGB Interface Timing

Figure 26 Timing chart of RGB interface HV mod

8.10 VSYNC Interface

8.10.1 18-bit RGB Interface

8.4.4 3-line serial interface / Ⅰ Ⅱ protocol

3-line serial interface Ⅰ/Ⅱ protocol:

8.8.1 8080- series Ⅰ 8-bit Parallel Interface

8.8.5 8080- series Ⅱ 8-bit Parallel Interface

8.8.8 8080- series 16 Ⅰ -Bit Parallel Interface

8.8.15 8080- series 16 Ⅱ -Bit Parallel Interface

8.8.21 8080- series 9 Ⅰ -Bit Parallel Interface

8.8.25 8080- series 9 Ⅱ -bit Parallel Interface

8.8.29 8080- series 18 Ⅰ -Bit Parallel Interface

8.8.33 8080- series 18 Ⅱ -Bit Parallel Interface