ST25DV04K-XX
Dynamic NFC/RFID tag ICThe ST25DV04K-XX is a dynamic nfc/rfid tag ic from STMicroelectronics. View the full ST25DV04K-XX datasheet below including electrical characteristics.
Manufacturer
STMicroelectronics
Category
Dynamic NFC/RFID tag IC
Overview
Part: ST25DVxxx Type: Dynamic NFC/RFID tag IC
Description: Dynamic NFC/RFID tag IC with 4-Kbit, 16-Kbit or 64-Kbit EEPROM, supporting ISO/IEC 15693 and NFC Forum Type 5 tag standards, featuring an I2C interface and Fast Transfer Mode capability.
Operating Conditions:
- Supply voltage: 1.8V to 5.5V
- Operating temperature: -40 to 85 °C
- I2C protocol speed: 1MHz
- RF fast read access: up to 53 Kbit/s
Key Specs:
- EEPROM memory sizes: 4-Kbit, 16-Kbit, 64-Kbit
- I2C interface speed: 1MHz
- RF fast read access speed: up to 53 Kbit/s
- Internal RF tuning capacitance: 28.5 pF
- Data retention: 40 years
- Write cycles endurance: 1 million at 25 °C, 600k at 85 °C
- Fast Transfer Mode buffer size: 256 bytes
- RF interface standard: ISO/IEC 15693 and NFC Forum Type 5 tag
Features:
- Two-wire I2C serial interface supports 1MHz protocol
- Multiple byte write programming (up to 256 bytes)
- Supports all ISO/IEC 15693 modulations, coding, subcarrier modes and data rates
- Single and multiple blocks write (up to 4) and read via RF
- Fast data transfer between I2C and RF interfaces
- Analog output pin for energy harvesting to power external components
- User memory: 1 to 4 configurable areas, protectable in read and/or write by three 64-bit RF passwords and one 64-bit I2C password
- System configuration: protected in write by 64-bit RF and I2C passwords
- GPO interruption pin configurable on multiple RF events
- Low power mode input pin
- RF command interpreter enabled/disabled from I2C host controller
Package:
- SO8N
- TSSOP8
- UFDFN8
- UFDFPN12
Features
ST25DVxxx offers the following features:
- A Fast Transfer Mode (FTM), to achieve a fast link between RF and contact worlds, via a 256 byte buffer called Mailbox. This mailbox dynamic buffer of 256 byte can be filled or emptied via either RF or I 2 C.
- A GPO pin, which indicates incoming event to the contact side, like RF Field changes, RF activity in progress, RF writing completion or Mailbox message availability.
- An Energy Harvesting element to deliver μW of power when external conditions make it possible.
- RF management, which allows ST25DVxxx to ignore RF requests.
All these features can be programmed by setting static and/or dynamic registers of the ST25DVxxx. ST25DVxxx can be partially customized using configuration registers located in the E 2 system area.
These registers are:
- dedicated to Data Memory organization and protection ENDA i , I2CSS, RFAiSS, LOCK_CCFILE.
- dedicated to Fast Transfer Mode MB_WDG, MB_MODE
- dedicated to observation, GPO, IT_TIME
- dedicated to RF , RF_MNGT, EH_MODE
- dedicated the device's structure LOCK_CFG
A set of additional registers allows to identify and customize the product (DSFID, AFI, IC_REF, etc.).
Electrical Characteristics
| Symbol | Parameter | Test condition | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| V IL | Input low voltage (SDA, SCL) | V CC = 1.8 V | - 0.45 | - | 0.25 V CC | V |
| V IL | Input low voltage (SDA, SCL) | V CC = 3.3 V | - 0.45 | - | 0.3 V CC | V |
| V IL | Input low voltage (SDA, SCL) | V CC = 5.5 V | - 0.45 | - | 0.3 V CC | V |
| V IL_LPD | Input low voltage (LPD) | V CC = 3.3 V | - 0.45 | - | 0.2 V CC | V |
| V IH | Input high voltage (SDA, SCL) | V CC = 1.8 V | 0.75 V CC | - | V CC + 1 | V |
| V IH | Input high voltage (SDA, SCL) | V CC = 3.3 V | 0.75 V CC | - | V CC + 1 | V |
| V IH | Input high voltage (SDA, SCL) | V CC = 5.5 V | 0.75 V CC | - | V CC + 1 | V |
| V IH _LPD | Input high voltage (LPD) | V CC = 1.8 V | 0.85 V CC | - | V CC + 1 | V |
| V IH _LPD | Input high voltage (LPD) | V CC = 3.3 V | 0.85 V CC | - | V CC + 1 | V |
| V IH _LPD | Input high voltage (LPD) | V CC = 5.5 V | 0.85 V CC | - | V CC + 1 | V |
| V OL _SDA | Output low voltage SDA (1 MHz) | I OL = 1 mA, V CC = 1.8 V | - | 0.05 | 0.4 | V |
| V OL _SDA | Output low voltage SDA (1 MHz) | I OL = 2.1 mA, V CC = 3.3 V | - | 0.075 | 0.4 | V |
| V OL _SDA | Output low voltage SDA (1 MHz) | I OL = 3 mA, V CC = 5.5 V | - | 0.09 | 0.4 | V |
| V CC _Power_up | Device Select Acknowledge | f C = 100 KHz | - | 1.48 | 1.7 | V |
210
Table 208. I 2 C AC characteristics
| Test conditions specified in Table 204 | Test conditions specified in Table 204 | Test conditions specified in Table 204 | Test conditions specified in Table 204 | Test conditions specified in Table 204 | Test conditions specified in Table 204 |
|---|---|---|---|---|---|
| Symbol | Alt. | Parameter | Min. | Max. | Unit |
| f C | f SCL | Clock frequency | 0.05 | 1000 | kHz |
| t CHCL | t HIGH | Clock pulse width high | 0.26 | 25000 (1) | μs |
| t CLCH | t LOW | Clock pulse width low | 0.5 | 25000 (2) | μs |
| t START_OUT | - | I²C timeout on Start condition | 35 | - | ms |
| t XH1XH2 | t R | Input signal rise time | (3) | (3) | ns |
| t XL1XL2 | t F | Input signal fall time | (3) | (3) | ns |
| t DL1DL2 (4) | t F | SDA (out) fall time | 20 | 120 | ns |
| t DXCX | t SU:DAT | Data in set up time | 0 | - | ns |
| t CLDX | t HD:DAT | Data in hold time | 0 | - | ns |
| t CLQX (5) | t DH | Data out hold time | 100 | - | ns |
| t CLQV (6) | t AA | Clock low to next data valid (access time) | - | 450 | ns |
| t CHDX (7) | t SU:STA | Start condition set up time | 250 | - | ns |
| t DLCL | t HD:STA | Start condition hold time | 0.25 | 35000 (8) | μs |
| t CHDH | t SU:STO | Stop condition set up time | 250 | - | ns |
| t DHDL | t BUF | Time between Stop condition and next Start condition | 500 | - | ns |
| t W | - | I²C write time | - | 5 | ms |
| t bootDC | - | RF OFF and LPD = 0 | - | 0.6 | ms |
| t bootLPD | - | RF OFF | - | 0.6 | ms |
- t CHCL timeout.
- t CLCH timeout.
- There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I 2 C specification that the input signal rise and fall times be less than 120 ns when f C < 1 MHz.
- Characterized on bench.
- To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
- t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V CC in a compatible way with the I 2 C specification (which specifies t SU:DAT (min) = 100 ns), assuming that the R bus × C bus time constant is less than 150 ns (as specified in the Figure 75: I 2 C Fast mode (f C = 1 MHz): maximum R bus value versus bus parasitic capacitance (C bus ) ).
- For a reStart condition, or following a write cycle.
- t DLCL timeout.
Figure 74. I 2 C AC waveforms
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Figure 75 indicates how the value of the pull-up resistor can be calculated. In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
Figure 75. I 2 C Fast mode (f C = 1 MHz): maximum R bus value versus bus parasitic capacitance (C bus )
Figure 75 indicates how the value of the pull-up resistor can be calculated. In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| ST25DV04K | STMicroelectronics | SO8N |
| ST25DV04K-IE | STMicroelectronics | — |
| ST25DV04K-JF | STMicroelectronics | — |
| ST25DV16K | STMicroelectronics | — |
| ST25DV64K | STMicroelectronics | — |
| ST25DVXXX | STMicroelectronics | — |
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