SPC560PXX

Part: SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 — STMicroelectronics

Type: 32-bit Power Architecture based Microcontroller (MCU)

Description: 32-bit Power Architecture based MCU operating at up to 64 MHz, with up to 256 KB Flash memory and 20 KB SRAM, designed for automotive chassis and safety applications.

Operating Conditions:

• Supply voltage: 3.0–5.5 V (for VDD_HV_IOx and VDD_HV_REG)
• Operating temperature: -40 to +125 °C (junction temperature)
• CPU performance: 0–64 MHz

Absolute Maximum Ratings:

• Max supply voltage: 6.0 V (for VDD_HV_IOx and VDD_HV_REG)
• Max junction/storage temperature: 150 °C (junction), 150 °C (storage)

Key Specs:

• CPU Core: 32-bit e200z0h Power Architecture
• Max CPU Frequency: 64 MHz
• Code Flash Memory: Up to 256 KB with ECC
• Data Flash Memory: 64 KB with ECC for EEPROM emulation
• SRAM: Up to 20 KB with ECC
• ADC: 10-bit, up to 16 input channels, < 1 μs conversion time
• LINFlex Channels: 2 (1x Master/Slave, 1x Master only)
• FlexCAN Interfaces: Up to 2 (2.0B Active) with 32 message buffers
• DSPI Channels: Up to 3 with automatic chip select generation

Features:

• Variable Length Encoding (VLE) instruction set
• Programmable watchdog timer, Non-maskable interrupt, Fault collection unit
• 16-channel eDMA controller
• Up to 25 external interrupts
• 1 FlexPWM unit with 8 outputs and ADC synchronization
• On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)
• On-chip voltage regulator (VREG)

Applications:

• Automotive chassis applications (electrical hydraulic power steering (EHPS), electric power steering (EPS))
• Airbag applications

Package:

• LQFP100 (14 x 14 x 1.4 mm)
• LQFP64 (10 x 10 x 1.4 mm)

• ■ Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h)
• -Compliant with Power Architecture ® embedded category
• -Variable Length Encoding (VLE)
• ■ Memory organization
• -Up to 256 KB on-chip code flash memory with ECC and erase/program controller
• -Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation
• -Up to 20 KB on-chip SRAM with ECC
• ■ Fail-safe protection
• -Programmable watchdog timer
• -Non-maskable interrupt
• -Fault collection unit
• ■ Nexus Class 1 interface
• ■ Interrupts and events
• -16-channel eDMA controller
• -16 priority level controller
• -Up to 25 external interrupts
• -PIT implements four 32-bit timers
• -120 interrupts are routed via INTC
• ■ General purpose I/Os
• -Individually programmable as input, output or special function
• -37 on LQFP64
• -64 on LQFP100
• ■ 1 general purpose eTimer unit
• -6 timers each with up/down capabilities
• -16-bit resolution, cascadable counters
• -Quadrature decode with rotation direction flag
• -Double buffer input capture and output compare

1

The following sections provide signal descriptions and related information about the functionality and configuration of the SPC560P34/SPC560P40 devices.

The internal voltage regulator requires an external NPN ballast, approved ballast list availbale in Table 15 , to be connected as shown in Figure 10 . Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the V DD_HV_REG , BCTRL and V DD_LV_CORx pins to less than L Reg . (refer to Table 16 ).

Note:

The voltage regulator output cannot be used to drive external circuits. Output pins are to be used only for decoupling capacitance.

VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is not possible to provide V DD_LV_COR through external regulator.

For the SPC560P34/SPC560P40 microcontroller, capacitor(s), with total values not below CDEC1 , should be placed between V DD_LV_CORx /V SS_LV_CORx close to external ballast transistor emitter. 4 capacitors, with total values not below C DEC2 , should be placed close to microcontroller pins between each V DD_LV_CORx /V SS_LV_CORx supply pairs and the VDD_LV_REGCOR /V SS_LV_REGCOR pair . Additionally, capacitor(s) with total values not below CDEC3 , should be placed between the V DD_HV_REG /V SS_HV_REG pins close to ballast collector. Capacitors values have to take into account capacitor accuracy, aging and variation versus temperature.

All reported information are valid for voltage and temperature ranges described in recommended operating condition, Table 10 and Table 11 .

Figure 10. Voltage regulator configuration

Table 15. Approved NPN ballast components

Table 15. Approved NPN ballast components

Table 15. Approved NPN ballast components

Table 16. Voltage regulator electrical characteristics

Table 16. Voltage regulator electrical characteristics

Table 9. Absolute maximum ratings (1) (continued)

1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device.
2. Absolute maximum voltages are currently maximum burn-in voltages.
3. The difference between each couple of voltage supplies must be less than 300 mV, VDD_HV_IOy - V DD_HV_IOx < 300 mV.
4. Guaranteed by device validation.
5. Minimum value of TV DD must be guaranteed until V DD_HV_REG reaches 2.6 V (maximum value of V PORH )
6. Only when V DD_HV_IOx < 5.2 V

Figure 6 shows the constraints of the different power supplies.

Figure 6. Power supplies constraints (-0.3 V ≤ VDD_HV_IOx ≤ 6.0 V)

The SPC560P34/SPC560P40 supply architecture allows the ADC supply to be managed independently from the standard V DD_HV supply. Figure 7 shows the constraints of the ADC power supply.

Figure 6. Power supplies constraints (-0.3 V ≤ VDD_HV_IOx ≤ 6.0 V)

Figure 7. Independent ADC supply (-0.3 V ≤ VDD_HV_REG ≤ 6.0 V)

Figure 7. Independent ADC supply (-0.3 V ≤ VDD_HV_REG ≤ 6.0 V)

Table 10. Recommended operating conditions (5.0 V)

Table 10. Recommended operating conditions (5.0 V)

Table 10. Recommended operating conditions (5.0 V) (continued)

1. The difference between each couple of voltage supplies must be less than 100 mV, VDD_HV_IOy -VDD_HV_IOx < 100 mV.
2. To be connected to emitter of external NPN. Low voltage supplies are not under user control-they are produced by an onchip voltage regulator-but for the device to function properly the low voltage grounds (V SS_LV_xxx ) must be shorted to high voltage grounds (V SS_HV_xxx ) and the low voltage supply pins (V DD_LV_xxx ) must be connected to the external ballast emitter.
4. The low voltage supplies (V DD_LV_xxx ) are not all independent. - V DD_LV_COR1 and V DD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low voltage supply to the data flash memory module. Similarly, V SS_LV_COR1 and V SS_LV_COR2 are internally shorted. - V DD_LV_REGCOR and V DD_LV_RECORx are physically shorted internally, as are V SS_LV_REGCOR and V SS_LV_CORx .

Table 11. Recommended operating conditions (3.3 V)

Table 11. Recommended operating conditions (3.3 V)

Table 11. Recommended operating conditions (3.3 V) (continued)

1. The difference between each couple of voltage supplies must be less than 100 mV, VDD_HV_IOy -VDD_HV_IOx < 100 mV.
2. To be connected to emitter of external NPN. Low voltage supplies are not under user control-they are produced by an onchip voltage regulator-but for the device to function properly the low voltage grounds (V SS_LV_xxx ) must be shorted to high voltage grounds (V SS_HV_xxx ) and the low voltage supply pins (V DD_LV_xxx ) must be connected to the external ballast emitter.
3. The low voltage supplies (V DD_LV_xxx ) are not all independent.

• V DD_LV_COR1 and V DD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low voltage supply to the data flash memory module. Similarly, V SS_LV_COR1 and V SS_LV_COR2 are internally shorted.
• V DD_LV_REGCOR and V DD_LV_RECORx are physically shorted internally, as are V SS_LV_REGCOR and V SS_LV_CORx .

Figure 8 shows the constraints of the different power supplies.

Figure 8. Power supplies constraints (3.0 V ≤ VDD_HV_IOx ≤ 5.5 V)

The SPC560P34/SPC560P40 supply architecture allows the ADC supply to be managed independently from the standard V DD_HV supply. Figure 9 shows the constraints of the ADC power supply.

Figure 9. Independent ADC supply (3.0 V ≤ VDD_HV_REG ≤ 5.5 V)

Figure 8. Power supplies constraints (3.0 V ≤ VDD_HV_IOx ≤ 5.5 V)

Figure 9. Independent ADC supply (3.0 V ≤ VDD_HV_REG ≤ 5.5 V)

1. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB or Theta-JB.
2. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
3. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
4. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JC.