SP233A

Part: SP232A/233A/310A/312A from Sipex

Type: Enhanced RS-232 Line Drivers/Receivers

Key Specs:

• Supply Voltage: +5V
• Max Data Rate: 240 Kbps
• Low Power Operation: 3mA (SP232A, no load)
• ESD Protection: 2kV Human Body Model
• Charge Pump Capacitor Range: 0.1μF to 1μF
• RS-232 Output Voltage Swing: ±5V (under load)
• RS-232 Input Voltage Range: ±30V

Features:

• Operates from Single +5V Power Supply
• Meets All RS-232F and ITU V.28 Specifications
• Operates with 0.1μF to 1μF Capacitors (SP232A, SP310A, SP312A)
• No External Capacitors Required (SP233A)
• High Data Rate 120Kbps Under Load
• Low Power CMOS 3mA Operation (SP232A)
• Low Power Shutdown (SP310A, SP312A)
• Enhanced ESD Protection (2kV Human Body Model)
• Pin-to-pin compatible with popular industry standards
• BiCMOS design for low power operation
• Internal charge pump voltage converters
• Transmitter outputs protected against infinite short-circuits to ground
• Receiver inputs protected against voltages up to ±25V
• Receiver inputs with hysteresis for noise immunity

Applications:

• Commercial applications

Package:

• Plastic DIP: null
• SOIC: null

• Operates from Single +5V Power Supply
• Meets All RS-232F and ITU V.28 Specifications

Solved by

• Operates with 0.1μF to 1μF Capacitors
• High Data Rate 120Kbps Under Load
• Low Power CMOS 3mA Operation (SP232A)
• No External Capacitors Required (SP233A)
• Low Power Shutdown (SP310A,SP312A)
• Enhanced ESD Protection (2kV Human Body Model)

Now Available in Lead Free Packaging

PARAMETERS MIN. TYP. MAX. UNITS CONDITIONS TTL INPUT Logic Threshold LOW 0.8 Volts TIN; EN, SD HIGH 2.0 Volts TIN; EN, SD Logic Pull-Up Current 15 200 μA TIN= ZeroV TTL OUTPUT TTL/CMOS Output Voltage, Low 0.4 Volts ^I OUT= 3.2mA; Vcc = +5V Voltage, High 3.5 Volts IOUT= -1.0mA Leakage Current; TA= +25 ° 0.05 ±10 μA EN= V CC, ZeroV)VOUT )VCC SP310A and SP312A only RS-232 OUTPUT Output Voltage Swing ±5 ±6 Volts All transmitter outputs loaded with 3k1to Ground Output Resistance 300 Ohms VCC= ZeroV; V OUT= ±2V Output Short Circuit Current ±18 mA Infinite duration Maximum Data Rate 120 240 Kbps CL = 2500pF, R ^L = 3k1 RS-232 INPUT Voltage Range -30 +30 Volts Voltage Threshold LOW 0.8 1.2 Volts VCC= 5V, T A= +25 °C HIGH 1.7 2.4 Volts VCC= 5V, T A= +25 °C Hysteresis 0.2 0.5 1.0 Volts VCC= 5V, T A= +25 °C Resistance 3 5 7 k1 TA= +25 °C, -15V )V IN )+15V DYNAMIC CHARACTERISTICS Driver Propagation Delay 1.5 3.0 μs TTL to RS-232; CL = 50pF Receiver Propagation Delay 0.1 1.0 μs RS-232 to TTL Instantaneous Slew Rate 30 V/μs CL = 10pF, R ^L= 3-7k1; TA=+25 °C Transition Region Slew Rate 10 V/μs CL = 2500pF, R ^L = 3k1; measured from +3V to -3V or -3V to +3V Output Enable Time 400 ns SP310A and SP312A only Output Disable Time 250 ns SP310A and SP312A only POWER REQUIREMENTS VCCPower Supply Current SP232A 3 5 mA No load, TA= +25°C; VCC= 5V SP233A, SP310A, SP312A 10 15 mA No load, TA= +25°C; VCC= 5V VCCSupply Current,Loaded SP232A 15 mA All transmitters RL = 3k 1; TA = +25 °C SP233A, SP310A, SP312A 25 mA All transmitters RL= 3k 1; TA = +25 °C Shutdown Supply Current SP310A,SP312A 1 10 μA VCC= 5V, T A= +25 °C

FEATURES…

The SP232A/233A/310A/312A devices are a family of line driver and receiver pairs that meet the specifications of RS-232 and V.28 serial protocols. The ESD tolerance has been improved on these devices to over ±2KV for the Human Body Model. These devices are pin-topin compatible with popular industry standards. The SP232A/233A/310A/312A devices feature10V/μs slew rate, 120Kbps data rate under load, 0.1μF charge pump capacitors, overall ruggedness for commercial applications, and increased drive current for longer and more flexible cable configurations. This family also features Sipex's BiCMOS design allowing low power operation without sacrificing performance.

The SP232A/233A/310A/312A devices have internal charge pump voltage converters which allow them to operate from a single +5V supply. The charge pumps will operate with polarized or non-polarized capacitors ranging from 0.1 to 1μF and will generate the ±6V needed for the RS-232 output levels. Both meet all EIA RS-232F and ITU V.28 specifications.

The SP310A provides identical features as the SP232A with the addition of a single control line which simultaneously shuts down the internal DC/DC converter and puts all transmitter and receiver outputs into a high impedance state. The SP312A is identical to the SP310A with separate tri-state and shutdown control lines.

THEORY OF OPERATION

The SP232A, SP233A, SP310A and SP312A devices are made up of three basic circuit blocks – 1) a driver/transmitter, 2) a receiver and 3) a charge pump. Each block is described below.

Driver/Transmitter

The drivers are inverting transmitters, which accept TTL or CMOS inputs and output the RS-232 signals with an inverted sense relative to the input logic levels. Typically the RS-232output voltage swing is ±6V. Even under worst case loading conditions of 3kOhms and 2500pF, the output is guaranteed to be ±5V, which is consistent with the RS-232 standard specifications. The transmitter outputs are protected against infinite short-circuits to ground without degradation in reliability.

Figure 1. Typical Circuit using the SP232A.

Figure 2. Typical Circuits using the SP233ACP and SP233ACT

The instantaneous slew rate of the transmitter output is internally limited to a maximum of 30V/ μs in order to meet the standards [EIA RS-232-F ]. The transition region slew rate of these enhanced products is typically 10V/μs. The smooth transition of the loaded output from VOL to VOH clearly meets the monotonicity requirements of the standard [EIA RS-232-F].

Receivers

The receivers convert RS-232 input signals to inverted TTL signals. Since the input is usually from a transmission line, where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is virtually immune to noisy transmission lines.

The input thresholds are 0.8V minimum and 2.4V maximum, again well within the ±3V RS-232 requirements. The receiver inputs are also protected against voltages up to ±25V. Should an input be left unconnected, a 5K1 pulldown resistor to ground will commit the output of the receiver to a high state.

Figure 3. Typical Circuits using the SP310A and SP312A

Figure 4. Charge Pump — Phase 1

In actual system applications, it is quite possible for signals to be applied to the receiver inputs before power is applied to the receiver circuitry. This occurs, for example, when a PC user attempts to print, only to realize the printer wasn't turned on. In this case an RS-232 signal from the PC will appear on the receiver input at the printer. When the printer power is turned on, the receiver will operate normally. All of these enhanced devices are fully protected.

Charge Pump

The charge pump is a Sipex–patented design (5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical power supplies. There is a free–running oscillator that controls the four phases of the voltage shifting. A description of each phase follows.

Phase 1

— VSS charge storage —During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to +5V. Cl + is then switched to ground and the charge in C1 – is transferred to C2 –. Since C2 + is connected to +5V, the voltage potential across capacitor C2 is now 10V.

Phase 2

— VSStransfer — Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to ground, and transfers the generated –l0V to C3. Simultaneously, the positive side of capacitor C 1 is switched to +5V and the negative side is connected to ground.

Phase 3

— VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1produces –5V in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2 + is at +5V, the voltage potential across C2 is a maximum of l0V.

Phase 4

— VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers the generated l0V across C2 to C4, the VDD storage capacitor. Again, simultaneously with this, the positive side of capacitor C1 is switched to +5V and the negative side is connected to ground, and the cycle begins again.

Since both V+ and V– are separately generated from VCC; in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches

Figure 5. Charge Pump — Phase 2

Figure 6. Charge Pump Waveforms

that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

The clock rate for the charge pump typically operates at greater than 15kHz. The external capacitors can be as low as 0.1μF with a 10V breakdown voltage rating.

Shutdown (SD) and Enable (EN) for the SP310A and SP312A

Both the SP310A and SP312A have a shutdown/ standby mode to conserve power in battery-powered systems. To activate the shutdown mode, which stops the operation of the charge pump, a logic "0" is applied to the appropriate control line. For the SP310A, this control line is ON/OFF (pin 18). Activating the shutdown mode also puts the

Figure 7. Charge Pump — Phase 3

Figure 8. Charge Pump — Phase 4

SP310A transmitter and receiver outputs in a high impedance condition (tri-stated). The shutdown mode is controlled on the SP312A by a logic "0" on the SHUTDOWN control line (pin 18); this also puts the transmitter outputs in a tri–state mode. The receiver outputs can be tri–stated separately during normal operation or shutdown by a logic "1" on the ENABLE line (pin 1).

Wake–Up Feature for the SP312A

The SP312A has a wake–up feature that keeps all the receivers in an enabled state when the device is in the shutdown mode. Table 1 defines the truth table for the wake–up function.

With only the receivers activated, the SP312A typically draws less than 5μA supply current. In the case of a modem interfaced to a computer in power down mode, the Ring Indicator (RI) signal from the modem would be used to "wake up" the computer, allowing it to accept data transmission.

After the ring indicator signal has propagated through the SP312A receiver, it can be used to trigger the power management circuitry of the computer to power up the microprocessor, and bring the SD pin of the SP312A to a logic high, taking it out of the shutdown mode. The receiver propagation delay is typically 1μs. The enable time for V+ and V– is typically 2ms. After V+ and V– have settled to their final values, a signal can be sent back to the modem on the data terminal ready (DTR) pin signifying that the computer is ready to accept and transmit data.

Table 1. Wake-up Function Truth Table.

• TOUT (V+, +0.3V) to (V-, -0.3V)
• ROUT -0.3V to (Vcc +0.3V)
• Short Circuit Duration
• TOUT Continuous
• Plastic DIP 375mW
• (derate 7mW/°C above +70°C)
• Small Outline 375mW
• (derate 7mW/°C above +70°C)