SN6505BDBVT
The SN6505BDBVT is an electronic component from Texas Instruments. View the full SN6505BDBVT datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
Manufacturer
Texas Instruments
Category
Power Management Specialised - PMIC
Key Specifications
| Parameter | Value |
|---|---|
| Packaging | MouseReel |
| Standard Pack Qty | 250 |
Overview
When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse. Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2 is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2, charging the capacitor and returning through the load to the center-tap.
Pin Configuration
Pin Functions
Pin Functions
| PIN | PIN | PIN | DESCRIPTION |
|---|---|---|---|
| NAME | NO. | TYPE | DESCRIPTION |
| D1 | 1 | O | Open drain output of the first power MOSFETs. Typically connected to the outer terminals of the center tap transformer. Because large currents flow through these pins, their external traces should be kept short. |
| V CC | 2 | P | This is the device supply pin. It should be bypassed with a 4.7 μ F or greater, low ESR capacitor. When V CC ≤ 2.25 V, an internal undervoltage lockout circuit trips and turns both outputs off. |
| D2 | 3 | O | Open drain output of the second power MOSFETs. Typically connected to the outer terminals of the center tap transformer. Because large currents flow through these pins, their external traces should be kept short. |
| GND | 4 | P | GND is connected to the source of the power MOSFET switches via an internal sense circuit. Because large currents flow through it, the GND terminals must be connected to a low-inductance quality ground plane. |
| EN | 5 | I | The EN pin turns the device on or off. Grounding or leaving this pin floating disables all internal circuitry. If unused this pin should be tied directly to V CC . |
| CLK | 6 | I | This pin is used to run the SN6505 with external clock. Internally it is pulled down to GND . If valid clock is not detected on this pin, the SN6505 shifts automatically to internal clock. |
Electrical Characteristics
over full-range of recommended operating conditions, unless otherwise noted. All typical values are at TA = 25°C, VCC = 5 V.
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| VOLTAGE SUPPLY | VOLTAGE SUPPLY | VOLTAGE SUPPLY | VOLTAGE SUPPLY | VOLTAGE SUPPLY | VOLTAGE SUPPLY | VOLTAGE SUPPLY |
| I (VCC) | Supply Current (2.8 V < VC C < 5.5) (SN6505A) | R L = 50 Ω | 1 | 1.4 | mA | |
| I (VCC) | Supply Current (2.8 V < VC C < 5.5) (SN6505B) | 1.56 | 2.3 | mA | ||
| I IH | Leakage Current on EN and CLK pin | EN / CLK = V CC | 10 | 20 | μA | |
| I DIS | V CC current for EN = 0 | 0.1 | μA | |||
| I LKG(D1) I LKG(D2) | Leakage Current on D1,D2 for EN=0 | Voltage of D1,D2 = V CC | 0.1 | μA | ||
| V CC+ (UVLO) | Positive-going UVLO threshold | 2.25 | V | |||
| V CC- (UVLO) | Negative-going UVLO threshold | 1.7 | V | |||
| V HYS (UVLO1) | UVLO threshold hysteresis | 0.3 | V | |||
| V IN(ON) | EN, CLK pin logic high threshold | 0.7 | V CC | |||
| V IN(OFF) | EN, CLK pin logic low threshold | 0.3 | V CC | |||
| V IN(HYS) | EN, CLK pin threshold hysteresis | 0.2 | V CC | |||
| CLK | CLK | CLK | CLK | CLK | CLK | CLK |
| F SW | D1, D2 average switching Frequency (SN6505A) | R L = 50 Ω to V CC ; Refer to Figure 12 | 138 | 160 | 203 | Khz |
| F SW | D1, D2 average switching Frequency (SN6505B) | R L = 50 Ω to V CC ; Refer to Figure 12. | 363 | 424 | 517 | kHz |
| F (EXT) | External clock frequency on CLK pin (SN6505A) | 100 | 600 | kHz | ||
| F (EXT) | External clock frequency on CLK pin (SN6505B) | 100 | 1600 | kHz | ||
| OUTPUT STAGE | OUTPUT STAGE | OUTPUT STAGE | OUTPUT STAGE | OUTPUT STAGE | OUTPUT STAGE | OUTPUT STAGE |
| DMM | Average ON time mismatch between D1 and D2 | R L = 50 Ω | 0% | |||
| R (ON) | Output switch on resistance | V CC = 4.5 V, ID1,ID2 = 1 A | 0.16 | 0.25 | Ω | |
| V CC = 2.8 V, ID1,ID2 = 1 A | 0.19 | 0.31 | Ω | |||
| V CC = 2.25 V, ID1,ID2 = 0.5 A | 0.21 | 0.45 | Ω |
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) .All typical values are at TA = 25°C, VCC = 5 V.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage (2) | V CC | -0.5 | 6 | V |
| Voltage | EN, CLK | -0.5 | V CC + 0.5 (3) | |
| Output switch voltage | D1, D2 | 16 | V | |
| Peak output switch current | I (D1)Pk , I (D2)Pk | 2.4 | A | |
| Junction temperature, T J | Junction temperature, T J | -55 | 150 | °C |
| Storage temperature range, T stg | Storage temperature range, T stg | -65 | 150 | °C |
- (2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND) and are peak voltage values.
(3) Maximum voltage of 6V.
Recommended Operating Conditions
| MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| V CC | Supply voltage | 2.25 | 5.5 | V | ||
| I D1 , I D2 | Output switch current - Primary side | 2.25 V < V CC < 2.8 V | 0.75 | A | ||
| Ambient temperature | 2.8 V < V CC < 5.5 V | 1 | A | |||
| T A | -55 | 125 | °C |
Thermal Information
| THERMAL METRIC (1) | THERMAL METRIC (1) | DW (SOIC) 16 PINS | UNIT |
|---|---|---|---|
| R θ JA | Junction-to-ambient thermal resistance | 137.7 | °C/W |
| R θ JC(top) | Junction-to-case (top) thermal resistance | 57.7 | °C/W |
| R θ JB | Junction-to-board thermal resistance | 46.0 | °C/W |
| ψ JT | Junction-to-top characterization parameter | 13.4 | °C/W |
| ψ JB | Junction-to-board characterization parameter | 44.9 | °C/W |
| R θ JC(bottom) | Junction-to-case(bottom) thermal resistance | N/A | °C/W |
Typical Application
The SN6505 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive, comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output signals which alternately turn the two output transistors on and off.
Figure 16. SN6505 Block Diagram And Output Timing With Break-Before-Make Action
The output frequency of the oscillator is divided down by an asynchronous divider that provides two complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gatedrive signals for the output transistors Q1 and Q2. As shown in Figure 17, before either one of the gates can assume logic high, there must be a short time period during which both signals are low and both transistors are high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of the primary.
Figure 17. Detailed Output Signal Waveforms
Figure 16. SN6505 Block Diagram And Output Timing With Break-Before-Make Action
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| SN6505 | Texas Instruments | — |
| SN6505A | Texas Instruments | — |
| SN6505ADBVR | Texas Instruments | — |
| SN6505ADBVT | Texas Instruments | — |
| SN6505B | Texas Instruments | — |
| SN6505BDBVR | Texas Instruments | SOT-23-6 |
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