RA4M1 GROUP
32-bit ARM Cortex-M4 MCUThe RA4M1 GROUP is a 32-bit arm cortex-m4 mcu from Renesas Electronics Corp.. View the full RA4M1 GROUP datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
Renesas Electronics Corp.
Category
32-bit ARM Cortex-M4 MCU
Overview
Part: RA4M1 Group — Renesas Electronics Corp.
Type: 32-bit ARM Cortex-M4 MCU
Description: High efficiency 48-MHz Arm Cortex-M4 core with FPU, 256-KB code flash memory, 32-KB SRAM, Segment LCD Controller, Capacitive Touch Sensing Unit, USB 2.0 Full-Speed Module, 14-bit A/D Converter, 12-bit D/A Converter, and security/safety features.
Operating Conditions:
- Supply voltage: 1.6 to 5.5 V
- Operating temperature: -40 to +85 °C (suffix-dependent — see "Operating Temperature and Packages" for grade-specific ranges)
- Max operating frequency: 48 MHz
Absolute Maximum Ratings:
Key Specs:
- Core: Arm Cortex-M4 with FPU
- Max CPU frequency: 48 MHz
- Code Flash Memory: 256 KB
- Data Flash Memory: 8 KB (100,000 P/E cycles)
- SRAM: 32 KB
- A/D Converter: 14-bit, up to 25 channels
- D/A Converter: 12-bit (1 channel), 8-bit (2 channels)
- GPIO pins: Up to 84
Features:
- Arm Memory Protection Unit (MPU) with 8 regions
- USB 2.0 Full-Speed Module (USBFS) with on-chip transceiver
- Serial Communications Interface (SCI) × 4 (UART, Simple IIC, Simple SPI, Smart card interface)
- Serial Peripheral Interface (SPI) × 2
- I2C bus interface (IIC) × 2
- Serial Sound Interface Enhanced (SSIE)
- Controller Area Network (CAN) module
- Segment LCD Controller (SLCDC)
- Capacitive Touch Sensing Unit (CTSU)
- Realtime Clock (RTC) with calendar and Battery Backup support
- True Random Number Generator (TRNG)
- AES128/256 encryption
- SRAM parity error check and ECC
- Low power modes
Applications:
Package:
- 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch)
- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
- 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch)
- 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch)
- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)
- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)
Pin Configuration
Table 1.14 Pin functions (1 of 4)
| Function | Signal | I/O | Description |
|---|---|---|---|
| Power supply | VCC | Input | Power supply pin. Connect this pin to the system power supply. Connect it to VSS through a 0.1-μF capacitor. The capacitor should be placed close to the pin. |
| Power supply | VCL | I/O | Connect this pin to the VSS pin through the smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. |
| Power supply | VSS | Input | Ground pin. Connect to the system power supply (0 V). |
| Power supply | VBATT | Input | Backup power supply pin |
| Clock | XTAL | Output | Pins for a crystal resonator. An external clock signal can be input through the |
| Clock | EXTAL | Input | EXTAL pin. |
| Clock | XCIN | Input | Input/output pins for the sub-clock oscillator. Connect a crystal resonator |
| Clock | XCOUT | Output | between XCOUT and XCIN. |
| Clock | CLKOUT | Output | Clock output pin |
| Operating mode control | MD | Input | Pins for setting the operating mode. The signal levels on these pins must not be changed during operation mode transition on release from the reset state. |
| System control | RES | Input | Reset signal input pin. The MCU enters the reset state when this signal goes low. |
| CAC | CACREF | Input | Measurement reference clock input pin |
| Interrupt | NMI | Input | Non-maskable interrupt request pin |
| Interrupt | IRQ0 to IRQ12, IRQ14, IRQ15 | Input | Maskable interrupt request pins |
| KINT | KR00 to KR07 | Input | Key interrupt input pins. A key interrupt (KINT) can be generated by inputting a falling edge to the key interrupt input pins. |
| On-chip debug | TMS | I/O | On-chip emulator or boundary scan pins |
| On-chip debug | TDI | Input | |
| On-chip debug | TCK | Input | |
| On-chip debug | TDO | Output | |
| On-chip debug | SWDIO | I/O | Serial wire debug data input/output pin |
| On-chip debug | SWCLK | Input | Serial wire clock pin |
| On-chip debug | SWO | Output | Serial wire trace output pin |
| Battery Backup | VBATWIO0 to VBATWIO2 | I/O | Output wakeup signal for the VBATT wakeup control function. External event input for the VBATT wakeup control function. |
| GPT | GTETRGA, GTETRGB | Input | External trigger input pin |
| GPT | GTIOC0A to GTIOC7A, GTIOC0B to GTIOC7B | I/O | Input capture, output capture, or PWM output pin |
| GPT | GTIU | Input | Hall sensor input pin U |
| GPT | GTIV | Input | Hall sensor input pin V |
| GPT | GTIW | Input | Hall sensor input pinW |
| GPT | GTOUUP | Output | 3-phase PWM output for BLDC motor control (positive U phase) |
| GPT | GTOULO | Output | 3-phase PWM output for BLDC motor control (negative U phase) |
| GPT | GTOVUP | Output | 3-phase PWM output for BLDC motor control (positive V phase) |
| GPT | GTOVLO | Output | 3-phase PWM output for BLDC motor control (negative V phase) |
| GPT | GTOWUP | Output | 3-phase PWM output for BLDC motor control (positive Wphase) |
| GPT | GTOWLO | Output | 3-phase PWM output for BLDC motor control (negative Wphase) |
Table 1.14 Pin functions (1 of 4)
| Table 1.14 | Pin functions (2 of 4) | Pin functions (2 of 4) | Pin functions (2 of 4) |
|---|---|---|---|
| Function | Signal | I/O | Description |
| AGT | AGTEE0, AGTEE1 | Input | External event input enable signals |
| AGT | AGTIO0, AGTIO1 | I/O | External event input and pulse output pins |
| AGT | AGTO0, AGTO1 | Output | Pulse output pins |
| AGT | AGTOA0, AGTOA1 | Output | Output compare match A output pins |
| AGT | AGTOB0, AGTOB1 | Output | Output compare match B output pins |
| RTC | RTCOUT | Output | Output pin for 1-Hz/64-Hz clock |
| RTC | RTCIC0 to RTCIC2 | Input | Time capture event input pins |
| SCI | SCK0 to SCK2, SCK9 | I/O | Clock (clock synchronous mode) input/output pins |
| SCI | RXD0 to RXD2, RXD9 | Input | Received data (asynchronous mode/clock synchronous mode) input pins |
| SCI | TXD0 to TXD2, TXD9 | Output | Transmitted data (asynchronous mode/clock synchronous mode) output pins |
| SCI | CTS0_RTS0 to CTS2_RTS2, CTS9_RTS9 | I/O | Input/output pins for controlling the start of transmission and reception (asynchronous mode/clock synchronous mode), active-low |
| SCI | SCL0 to SCL2, SCL9 | I/O | I 2 C clock (simple IIC) input/output pins |
| SCI | SDA0 to SDA2, SDA9 | I/O | I 2 C data (simple IIC) input/output pins |
| SCI | SCK0 to SCK2, SCK9 | I/O | Clock (simple SPI) input/output pins |
| SCI | MISO0 to MISO2, MISO9 | I/O | Slave transmission of data (simple SPI) input/output pins |
| SCI | MOSI0 to MOSI2, MOSI9 | I/O | Master transmission of data (simple SPI) input/output pins |
| SCI | SS0 to SS2, SS9 | Input | Slave-select input pins (simple SPI), active-low |
| IIC | SCL0, SCL1 | I/O | Clock input/output pins |
| IIC | SDA0, SDA1 | I/O | Data input/output pins |
| SSIE | SSIBCK0 | I/O | SSIE serial bit clock pin |
| SSIE | SSILRCK0/SSIFS0 | I/O | Word select pins |
| SSIE | SSITXD0 | Output | Serial data output pin |
| SSIE | SSIRXD0 | Input | Serial data input pin |
| SSIE | AUDIO_CLK | Input | External clock pin for audio (input oversampling clock) |
| SPI | RSPCKA, RSPCKB | I/O | Clock input/output pin |
| SPI | MOSIA, MOSIB | I/O | Input/output pins for data output from the master |
| SPI | MISOA, MISOB | I/O | Input/output pins for data output from the slave |
| SPI | SSLA0, SSLB0 | I/O | Input/output pins for slave selection |
| SPI | SSLA1, SSLA2, SSLA3, SSLB1, SSLB2, SSLB3 | Output | Output pins for slave selection |
| CAN | CRX0 | Input | Receive data |
| CAN | CTX0 | Output | Transmit data |
Table 1.14 Pin functions (3 of 4)
| Function | Signal | I/O | Description |
|---|---|---|---|
| USBFS | VSS_USB | Input | Ground pin |
| USBFS | VCC_USB_LDO | Input | Power supply pin for USB LDO regulator |
| USBFS | VCC_USB | I/O | Input: USB transceiver power supply pin. Output: USB LDO regulator output pin. This pin should be connected to an external capacitor. |
| USBFS | USB_DP | I/O | D+ I/O pin of the USB on-chip transceiver. This pin should be connected to the D+ pin of the USB bus. |
| USBFS | USB_DM | I/O | D- I/O pin of the USB on-chip transceiver. This pin should be connected to the D- pin of the USB bus. |
| USBFS | USB_VBUS | Input | USB cable connection monitor pin. This pin should be connected to VBUS of the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a device controller. |
| USBFS | USB_EXICEN | Output | Low power control signal for external power supply (OTG) chip |
| USBFS | USB_VBUSEN | Output | VBUS (5 V) supply enable signal for external power supply chip |
| USBFS | USB_OVRCURA, USB_OVRCURB | Input | Connect the external overcurrent detection signals to these pins. Connect the VBUS comparator signals to these pins when the OTG power supply chip is connected. |
| USBFS | USB_ID | Input | Connect the MicroAB connector ID input signal to this pin during operation in OTG mode |
| Analog power supply | AVCC0 | Input | Analog voltage supply pin |
| Analog power supply | AVSS0 | Input | Analog voltage supply ground pin |
| Analog power supply | VREFH0 | Input | Analog reference voltage supply pin |
| Analog power supply | VREFL0 | Input | Reference power supply ground pin |
| Analog power supply | VREFH | Input | Analog reference voltage supply pin for D/A converter |
| Analog power supply | VREFL | Input | Analog reference ground pin for D/A converter |
| ADC14 | AN000 to AN014, AN016 to AN025 | Input | Input pins for the analog signals to be processed by the A/D converter |
| ADC14 | ADTRG0 | Input | Input pins for the external trigger signals that start the A/D conversion, active- low |
| DAC12 | DA0 | Output | Output pins for the analog signals to be processed by the D/A converter |
| Comparator output | VCOUT | Output | Comparator output pin |
| ACMPLP | CMPREF0, CMPREF1 | Input | Reference voltage input pin |
| ACMPLP | CMPIN0, CMPIN1 | Input | Analog voltage input pins |
| OPAMP | AMP0+ to AMP3+ | Input | Analog voltage input pins |
| OPAMP | AMP0- to AMP3- | Input | Analog voltage input pins |
| OPAMP | AMP0O to AMP3O | Output | Analog voltage output pins |
| CTSU | TS00 to TS13, TS17 to TS22, TS27 to TS31, TS34, TS35 | Input | Capacitive touch detection pins (touch pins) |
| CTSU | TSCAP | - | Secondary power supply pin for the touch driver |
Table 1.14 Pin functions (3 of 4)
| Signal | I/O | Description | |
|---|---|---|---|
| I/O ports Function | P000 to P008, P010 to P015 | I/O | General-purpose input/output pins |
| I/O ports Function | P100 to P115 | I/O | General-purpose input/output pins |
| I/O ports Function | P200 | Input | General-purpose input pin |
| I/O ports Function | P201 to P206, P212, P213 | I/O | General-purpose input/output pins |
| I/O ports Function | P214, P215 | Input | General-purpose input pins |
| I/O ports Function | P300 to P307 | I/O | General-purpose input/output pins |
| I/O ports Function | P400 to P415 | I/O | General-purpose input/output pins |
| I/O ports Function | P500 to P505 | I/O | General-purpose input/output pins |
| I/O ports Function | P600 to P603, P608 to P610 | I/O | General-purpose input/output pins |
| I/O ports Function | P708 | I/O | General-purpose input/output pins |
| I/O ports Function | P808, P809 | I/O | General-purpose input/output pins |
| I/O ports Function | P914, P915 | I/O | General-purpose input/output pins |
| SLCDC | VL1, VL2, VL3, VL4 | I/O | Voltage pin for driving the LCD |
| SLCDC | CAPH, CAPL | I/O | Capacitor connection pin for the LCD controller/driver |
| SLCDC | COM0 to COM7 | Output | Common signal output pins for the LCD controller/driver |
| SLCDC | SEG00 to SEG37 | Output | Segment signal output pins for the LCD controller/driver |
Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC * 1 = AVCC0 = VCC_USB * 2 = VCC_USB_LDO * 2 = 1.6 to 5.5V, VREFH = VREFH0 = 1.6 to AVCC0, VBATT = 1.6 to 3.6V, VSS = AVSS0 = VREFL = VREFL0 = VSS_USB = 0V, T a = T opr .
Note 1. The typical condition is set to VCC = 3.3V.
Note 2. When USBFS is not used.
Figure 2.1 shows the timing conditions.
Figure 2.1 Input or output timing measurement conditions
The recommended measurement conditions for the timing specification of each peripheral provided are for the best peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.
Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function pin is mixed, the AC specification of each function is not guaranteed.
Absolute Maximum Ratings
Table 2.1 Absolute maximum ratings
| Parameter | Parameter | Symbol | Value | Unit |
|---|---|---|---|---|
| Power supply voltage | Power supply voltage | VCC | -0.5 to +6.5 | V |
| Input voltage | 5 V-tolerant ports* 1 | V in | -0.3 to +6.5 | V |
| Input voltage | P000 to P008, P010 to P015 | V in | -0.3 to AVCC0 + 0.3 | V |
| Input voltage | Others | V in | -0.3 to VCC + 0.3 | V |
| Reference power supply voltage | Reference power supply voltage | VREFH0 VREFH | -0.3 to +6.5 | V V |
| VBATT power supply voltage | VBATT power supply voltage | VBATT | -0.5 to +6.5 | V |
| Analog power supply voltage | Analog power supply voltage | AVCC0 | -0.5 to +6.5 | V |
| USB power supply voltage | USB power supply voltage | VCC_USB | -0.5 to +6.5 | V |
| VCC_USB_LDO | -0.5 to +6.5 | V | ||
| Analog input voltage | When AN000 to AN014 are used | V AN | -0.3 to AVCC0 + 0.3 | V |
| When AN016 to AN025 are used | -0.3 to VCC + 0.3 | V | ||
| LCD voltage | VL1 voltage | V L1 | -0.3 to +2.8 | V |
| VL2 voltage | V L2 | -0.3 to +6.5 | V | |
| VL3 voltage | V L3 | -0.3 to +6.5 | V | |
| VL4 voltage | V L4 | -0.3 to +6.5 | V | |
| Operating temperature* 2, * 3, * 4 | Operating temperature* 2, * 3, * 4 | T opr | -40 to +105 -40 to +85 | °C |
| Storage temperature | Storage temperature | T stg | -55 to +125 | °C |
Package Information
Information on the latest version of the package dimensions or mountings is shown in 'Packages' on the Renesas Electronics Corporation website.
Figure 1.1 100-pin LGA
Figure 1.1 100-pin LGA
| JEITA Package Code | RENESAS Code | Previous Code | MASS (Typ) [g] |
|---|---|---|---|
| P-LFQFP100-14x14-0.50 | PLQP0100KB-B | - | 0.6 |
| Reference Symbol | Dimensions in millimeters | Dimensions in millimeters | Dimensions in millimeters |
|---|---|---|---|
| Reference Symbol | Min | Nom | Max |
| D | 13.9 | 14.0 | 14.1 |
| E | 13.9 | 14.0 | 14.1 |
| A 2 | | 1.4 | |
| H D | 15.8 | 16.0 | 16.2 |
| H E | 15.8 | 16.0 | 16.2 |
| A | | | 1.7 |
| A 1 | 0.05 | | 0.15 |
| b p | 0.15 | 0.20 | 0.27 |
| c | 0.09 | | 0.20 |
| T | 0 q | 3.5 q | 8 q |
| e | | 0.5 | |
| x | | | 0.08 |
| y | | | 0.08 |
| L p | 0.45 | 0.6 | 0.75 |
| L 1 | | 1.0 | |
Figure 1.2 100-pin LQFP
Figure 1.2 100-pin LQFP
| JEITA Package Code | RENESAS Code | Previous Code | MASS (Typ) [g] |
|---|---|---|---|
| P-LFQFP64-10x10-0.50 | PLQP0064KB-C | - | 0.3 |
Unit: mm
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| RA4M1 | Renesas | 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch) |
| RA4M1AC3CFP | Renesas Electronics Corp. | — |
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