PN5180A0HN/C3Y

NFC Frontend IC

The PN5180A0HN/C3Y is a nfc frontend ic from NXP Semiconductors. View the full PN5180A0HN/C3Y datasheet below including key specifications.

PN5180A0HN/C3Y shares its datasheet with PN5180A0HN/C4, whose page lists every part number it covers.

Official PN5180A0HN/C3Y datasheet (PDF) — the source this page was extracted from.

Manufacturer

NXP Semiconductors

PN5180A0HN/C3Y Key Specifications

Parameter	Value
Frequency	13.56MHz
Height - Seated (Max)	1 mm
Interface	SPI, UART
Introduction Date	2020-06-02
Length	6 mm
Lifecycle Status	Production (Last Updated: 1 month ago)
Max Operating Temperature	85 °C
Max Supply Voltage	1.95 V
Min Operating Temperature	-30 °C
Min Supply Voltage	1.65 V
Mounting Type	Surface Mount
Nominal Supply Voltage (DC)	1.8 V
Number of Terminals	40
Operating Temperature	-30°C ~ 85°C (TA)
Package / Case	40-VFQFN Exposed Pad
Packaging	Cut Tape
REACH SVHC	Unaffected
RoHS	Compliant
Standard Pack Qty	4000
Standards	FeliCa, ISO 14443, ISO 15693, ISO 18000-3, ISO 18092, ISO 21481, MIFARE, NFC
Supplier Device Package	40-HVQFN (6x6)
Terminal Pitch	500 µm
Type	RFID Reader/Transponder
Supply Voltage	2.7V ~ 5.5V
Width	6 mm

PN5180A0HN/C3Y Overview

Part: PN5180A0HN/C4Y — NXP Semiconductors

Type: High-power multiprotocol NFC frontend IC

Description: Full NFC Forum-compliant 13.56 MHz frontend with SPI host interface (up to 7 Mbit/s), transmitter current up to 250 mA, EMVCo 3.1 L1 support, in HVQFN40 (firmware 4.1, delivered on 13" reel).

Operating Conditions:

Supply voltage: VBAT 2.7–5.5 V; TVDD 2.7–5.5 V; PVDD 1.65–1.95 V (1.8 V supply) or 2.7–3.6 V (3.3 V supply)
Operating temperature: -30 to +85 °C (ambient, in still air with exposed pins soldered on a 4-layer JEDEC PCB)
TVDD supply current: 180 mA typ, 250 mA max
LDO_OUT: 3.2–3.6 V at 0–100 mA load

Absolute Maximum Ratings:

Max supply voltage: PVDD 3.6 V; TVDD 5.5 V
Max supply current on TVDD: 300 mA
Max output current on LDO_OUT: 100 mA
Max total power dissipation: 1125 mW
Max junction temperature: 150 °C
Storage temperature: -55 to +150 °C
ESD (HBM): 1500 V

Key Specs:

VBAT supply: 2.7 V min, 3.3 V typ, 5.5 V max
TVDD supply: 2.7 V min, 5.0 V typ, 5.5 V max
TVDD supply current: 180 mA typ, 250 mA max
Hard power-down current: 10 μA typ (RESET_N low, Tamb = 25 °C)
Standby current: 15 μA typ (Tamb = 25 °C)
Ambient temperature: -30 to +85 °C
Clock: 27.12 MHz crystal, or external 8/12/16/24 MHz clock via PLL
SPI data rate: up to 7 Mbit/s

Features:

Reader/Writer modes: ISO/IEC 14443 A/B up to 848 kbit/s, JIS X 6319-4 (FeliCa), ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, MIFARE Classic
NFC-IP1 (ISO/IEC 18092) and NFC-IP2 (ISO/IEC 21481)
ISO/IEC 14443 type A card emulation up to 848 kbit/s, with active load modulation
Dynamic Power Control (DPC), Adaptive Waveform Control (AWC), Adaptive Receiver Control (ARC)
Automatic EMD handling without host interaction
Low-power card detection (LPCD) with external LDO/DC-DC power-down support
Zero-Power-Wake-up
Full compliance with EMVCo 3.1 L1 and NFC Forum standards
Integrated 3.3 V LDO output (LDO_OUT)
NFC Cockpit tool, LPC1769-based development kit and NFC Reader Library

Applications:

Payment
Physical access
eGov
Industrial

Package:

HVQFN40 (SOT618-1), 6 x 6 x 1.0 mm, 40 terminals + central ground pad, MSL 3, delivered on 13" reel (4000 pcs minimum order)

PN5180A0HN/C3Y Features

Transmitter current up to 250 mA
Dynamic Power Control (DPC) for optimized RF performance, even under detuned antenna conditions
Adaptive Waveform Control (AWC) automatically adjusts the transmitter modulation for RF compliancy
Adaptive Receiver Control (ARC) automatically adjusts the receiver parameters for always reliable communication
Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property licensing rights
Full compliancy with all standards relevant to NFC, contactless operation and EMVCo 3.1 L1
Active load modulation supports smaller antenna in Card Emulation Mode
Automatic EMD handling performed without host interaction relaxes the timing requirements on the Host Controller
Low-power card detection (LPCD) minimizes current consumption during polling
Automatic support of system LDO or system DC-DC power-down mode during LPCD
Zero-Power-Wake-up
Small, industry-standard packages
NFC Cockpit: PC-based support tool for fast configuration of register settings
Development kit with 32-bit NXP LPC1769 MCU and antenna
NFC Reader Library with source code ready for EMVCo 3.1 L1 and NFC Forum compliance

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

PN5180A0HN/C3Y Applications

Payment
Physical-access
eGov
Industrial

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

PN5180A0HN/C3Y Pin Configuration

Symbol	Pin	Type	Description
NSS	1	I	SPI NSS
AUX2 /DWL_REQ	2	I/O	Analog test bus or Download request
MOSI	3	I	SPI MOSI
PVSS	4	supply	Pad ground
MISO	5	O	SPI MISO
PVDD	6	supply	Pad supply voltage
SCK	7	I	SPI Clock
BUSY	8	O	Busy signal
VSS	9	supply	Ground
RESET_N	10	I	RESET, Low active
n.c.	11	-	leave unconnected, do not ground
VBAT	12	supply	Supply Connection, all VBAT mandatory to be connected
VBAT	13	supply	Supply Connection, all VBAT mandatory to be connected
nc / LDO_OUT	14	O	leave unconnected, do not ground / use as 3.3 V LDO output
RXN	15	I	Receiver Input
RXP	16	I	Receiver Input
VMID	17	supply	Stabilizing capacitor connection output
TX2	18	O	Antenna driver output 2
TVSS	19	supply	Antenna driver ground

All information provided in this document is subject to legal disclaimers.

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

Table 4. Pin description HVQFN40 ...continued

Symbol	Pin	Type	Description
n.c.	20	-	leave unconnected, do not ground
TX1	21	O	Antenna driver output 1
TVDD	22	supply	Antenna driver supply
ANT1	23	I	Antenna connection 1 for load modulation in card emulation mode (only in case of PLM)
ANT2	24	I	Antenna connection 2 for load modulation in card emulation mode (only in case of PLM)
VDHF	25	supply	Stabilizing capacitor connection output
VBAT	26	supply	Supply Connection, all VBAT mandatory to be connected
VSS	27	supply	Ground
AVDD	28	supply	Analog VDD supply voltage input (1.8 V), connected to VDD
VDD	29	supply	VDD output (1.8 V)
DVDD	30	supply	Digital supply voltage input (1.8 V), connected to VDD
n.c.	31	-	leave unconnected, do not ground
n.c.	32	-	leave unconnected, do not ground
n.c.	33	-	leave unconnected, do not ground
n.c.	34	-	leave unconnected, do not ground
n.c.	35	-	leave unconnected, do not ground
CLK1	36	I	Clock input for crystal. This pin is also used as input for an external generated accurate clock (8 MHz, 12 MHz, 16 MHz, 24 MHz, other clock frequencies not supported)
CLK2	37	O	Clock output (amplifier inverted signal output) for crystal
GPO1	38	O	(double function pin) GPO1, Digital output 1
IRQ	39	O	Interrupt request output, active level configurable
AUX1	40	O	Analog/Digital Test signal

The central heat sink of the HVQFN40 package shall be connected to GND.

The pinning of the TFBGA version can be found in the data sheet addendum which is available through the NXP DocStore.

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

PN5180A0HN/C3Y Recommended Operating Conditions

Exposure of the device to other conditions than specified in the recommended operating conditions section for extended periods may affect device reliability.

Electrical parameters (minimum, typical and maximum) of the device are guaranteed only when it is used within the recommended operating conditions.

Table 124. Recommended Operating Conditions

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V DD(VBAT)	supply voltage on pin VBAT	-	2.7	3.3	5.5	V
V DD(PVDD)	supply voltage on pin PVDD	1.8 V supply	1.65	1.8	1.95	V
V DD(PVDD)	supply voltage on pin PVDD	3.3 V supply	2.7	3.3	3.6	V
V DD(TVDD)	supply voltage on pin TVDD	-	2.7	5.0	5.5	V
I DD(TVDD)	supply current on pin TVDD	in still air with exposed pins soldered on a 4 layer JEDEC PCB	-	180	250	mA
V OUT(LDO_OUT)	output voltage of pin LDO_OUT	I (OUT)LDO_OUT = 0...100mA	3.2	3.3	3.6	V
T amb	ambient temperature	in still air with exposed pins soldered on a 4 layer JEDEC PCB	-30	+25	+85	°C

The system design shall consider that maximum supply voltages are not exceeded during power-on of the system.

Table 124. Recommended Operating Conditions

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

PN5180A0HN/C3Y Thermal Information

Symbol	Parameter	Conditions	Typ	Unit
R th(j-a)	thermal resistance from junction to ambient	in free air with exposed pad soldered on a 4 layer JEDEC PCB, package HVQFN40	40	K/W

PN5180A0HN/C3Y Typical Application

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

PN5180A0HN/C3Y Package Information

Figure 50. Package outline SOT618-1

High-performance multiprotocol full NFC frontend, supporting all NFC Forum modes

Variants on the same datasheet

These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.

Part Number	Manufacturer	Package
PN5180	NXP Semiconductors	—
PN5180A0ET/C3J	NXP Semiconductors	—
PN5180A0ET/C3QL	NXP Semiconductors	—
PN5180A0ET/C4J	NXP Semiconductors	—
PN5180A0ET/C4QL	NXP Semiconductors	—
PN5180A0HN/C3E	NXP Semiconductors	—
PN5180A0HN/C4	NXP Semiconductors	—
PN5180A0HN/C4E	NXP Semiconductors	—
PN5180A0HN/C4Y	NXP Semiconductors	40-VFQFN Exposed Pad

More datasheets

All NXP Semiconductors datasheets (210)

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