PIC24FJ64GA705
The PIC24FJ64GA705 is an electronic component from Microchip Technology. View the full PIC24FJ64GA705 datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
Microchip Technology
Category
Microcontrollers
Overview
| Pin Function | Pin Number/Grid Locator | Pin Number/Grid Locator | Pin Number/Grid Locator | Pin Number/Grid Locator | I/O | Input Buffer | Description |
|---|---|---|---|---|---|---|---|
| Pin Function | 28-Pin SOIC, SSOP, SPDIP | 28-PinQFN, UQFN | 44-Pin TQFP | 48-Pin UQFN/TQFP | I/O | Input Buffer | Description |
| PGC1 | 5 | 2 | 22 | 24 | I | ST | ICSP™ Programming Clock |
| PGC2 | 22 | 19 | 9 | 10 | I | ST | ICSP™ Programming Clock |
| PGC3 | 15 | 12 | 42 | 46 | I | ST | ICSP™ Programming Clock |
| PGD1 | 4 | 1 | 21 | 23 | I/O | DIG/ST | ICSP Programming Data |
| PGD2 | 21 | 18 | 8 | 9 | I/O | DIG/ST | ICSP Programming Data |
| PGD3 | 14 | 11 | 41 | 45 | I/O | DIG/ST | ICSP Programming Data |
| PMA0 | - | - | 3 | 3 | I/O | DIG/ST/ TTL | Parallel Master Port Address[0]/ Address Latch Low |
| PMA1 | - | - | 2 | 2 | I/O | DIG/ST/ TTL | Parallel Master Port Address[1]/ Address Latch High |
| PMA2 | - | - | 12 | 13 | I/O | DIG/ST/ TTL | Parallel Master Port Address[2] |
| PMA3 | - | - | 38 | 41 | I/O | DIG/ST/ TTL | Parallel Master Port Address[3] |
| PMA4 | - | - | 37 | 40 | I/O | DIG/ST/ TTL | Parallel Master Port Address[4] |
| PMA5 | - | - | 4 | 4 | I/O | DIG/ST/ TTL | Parallel Master Port Address[5] |
| PMA6 | - | - | 5 | 5 | I/O | DIG/ST/ TTL | Parallel Master Port Address[6] |
| PMA7 | - | - | 13 | 14 | I/O | DIG/ST/ TTL | Parallel Master Port Address[7] |
| PMA8 | - | - | 32 | 35 | I/O | DIG/ST/ TTL | Parallel Master Port Address[8] |
| PMA9 | - | - | 35 | 38 | I/O | DIG/ST/ TTL | Parallel Master Port Address[9] |
| PMA14/PMCS/ PMCS1 | - | - | 15 | 16 | I/O | DIG/ST/ TTL | Parallel Master Port Address[14]/ Slave Chip Select/Chip Select 1 Strobe |
Legend:
TTL = TTL input buffer
ANA = Analog level input/output DIG = Digital input/output
ST = Schmitt Trigger input buffer I 2 C = I 2 C/SMBus input buffer XCVR = Dedicated Transceiver
Features
- Up to 14-Channel, Software-Selectable, 10/12-Bit Analog-to-Digital Converter:
- -12-bit, 200K samples/second conversion rate (single Sample-and-Hold)
- -Sleep mode operation
- -Charge pump for operating at lower AVDD
- -Band gap reference input feature
- -Windowed threshold compare feature
- -Auto-scan feature
- Three Analog Comparators with Input Multiplexing:
- -Programmable reference voltage for comparators
- LVD Interrupt Above/Below Programmable VLVD Level
- Charge Time Measurement Unit (CTMU):
- -Allows measurement of capacitance and time
- -Operational in Sleep
Electrical Characteristics
This section provides an overview of the PIC24FJ256GA705 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ256GA705 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings
| Ambient temperature under bias.............................................................................................................-40°C | to +125°C |
|---|---|
| Storage temperature .............................................................................................................................. -65°C | to +150°C |
| Voltage on VDD with respect to VSS ......................................................................................................... | -0.3V to +4.0V |
| Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to VSS ....... -0.3V to | (VDD + 0.3V) |
| Voltage on any general purpose digital or analog pin (5.5V tolerant, including MCLR) with respect to VSS: | Voltage on any general purpose digital or analog pin (5.5V tolerant, including MCLR) with respect to VSS: |
| When VDD = 0V: .......................................................................................................................... | -0.3V to +4.0V |
| When VDD 2.0V: ....................................................................................................................... | -0.3V to +6.0V |
| Voltage on AVDD with respect to VSS ...................................................(VDD - 0.3V) to (lesser of: 4.0V or | (VDD + 0.3V)) |
| Voltage on AVSS with respect to VSS ........................................................................................................ | -0.3V to +0.3V |
| Maximum current out of VSS pin ...........................................................................................................................300 | mA |
| Maximum current into VDD pin (Note 1) ................................................................................................................250 | mA |
| Maximum output current sunk by any I/O pin .........................................................................................................25 | mA |
| Maximum output current sourced by any I/O pin ....................................................................................................25 | mA |
| Maximum current sunk by all ports .......................................................................................................................200 | mA |
| Maximum current sourced by all ports (Note 1) ....................................................................................................200 | mA |
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 32-1).
† NOTICE: Stresses above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Thermal Information
| Rating | Symbol | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| PIC24FJ256GA705: | |||||
| Operating Junction Temperature Range | TJ | -40 | - | +125 | °C |
| Operating Ambient Temperature Range | T A | -40 | - | +125 | °C |
| Power Dissipation: | |||||
| Internal Chip Power Dissipation: PINT = VDD x (IDD - I OH) | PD | PINT + PI /O | PINT + PI /O | PINT + PI /O | W |
| I/O Pin Power Dissipation: PI /O = ({VDD - VOH} x I OH) + (V OL x I OL ) | |||||
| Maximum Allowed Power Dissipation | PDMAX | (T J - T A )/ JA | (T J - T A )/ JA | (T J - T A )/ JA | W |
Package Information
| Units | MILLIMETERS | MILLIMETERS | MILLIMETERS | |
|---|---|---|---|---|
| Dimension Limits | Dimension Limits | MIN | NOM | MAX |
| Contact Pitch | E | 0.40 BSC | ||
| Center Pad Width | X2 | 4.70 | ||
| Center Pad Length | Y2 | 4.70 | ||
| Contact Pad Spacing | C1 | 6.00 | ||
| Contact Pad Spacing | C2 | 6.00 | ||
| Contact Pad Width (X48) | X1 | 0.20 | ||
| Contact Pad Length (X48) | Y1 | 0.80 | ||
| Corner Anchor Pad Width (X4) | X3 | 0.90 | ||
| Corner Anchor Pad Length (X4) | Y3 | 0.90 | ||
| Pad Corner Radius (X 20) | R | 0.10 | ||
| Contact Pad to Center Pad (X48) | G1 | 0.25 | ||
| Contact Pad to Contact Pad | G2 | 0.20 | ||
| Thermal Via Diameter | V | 0.33 | ||
| Thermal Via Pitch | EV | 1.20 |
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
- For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 2.
Microchip Technology Drawing C04-2442A-M4
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| PIC24FJ64GA702 | Microchip Technology | — |
| PIC24FJ64GA704 | Microchip Technology | — |
| PIC24FJ64GA70X | Microchip Technology | — |
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