NRF9161-LACA-R

Part: nRF9161 — Nordic Semiconductor

Type: Cellular IoT SiP (System-in-Package) with integrated MCU, LTE modem, and GPS

Description: A highly integrated cellular IoT SiP featuring an Arm Cortex-M33 microcontroller with 1 MB flash and 256 kB RAM, a 3GPP LTE release 14 Cat-M1/NB1/NB2 compliant modem, and a GPS receiver, all in a compact 10 × 16 × 1.04 mm LGA package.

Operating Conditions:

• Supply voltage: 3.0 - 5.5 V
• LTE power saving mode (PSM) floor current: 2.7 μA @ 3.7 V
• eDRX current: 19 μA (Cat-M1), 33 μA (Cat-NB1) @ 3.7 V (UICC included)

Absolute Maximum Ratings:

Key Specs:

• Microcontroller: Arm Cortex-M33
• Flash memory: 1 MB
• RAM: 256 kB
• ADC: 12-bit, 200 ksps, 8 configurable channels
• LTE Cat-M1 sensitivity: -108 dBm (low band), -107 dBm (mid band)
• LTE output power: Up to 23 dBm
• GPIO pins: 32
• Package dimensions: 10 × 16 × 1.04 mm

Features:

• Arm TrustZone and CryptoCell 310 for security
• Integrated GPS L1 C/A and QZSS L1 C/A receiver
• Up to 4x SPI master/slave with EasyDMA
• Up to 4x I2C compatible two-wire master/slave with EasyDMA
• Up to 4x UART (CTS/RTS) with EasyDMA
• I2S and Digital microphone interface (PDM) with EasyDMA
• Power saving features: DRX, eDRX, PSM
• Single 50 Ω antenna interface

Applications:

• Sensor networks
• Logistics and asset tracking
• Smart energy
• Smart building automation
• Smart agriculture
• Industrial
• Retail and monitor devices
• Medical devices
• Wearables

Package:

• LGA (10 × 16 × 1.04 mm)

• Up to two PDM microphones configured as a left/right pair using the same data input
• 16 kHz output sample rate, 16-bit samples
• EasyDMA support for sample buffering
• HW decimation filters
• Selectable ratio of 64 or 80 between PDM_CLK and output sample rate

The PDM module illustrated below is interfacing up to two digital microphones with the PDM interface. EasyDMA is implemented to relieve the real-time requirements associated with controlling of the PDM slave from a low priority CPU execution context. It also includes all the necessary digital filter elements to produce pulse code modulation (PCM) samples. The PDM module allows continuous audio streaming.

Figure 38: PDM module

• Sensor networks
• Logistics and asset tracking
• Smart energy
• Smart building automation
• Smart agriculture

The GPIO port peripheral implements up to 32 pins, PIN0 through PIN31 . Each of these pins can be individually configured in the PIN_CNF[n] registers (n=0..31).

The following parameters can be configured through these registers:

• Direction
• Drive strength
• Enabling of pull-up and pull-down resistors
• Pin sensing
• Input buffer disconnect
• Analog input (for selected pins)

Note: All write-capable registers are retained registers, see POWER - Power control on page 63 for more information.

The input buffer of a GPIO pin can be disconnected from the pin to enable power savings when the pin is not used as an input, see GPIO port and the GPIO pin details on page 98. Inputs must be connected to get a valid input value in the IN register, and for the sense mechanism to get access to the pin.

Other peripherals in the system can connect to GPIO pins and override their output value and configuration, or read their analog or digital input value. See GPIO port and the GPIO pin details on page 98.

Selected pins also support analog input signals, see ANAIN in GPIO port and the GPIO pin details on page 98. The assignment of the analog pins can be found in Pin assignments on page 450.

The following delays should be taken into considerations:

• There is a delay of 2 CPU clock cycles from the GPIO pad to the IN register.
• The GPIO pad must be low (or high depending on the SENSE polarity) for 3 CPU clock cycles after DETECT has gone high to generate a new DETECT signal.

Note: When a pin is configured as digital input, care has been taken to minimize increased current consumption when the input voltage is between VIL and VIH. However, it is a good practice to ensure that the external circuitry does not drive that pin to levels between VIL and VIH for a long period of time.

Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the device.

No internal voltage boost converters

Table 58: Absolute maximum ratings

28 ATEX compliance requires a maximum of 5.0 V.