NAU7802

Part: Nuvoton NAU7802

Type: Precision 24-bit Analog-to-Digital Converter (ADC)

Key Specs:

• Supply Voltage: 2.7V~5.5V
• Effective Number of Bits (ENOB): up to 23-bit
• Programmable Gain Amplifier (PGA) Gain: 1 to 128
• RMS Noise: 50nV (10 SPS data output rate, PGA gain = 128)
• RMS Noise: 150nV (80 SPS data output rate, PGA gain = 128)
• Standby Current: < 1uA
• Operating Temperature: -40~85°C
• AVDD LDO Output Drive Capability: Minimum 10mA at 3.0V output voltage
• External Differential Reference Voltage Range: 0.1V ~ 5V

Features:

• Onboard low-noise programmable gain amplifier (PGA)
• Onboard RC or Crystal oscillator
• Precision 24-bit sigma-delta (Σ-Δ) ADC
• Simultaneous 50Hz and 60Hz rejection (reaching -90dB)
• 2-wire interface compatible with I2C protocol
• On-chip AVDD regulator (Programmable AVDD: Off, 2.4V ~ 4.5V with eight options)
• Programmable ADC data output rates
• On-chip calibration
• On-chip power-on reset circuit
• On-chip temperature sensor
• Low Power Consumption and Programmable Power Management Options
• Halogen-free, RoHS-compliant and TSCA-compliant package

Applications:

• Weigh scales
• Strain Gauge
• Industrial process control
• Liquid/gas flow control
• Pressure sensors
• Voltage monitors

Package:

• SOP-16: 150 mil
• PDIP-16: 300 mil
• QFN-16: null

• Supply Voltage: 2.7V~5.5V
• On-chip AVDD regulator for internal analog circuit or external load cell o Programmable AVDD: Off, 2.4V ~ 4.5V with eight options
• Minimum 10mA AVDD LDO output drive capability at 3.0V output voltage* 1
• 23-bit effective precision analog-to-digital converter
• Simultaneous 50Hz and 60Hz rejection (reaching -90dB)
• RMS Noise:
  • o 50nV in 10 SPS data output rate and PGA gain = 128
  • o 150nV in 80 SPS data output rate and PGA gain = 128
• Programmable PGA gains from 1 to 128
• Programmable ADC data output rates
• External differential reference voltage ranges from 0.1V ~ 5V
• System clock: External crystal oscillator or on-chip RC oscillator (4.9152Mhz)
• On-chip calibration
• On-chip power-on reset circuit
• On-chip temperature sensor
• Low Power Consumption and Programmable Power Management Options o < 1uA standby current
• External 4.9152MHz Crystal oscillator
• System clock:
  • o Internal 4.9152MHz RC oscillator (power-on default system clock)
  • o External 4.9152MHz Crystal oscillator
• MCU control interface: 2-wire interface compatible with I2C protocol
• Operating Temperature: -40~85°C
• Packages:
  • o SOP-16 (150mil) / PDIP-16 (300mil) / QFN-16
  • o Package is Halogen-free, RoHS-compliant and TSCA-compliant

• Weigh scales
• Strain Gauge
• Industrial process control
• Liquid/gas flow control
• Pressure sensors
• Voltage monitors

¹ Note:

The LDO load current at AVDD should not exceed 10mA.

DVDD must be 0.3V greater than desired AVDD output voltage.

Note: QFN device center pad underneath should be connected to AVSS.

1.1 Absolute Maximum Ratings

Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life time and reliability

* AVDD should not exceed DVDD supply voltage

1.2 DC Electrical Characteristics

(Unless otherwise specified; Typical value is tested at TA=25°C, DVDD = 5V, AVDD = 5V)

1.3 RC Osc and AC characteristics

1.4 Temperature Sensor

1.5 Typical Characteristics

1.5.1 NAU7802 Linearity – (Error % vs. Input Voltage) AVDD = 4.5V / PGA gain = 1x

• NAU7802 Linearity Performance is symmetric, from the differential input voltage -1.2V to 0V and from 0V to 1.2V. One-sided linearity performance result is shown.

1.5.2 Noise Performance – NAU7802

• AVDD/
  REFP (V) PGA
  Gain ENOB ENOB2 NOISE FREE BITS
• 4.5 1 22.29 22.31 20.09
• 4.5 2 22.15 22.16 19.75
• 4.5 4 22.01 22.02 19.61
• 4.5 8 21.88 21.91 19.36
• 4.5 16 21.39 21.42 18.71
• 4.5 32 21.09 21.11 18.42
• 4.5 64 20.42 20.43 17.89
• 4.5 128 19.73 19.74 17.11
• 3.3 1 21.14 21.15 19.09
• 3.3 2 21.11 21.13 18.96
• 3.3 4 21.1 21.1 19
• 3.3 8 21.03 21.04 18.64
• 3.3 16 20.8 20.81 18.19
• 3.3 32 20.41 20.42 17.85
• 3.3 64 19.84 19.85 17.23
• 3.3 128 19.16 19.17 16.54

1.5.3 ESD Performance – NAU7802

1.6 Digital Serial Interface Timing

Two-wire Control Mode Timing

1.7 Analog Input (VIN1P, VIN1N, VIN2N, VIN2P)

The input signal to be measured is applied to one of two differential input signal pairs. The desired signal pair is selected using an analog input multiplexer, which is controlled by settings in the device command and control registers.

This device is optimized to accept differential input signals, but can also measure single-ended signals. When measuring single-ended signals with respect to ground, connect the negative input (VIN1N or VIN2N) to ground and connect the input signal to the positive input (VIN1P or VIN2P). Note that when this device is configured this way, only half of the converter full-scale range is used, since only positive digital output codes are produced.

1.8 Power Supply

The digital power supply DVDD should use the same power source as used for the host processor supporting the digital interface communication. The analog power supply AVDD can be provided by external regulator output (power-on default setting) or provided by a built-in voltage regulator. The eight programmable output voltage levels of the built-in regulator are: off (High-Z output, default power-on setting), 2.4V, 2.7V, 3.0V 3.3V, 3.6V, 4.2V, and 4.5V. This output is intended to provide the driving current for external sensors such as load cells for weight measurement applications.

1.9 2-Wire-Serial Control and Data Bus (I2 C Style Interface)

The serial interface provides a 2-wire bidirectional read/write data interface similar to and typically compatible with standard I2C protocol. This protocol defines any device that sends CLK onto the bus as a master, and the receiving device as slave. The NAU7802 can function only as a slave device.

An external clock drives the device, and in accordance with the protocol, data is sent to or from the device accordingly. All functions are controlled by means of a register control interface in the device. Additionally, a "data ready" output pin – DRDY pin is provided to indicate to the host that a new conversion has been completed and that data are ready to be read from the device. The host may either use this signal or poll device register Reg0x00[5] CR bit to determine when new data are available.

1.9.1 2-Wire Protocol Convention

All 2-Wire interface operations must begin with a START condition, which is a HIGHto-LOW transition of SDIO while SCLK is HIGH. All 2-Wire interface operations are terminated by a STOP condition, which is a LOW to HIGH transition of SDIO while SCLK is HIGH. A STOP condition at the end of a read or write operation places the serial interface in standby mode.

An acknowledge (ACK), is a software convention is used to indicate a successful data transfer. To allow for the ACK response, the transmitting device releases the SDIO bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDIO line LOW to acknowledge the reception of the eight bits of data.

Following a START condition, the master must output a device address byte. This consists of a 7-bit device address, and the LSB of the device address byte is the R/W (Read/Write) control bit. When R/W=1, this indicates the master is initiating a read operation from the slave device, and when R/W=0, the master is initiating a write operation to the slave device. If the device address matches the address of the slave device, the slave will output an ACK during the period when the master allows for the ACK signal.

Figure 1: START and STOP

Figure 2: Acknowledge and NOT Acknowledge

Figure 3: Slave Address Byte, Control Address Byte, and Data Byte

Figure 4: A complete 2 wire write 1 control register sequence

1.9.2 2-Wire Write Operation

A Write operation consists of a two-byte instruction followed by one or more Data Bytes. A Write operation requires a START condition, followed by a valid device address byte with R/W=0, a valid control address byte, data byte(s), and a STOP condition.

When more than one Data Byte is written, this is known as a "burst write" operation. In this operation, the host may write sequential bytes of information simply by transmitting a new data byte after each ACK from the NAU7802. The NAU7802 automatically increments the register address by one for each subsequent byte-write operation. This will continue until the STOP condition is met.

The NAU7802 is permanently programmed with "010 1010" (0x2A) as the Device Address. If the Device Address matches this value, the NAU7802 will respond with the expected ACK signaling as it accepts the data being transmitted into it.

1.9.3 2-Wire Single Read Operation

A Read operation consists of a three-byte Write instruction followed by a Read instruction of one or more data bytes. The bus master initiates the operation issuing the following sequence: a START condition, device address byte with the R/W bit set to "0", and a Control Register Address byte. This indicates to the slave device which of its control registers is to be accessed.

The NAU7802 is permanently programmed with "010 1010" (0x2A) as its device address. If the device address matches this value, the NAU7802 will respond with the expected ACK signaling as it accepts the Control Register Address being transmitted into it. After this, the master transmits a second START condition, and a second instantiation of the same device address, but now with R/W=1.

After again recognizing its device address, the NAU7802 transmits an ACK, followed by a one-byte value containing the data from the selected control register inside the NAU7802. During this phase, the master generates the ACK signaling with each byte transferred from the NAU7802. If there is no STOP signal from the master, the NAU7802 will internally auto-increment the target Control Register Address and then output the data bytes for this next register in the sequence.

This process will continue while the Master continues to issue ACK signaling. If the Control Register Address being indexed inside the NAU7802 reaches the value 0x7F (hexadecimal) and the value for this register is output, the index will roll over to 0x00. The data bytes will continue to be output until the master terminates the read operation by issuing a STOP condition.

1.10 2-Wire Timing

The NAU7802 is compatible with serial clock speeds defined as "standard mode" with SCLK 0 - 100 kHz, and "fast mode" with SCLK 0 - 400 kHz. At these speeds the total bus line capacitance load is required to be 400 pF or less.

Open collector drivers are required for the serial interface. Therefore, the bus line rise time is determined by the total serial bus capacitance and the DVDD pull-up resistors. The NAU7802 defaults to a weak pull up (typical 50 k ohm) for applications with no external pull up resistor. Register 0x11 bits 5:4 provide other options including a strong internal pull-up (typical 1.6 k ohm) or no internal pull-up resistor.

1.11NAU7802 Streaming Data Mode

1.11.1 Enabling the Streaming I2C Mode

• • Power Up the chip
• o Write 0x00 = 0x06 (PU analog and PU digital)
• o (read back 0x00 bit 3 to make sure chip is powered up)
• Enable Streaming I2C Mode
• o Write REG11[7] =1 to enable streaming mode 1, or Write REG11[7] =1 and REG11[6]=1 and REG15[7]=1 to enable streaming mode 2
• o (read back 0x1D bit 7 to make sure the streaming I2C mode is active)

1.11.2 Streaming I2C Mode R/W Protocol 1

When REG0x11[7] CRSD=1, I2C is IDLE and a conversion is complete, NAU7802 will pull SDA/SDIO low to inform the host a conversion is complete. Host should respond by pulling SDA/SDIO low and pulling SCK low to initial an I2C "start" condition. When seeing SCK pulled low by host, NAU7802 will release the SDA/SDIO. Host can continue the standard I2C transaction with NAU7802

1.11.3 Streaming I2C Mode R/W Protocol 2

In addition to CASE1 REG11[7] =1, if REG0x11[6] FRD=1 and REG0x15[7]=1, host can direct issue a I2C read cycle (No writing register address first needed), after the ACK bit for the ID and "Read Select", the following 24 SCK is used for NAU7802 to shift out the 24 bit ADC conversion result without the ACK bit needed. So the total Read ADC conversion data cycle can be shortened to 33 SCK comparing to 54 SCK plus a repeat start by using the standard I2C.

Note: Write NAU7802 register is always allowed by using Standard I2C write NAU7802 register protocol. So these two special bits can be reset to 0 to return to Standard I2C protocol

1.12Device Calibration Features

Calibration is not required for low accuracy applications, but may be needed in sensitive applications. When calibration is used the system designer has three options.

Calibration can be performed at the system level with an external processor or at the ADC device. Inside the ADC device both internal and external calibration can be performed.

Internal ADC device calibration only removes internal PGA gain and offset errors.

External ADC device calibration removes DC errors at the device input pins and the internal PGA gain and offset errors.

As with all devices of this type, the NAU7802 internal gain factors and offset voltages will contain small errors owing to fabrication process variations, power supply voltage changes, and temperature variations. The same types of errors exist at the external system level.

These errors can be measured by the NAU7802 device itself using the calibration features. After calibration, the stored values in the calibration registers are automatically added/subtracted to the data from the ADC before being output as the ADC resulting data. It is recommended to calibrate the NAU8702 after the following conditions:

• Initial power-up
• Power-up after long-duration register mediated power-down conditions
• PGA gain changes
• Supply changes
• Significant temperature changes (can be measured using built-in thermal sensing feature)
• Sample rate changes
• Channel select changes

Calibration is initiated by writing 1 to Reg0x02[2] CALS bit. CALS then becomes a status bit that can be read to know when calibration is complete. Calibration type is defined by Reg0x02[1:0] CALMOD bits. CALS will remain Logic=1 during calibration, and will read back as Logic=0 when calibration is completed.

After calibration, it is important to check the Reg0x02[3] CAL_ERR status bit to determine if there was any problem during calibration. If there was an error, all data output could be invalid.

1.12.1 Internal or External Calibration

The internal calibration disconnects the inputs from the input pins and internally connects the differential inputs to the same internal voltage reference point for calibration. External calibration uses the inputs as-is, and it is up to the system designer to configure them appropriately for the calibration procedure. The resulting gain or offset calibration value is stored in the selected calibration register. The same register sets are used for both internal or external calibration and it is intended that only one choice of internal/external calibration is used at any given time.

At all times, when reading a value from the ADC registers, the gain and offset calibration values are added/subtracted to the ADC value before being output. The default values for the calibration registers is zero, so these have no effect on the ADC output value until after a calibration operation has been instantiated.

The resulting output value is calculated as: ADC Output Value = Gain_Calibration* (ADC measurement - Offset_Calibration)

Calibration Equations:

OFFSET = sign(23)

× (22 × 2-1 + 21 × 2-2 + 20 × 2-3 + 19 × 2-4 + 18 × 2-5 + 17 × 2-6 + 16 × 2-7 + 15 × 2-8 + 14 × 2-9 + 13 × 2-10 + 12 × 2-11 + 11 × 2-12 + 10 × 2-13 + 9 × 2-14 + 8 × 2-15 + 7 × 2-16 + 6 × 2-17 + 5 × 2-18 + 4 × 2-19 + 3 × 2-20 + 2 × 2-21 + 1 × 2-22 + 0 × 2-23)

GAIN_Calibration

= 31 × 2⁸ + 30 × 2⁷ + 29 × 2⁶ + 28 × 2⁵ + 27 × 2⁴ + 26 × 2³ + 25 × 2² + 24 × 2¹ + 23 × 2⁰ + 22 × 2-1 + 21 × 2-2 + 20 × 2-3 + 19 × 2-4 + 18 × 2-5 + 17 × 2-6 + 16 × 2-7 + 15 × 2-8 + 14 × 2-9 + 13 × 2-10 + 12 × 2-11 + 11 × 2-12 + 10 × 2-13 + 9 × 2-14 + 8 × 2-15 + 7 × 2-16 + 6 × 2-17 + 5 × 2-18 + 4 × 2-19 + 3 × 2-20 + 2 × 2-21 + 1 × 2-22 + 0 × 2-23

sign(b23) = 1 if b23 =0; sign(b23) = -1 if b23 =1.

DOUT〈23: 0〉′ = (DOUT〈23: 0〉 + OFFSET〈23: 0〉) × GAIN_Calibration〈31: 0〉

1.12.2 Calibration Limitations

Note that the offset that is trimmed from the input is mapped through the gain register. Additionally:

• Calibration can be limited by signal headroom in the analog path
• With the converters intrinsic gain & offset error the minimal full scale input range may be higher or lower.

1.12.3 Calibration Error

A calibration error may occur during gain calibration when one of the following happens:

• The gain required to map input to full scale is larger than the range available in the gain register ~ 256
• The offset adjusted input is negative, e.g. 256 > gain > 0
• If there is a calibration error, CAL_ERR will set to Logic=1 when the calibration sequence is completed. Once CAL_ERR is set to Logic=1, it will remain in this state until either the NAU7802 is reset, or after a valid calibration sequence is completed. When CAL_ERR = 1, the data in the calibration registers is invalid. It is recommended perform the calibration routine again, or to write a default value into the calibration registers.

1.13Internal Band-Gap Circuit

An internal band-gap establishes accurate operation of the device over a wide temperature range. No adjustment of the bandgap is necessary. For optimum performance, the NAU7802 makes available a band-gap output pin "VBG" which should be bypassed to ground with a high quality X7R small value 0.1 uF filter capacitor.

1.14Reset and Power-down Mode

An automatic built-in power-on reset function will reset the NAU7802 after DVDD power becomes valid. After AVDD power is stable (from external power or from the built-in regulator), reset may also be initiated at any time using the register control interface. The scope of the register based reset using register 0x00 bit 0, named "RR" set to 1, is equivalent to the poweron reset.

Power-down standby mode can be selected using the register control interface using register 0x00 bits 2:1, named "PUA" and "PUD" set to 0. This mode shuts down the entire analog portion of the part, including the 24-bit ADC, voltage regulator, PGA, bandgap reference, and internal RC oscillator (or external crystal oscillator) to reduce power consumption.

The command and control interface is static and works normally in power-down mode. Powerdown mode can be terminated at any time by changing the register controls to return the device to normal operating mode, using register 0x00 bits 2:1, named "PUA" and "PUD" set to 1. In this way the contents of the registers are retained for immediate normal use.

After reset or after resuming normal operating mode after power-down mode, the host should wait through six cycles of data conversion. This allows the device to stabilize all functions and to flush all old internal data for a full-accuracy output. This timing is automatically generated by the device for the DRDY pin and Data Ready device status bit.

1.15Temperature Sensor

A matched pair of on-chip diodes provides temperature sensing capability. Temperature sensing is selected by setting of the analog input multiplexer using the register control interface. A PGA gain of 2x or 1x is used for temperature sensing to prevent PGA clipping.

By measuring the difference in voltage of these diodes, temperature changes can be inferred from a baseline temperature. Please refer to the specification items "Temperature sensor output" and "Temperature sensor delta coefficient."

Note: On chip temperature can be directly measured ADC and bypass PGA, when using this mode, ADC output is timed by two for correct temperature. If using PGA for temperature measurement, PGA gain needs to set 2 for correct measurement.

0x11[1]=1 // PAG input switched to temperature sensor 0x15[3:2] // set common mode to REFN or REFP and ADC gain divided by 2 0x1B[5:3]=3b'010 // disable PGA output buffer and PGA output bypass

Figure 8

1.16Oscillator Features

This device may either accept an external clock, use an internal RC oscillator, or use a built-in crystal oscillator for its time base. An accurate clock is important for the digital filtering of 50Hz or 60Hz components to work optimally. The internal oscillator is trimmed at the factory for good accuracy.

The internal RC or crystal oscillator frequency may be output on the DRDY pin. This is done by programming Reg0x00[6] DRDY_SEL bit as follows:

• Write REG0x00[6] = 0: Use oscillator as system clock
• Write REG0x01[6] = 1: Output system clock on DRDY pin

1.16.1 External Crystal Oscillator

When an external 4.9152MHz crystal oscillator is used, the preferred application circuit on the XIN & XOUT pins is as shown below. The crystal oscillator could operate without the 270 Ohm resistor and without the 18pF capacitor on XIN at a reduced performance.

1.16.2 External Clock Source

When the clock for the NAU7802 may also be provided from an external source. To use this feature, the device is configured in the same way as for using a crystal and the external clock signal is applied to the XIN pin.

Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life time and reliability

* AVDD should not exceed DVDD supply voltage