Overview

Part: LM324B, LM2902B and family from Texas Instruments

Type: Quadruple Operational Amplifiers

Key Specs:

Supply range: 3V to 36V (B, BA versions)
Low input offset voltage: ±2mV (BA version) / 3mV (B version)
ESD rating: 2kV (HBM), 1.5kV (CDM)
Low

Features

Next-generation LM324B and LM2902B
B versions are drop-in replacements for all versions of LM224, LM324, and LM2902
Improved specifications of B version
- Supply range: 3V to 36V (B, BA versions)
- Low input offset voltage: ±2mV (BA version) / 3mV (B version)
- ESD rating: 2kV (HBM), 1.5kV (CDM)
- EMI rejection: integrated RF and EMI filter
- Low input bias current: 50nA maximum (across –40°C to +125°C)
Common-mode input voltage range includes V–
Input voltage differential are drivable up to the supply voltage
For dual B versions, see LM358B and LM2904B

Applications

Pin Configuration

Figure 5-1. D, DB, J, N, NS, PW, W Packages, 14-Pin SOIC, SSOP, CDIP, PDIP, SO, TSSOP, CFP (Top View)

Figure 5-2. FK Package, 20-Pin LCCC (Top View)

Table 5-1. Pin Functions

| | PIN | |------|---------------------|-----------------------------------------------------------------------|--------|------------------------------------------------------------------| | | N | 0. | | NAME | FK (LCCC) | D (SOIC), DB (SSOP), J (CDIP), N (PDIP), NS (SO), PW (TSSOP), W (CFP) | TYPE | DESCRIPTION | | 1IN- | 3 | 2 | Input | Negative input | | 1IN+ | 4 | 3 | Input | Positive input | | 10UT | 2 | 1 | Output | Output | | 2IN- | 9 | 6 | Input | Negative input | | 2IN+ | 8 | 5 | Input | Positive input | | 2OUT | 10 | 7 | Output | Output | | 3IN- | 13 | 9 | Input | Negative input | | 3IN+ | 14 | 10 | Input | Positive input | | 3OUT | 12 | 8 | Output | Output | | 4IN- | 19 | 13 | Input | Negative input | | 4IN+ | 18 | 12 | Input | Positive input | | 4OUT | 20 | 14 | Output | Output | | NC | 1, 5, 7, 11, 15, 17 | _ | _ | Do not connect | | VCC- | 16 | 11 | _ | Negative (lowest) supply or ground (for single-supply operation) | | VCC+ | 6 | 4 | _ | Positive (highest) supply |

Figure 5-3. RTE Package, 16-Pin WQFN (Top View)

Table 5-2. Pin Functions

	PIN	TYPE	DESCRIPTION
NAME	NO.	- ITPE	DESCRIPTION
1IN-	16	Input	Negative input
1IN+	1	Input	Positive input
10UT	15	Output	Output
2IN-	5	Input	Negative input
2IN+	4	Input	Positive input
2OUT	6	Output	Output
3IN-	8	Input	Negative input
3IN+	9	Input	Positive input
3OUT	7	Output	Output
4IN-	13	Input	Negative input
4IN+	12	Input	Positive input
4OUT	14	Output	Output
NC	3, 10	_	Do not connect
VCC-	11	_	Negative (lowest) supply or ground (for single-supply operation)
VCC+	2	_	Positive (highest) supply

Electrical Characteristics

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
OFFSET VOLTAGE
					±0.6	±3.0
		LM324B	TA = –40°C to +85°C			±4.0
VOS	Input offset voltage				±0.3	±2	mV
		LM324BA	TA = –40°C to +85°C			2.5
dVOS/dT	Input offset voltage drift	RS = 0Ω	TA = –40°C to +85°C		±7		μV/°C
PSRR	Input offset voltage versus power supply			65	100		dB
	Channel separation	f = 1kHz to 20kHz			120		dB
	INPUT VOLTAGE RANGE
		VS = 3V to 36V		V–		(V+) – 1.5
VCM	Common-mode voltage	VS = 5V to 36V, TA = –40°C to +85°C		V–		(V+) – 2	V
	Common-mode rejection	VS = 3V to 36V, (V–) ≤ VCM ≤ (V+) – 1.5V		70	80
CMRR	ratio	VS = 5V to 36V, (V–) ≤ VCM ≤ (V+) – 2V, TA = –40°C to +85°C		65	80		dB
	INPUT BIAS CURRENT
					–10	–35
IB	Input bias current	TA = –40°C to +85°C				–60	nA
dIOS/dT	Input offset current drift	TA = –40°C to +85°C		10		pA/°C
					±0.5	±4
IOS	Input offset current	TA = –40°C to +85°C				±5	nA
dIOS/dT	Input offset current drift	TA = –40°C to +85°C			10		pA/°C
NOISE
EN	Input voltage noise	f = 0.1Hz to 10Hz			3		μVPP
eN	Input voltage noise density	RS = 100Ω, VI = 0V, f = 1kHz (see Figure 6-2 for test circuit)			35		nV/√Hz
	INPUT CAPACITANCE
ZID	Differential				10 0.1		MΩ pF
ZICM	Common-mode				4 1.5		GΩ pF
OPEN-LOOP GAIN
		VS = 15V, VO = 1V to 11V, RL ≥ 10kΩ,		50	100
AOL	Open-loop voltage gain	connected to (V–)	TA = –40°C to +85°C	25			V/mV
	FREQUENCY RESPONSE
GBW	Gain-bandwidth product	RL = 1MΩ, CL = 20pF (see Figure 6-1 for test circuit)			1.2		MHz
SR	Slew rate	RL = 1MΩ, CL = 30pF, VI = ±10V (see Figure 6-1 for test circuit)			0.5		V/μs
Θm	Phase margin	G = +1, RL = 10kΩ, CL = 20pF			56		°
tS	Settling time	To 0.1%, VS = 5V, 2V step, G = +1, CL = 100pF			4		μs
	Overload recovery time	VIN × gain > VS			10		μs
THD+N	Total harmonic distortion + noise	G = +1, f = 1kHz, VO = 3.53VRMS, VS = 36V, RL = 100kΩ, IOUT ≤ 50µA, BW = 80kHz			0.001%
SLOS066AE – AUGUST 1975 – REVISED SEPTEMBER 2025 www.ti.com

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

		1	LM324BA, LM2902BA	LM	2902		LM224xx, x, LM124x	UNIT
		MIN	MAX	MIN	MAX	MIN	MAX
Supply voltage, V _CC ⁽²⁾			40		26		32	V
Differential input voltage, V _ID ⁽³⁾			±40		±26		±32	V
put voltage, V _I (either input)		-0.3	40	-0.3	26	-0.3	32	V
Duration of output short circuit (one at (or below) T _A = 25°C, V _CC ≤ 15V ⁽²⁾		Unlir	mited	Unlii	mited	Unlir	mited
Operating virtual junction temperature	re, T _J		150		150		150	°C
Case temperature for 60 seconds	FK package				-		260	°C
Lead temperature 1.6mm (1/16 inch) from case for 60 seconds	J or W package				300		300	°C
Storage temperature, T _stg		-65	150	-65	150	-65	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values (except differential voltages and V_CC specified for the measurement of I_OS) are with respect to the network GND.
(3) Differential voltages are at IN+, with respect to IN-.
(4) Short circuits from outputs to V_CC can cause excessive heating and eventual destruction.

6.2 ESD Ratings

			VALUE	UNIT
LM324B,	, LM324BA, LM2902B, LM2	902BA, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV,	LM2902KAV
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±1000
V _(ESD) Electrostatic discharge		Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±1000	V
LM124, L	M124A, LM224, LM224A, L	M324, LM324A, LM2902
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±500
V _(ESD) Electrostatic discharge		Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

| | | | LM324B, LM
LM2902B, LN | | LM2902 | | LM324xx, I
LM2902xxx | UNIT | |-----------------|---------------|------------------------|---------------------------|---------------------|--------|---------------------|-------------------------|---------------------|----| | | | | MIN | MAX | MIN | MAX | MIN | MAX | | V _CC | Supply voltag | јe | 3 | 36 | 3 | 26 | 3 | 30 | V | | V _CM | Common-mo | de voltage | 0 | V _CC – 2 | 0 | V _CC – 2 | 0 | V _CC – 2 | V | | | | LM124x | | | | | – 55 | 125 | | | Operating | LM2902xxx,
LM2902Bx | -40 | 125 | -40 | 125 | | T _A | free air | LM324Bx | -40 | 85 | | | | | °C | | | temperature | LM224xx | | | | | -25 | 85 | | | | LM324xx | | | | | 0 | 70 |

6.4 Thermal Information

| | | | | LMx24 | I, LM2902 | |---------------------------|-------------------------------------------------|-------------|--------------|-------------|------------|---------------|---------------|--------------|-------------|------------|------| | THERM | MAL METRIC ⁽¹⁾ | D
(SOIC) | DB
(SSOP) | N
(PDIP) | NS
(SO) | PW
(TSSOP) | RTE
(WQFN) | FK
(LCCC) | J
(CDIP) | W
(CFP) | UNIT | | | | 14 PINS | 14 PINS | 14 PINS | 14 PINS | 14 PINS | 16 PINS | 20 PINS | 14 PINS | 14 PINS | | R _0JA (2) (3) | Junction-to-
ambient thermal
resistance | 99.3 | 106.5 | 83.5 | 90.4 | 124.7 | 64.9 | 74.5 | 84.7 | 153.4 | °C/W | | R _θJC(top) (4) | Junction-to-case
(top) thermal
resistance | 60.4 | 55.5 | 62.0 | 48.0 | 57.9 | 68.8 | 49.9 | 37.5 | 72.7 | °C/W | | R _θJB | Junction-to-board thermal resistance | 57.5 | 56.8 | 57.7 | 49.2 | 80.7 | 40.2 | 49.0 | 72.2 | 146.5 | °C/W | | ΨЈT | Junction-to-top characterization parameter | 19.8 | 18.2 | 40.5 | 14.4 | 8.4 | 4.9 | 42.9 | 31.0 | 48.3 | °C/W | | ΨЈB | Junction-to-board characterization parameter | 57.0 | 55.8 | 57.1 | 48.8 | 79.8 | 40.0 | 48.9 | 67.3 | 129.2 | °C/W | | R ₀ JC(bot) | Junction-to-case (bottom) thermal resistance | _ | _ | _ | _ | _ | 23.6 | 7.3 | 18.8 | 10.1 | °C/W |

⁽¹⁾ For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

Short circuits from outputs to V_CC can cause excessive heating and eventual destruction.

Maximum power dissipation is a function of $T_{J(max)}$ , $R_{\theta JA}$ , and $\bar{T}_A$ . The maximum allowable power dissipation at any allowable ambient

temperature is $P_D = (T_{J(max)} - T_A) / R_{\theta JA}$ . Operating at the absolute maximum $T_J$ of 150°C can affect reliability.

(4) Maximum power dissipation is a function of $T_{J(max)}$ , $R_{\theta JA}$ , and $T_C$ . The maximum allowable power dissipation at any allowable case temperature is $P_D = (T_{J(max)} - T_C) / R_{\theta JC}$ . Operating at the absolute maximum $T_J$ of 150°C can affect reliability.

6.5 Electrical Characteristics for LM324B and LM324BA

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
OFFSET VOLTAGE
					±0.6	±3.0
		LM324B	TA = –40°C to +85°C			±4.0
VOS	Input offset voltage				±0.3	±2	mV
		LM324BA	TA = –40°C to +85°C			2.5
dVOS/dT	Input offset voltage drift	RS = 0Ω	TA = –40°C to +85°C		±7		μV/°C
PSRR	Input offset voltage versus power supply			65	100		dB
	Channel separation	f = 1kHz to 20kHz			120		dB
	INPUT VOLTAGE RANGE
		VS = 3V to 36V		V–		(V+) – 1.5
VCM	Common-mode voltage	VS = 5V to 36V, TA = –40°C to +85°C		V–		(V+) – 2	V
	Common-mode rejection	VS = 3V to 36V, (V–) ≤ VCM ≤ (V+) – 1.5V		70	80
CMRR	ratio	VS = 5V to 36V, (V–) ≤ VCM ≤ (V+) – 2V, TA = –40°C to +85°C		65	80		dB
	INPUT BIAS CURRENT
					–10	–35
IB	Input bias current	TA = –40°C to +85°C				–60	nA
dIOS/dT	Input offset current drift	TA = –40°C to +85°C		10		pA/°C
					±0.5	±4
IOS	Input offset current	TA = –40°C to +85°C				±5	nA
dIOS/dT	Input offset current drift	TA = –40°C to +85°C			10		pA/°C
NOISE
EN	Input voltage noise	f = 0.1Hz to 10Hz			3		μVPP
eN	Input voltage noise density	RS = 100Ω, VI = 0V, f = 1kHz (see Figure 6-2 for test circuit)			35		nV/√Hz
	INPUT CAPACITANCE
ZID	Differential				10 0.1		MΩ pF
ZICM	Common-mode				4 1.5		GΩ pF
OPEN-LOOP GAIN
		VS = 15V, VO = 1V to 11V, RL ≥ 10kΩ,		50	100
AOL	Open-loop voltage gain	connected to (V–)	TA = –40°C to +85°C	25			V/mV
	FREQUENCY RESPONSE
GBW	Gain-bandwidth product	RL = 1MΩ, CL = 20pF (see Figure 6-1 for test circuit)			1.2		MHz
SR	Slew rate	RL = 1MΩ, CL = 30pF, VI = ±10V (see Figure 6-1 for test circuit)			0.5		V/μs
Θm	Phase margin	G = +1, RL = 10kΩ, CL = 20pF			56		°
tS	Settling time	To 0.1%, VS = 5V, 2V step, G = +1, CL = 100pF			4		μs
	Overload recovery time	VIN × gain > VS			10		μs
THD+N	Total harmonic distortion + noise	G = +1, f = 1kHz, VO = 3.53VRMS, VS = 36V, RL = 100kΩ, IOUT ≤ 50µA, BW = 80kHz			0.001%
SLOS066AE – AUGUST 1975 – REVISED SEPTEMBER 2025 www.ti.com

Thermal Information

| | | | | LMx24 | I, LM2902 | |---------------------------|-------------------------------------------------|-------------|--------------|-------------|------------|---------------|---------------|--------------|-------------|------------|------| | THERM | MAL METRIC ⁽¹⁾ | D
(SOIC) | DB
(SSOP) | N
(PDIP) | NS
(SO) | PW
(TSSOP) | RTE
(WQFN) | FK
(LCCC) | J
(CDIP) | W
(CFP) | UNIT | | | | 14 PINS | 14 PINS | 14 PINS | 14 PINS | 14 PINS | 16 PINS | 20 PINS | 14 PINS | 14 PINS | | R _0JA (2) (3) | Junction-to-
ambient thermal
resistance | 99.3 | 106.5 | 83.5 | 90.4 | 124.7 | 64.9 | 74.5 | 84.7 | 153.4 | °C/W | | R _θJC(top) (4) | Junction-to-case
(top) thermal
resistance | 60.4 | 55.5 | 62.0 | 48.0 | 57.9 | 68.8 | 49.9 | 37.5 | 72.7 | °C/W | | R _θJB | Junction-to-board thermal resistance | 57.5 | 56.8 | 57.7 | 49.2 | 80.7 | 40.2 | 49.0 | 72.2 | 146.5 | °C/W | | ΨЈT | Junction-to-top characterization parameter | 19.8 | 18.2 | 40.5 | 14.4 | 8.4 | 4.9 | 42.9 | 31.0 | 48.3 | °C/W | | ΨЈB | Junction-to-board characterization parameter | 57.0 | 55.8 | 57.1 | 48.8 | 79.8 | 40.0 | 48.9 | 67.3 | 129.2 | °C/W | | R ₀ JC(bot) | Junction-to-case (bottom) thermal resistance | _ | _ | _ | _ | _ | 23.6 | 7.3 | 18.8 | 10.1 | °C/W |

⁽¹⁾ For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

Short circuits from outputs to V_CC can cause excessive heating and eventual destruction.

Maximum power dissipation is a function of $T_{J(max)}$ , $R_{\theta JA}$ , and $\bar{T}_A$ . The maximum allowable power dissipation at any allowable ambient

temperature is $P_D = (T_{J(max)} - T_A) / R_{\theta JA}$ . Operating at the absolute maximum $T_J$ of 150°C can affect reliability.

(4) Maximum power dissipation is a function of $T_{J(max)}$ , $R_{\theta JA}$ , and $T_C$ . The maximum allowable power dissipation at any allowable case temperature is $P_D = (T_{J(max)} - T_C) / R_{\theta JC}$ . Operating at the absolute maximum $T_J$ of 150°C can affect reliability.