LM317
LM317 3-Pin Adjustable Regulator
Manufacturer
ti
Overview
Part: LM317 3-Pin Adjustable Regulator, Texas Instruments
Type: 3-Pin Adjustable Regulator
Key Specs:
- Output voltage range: 1.25V to 37V
- Output current: 1.5A
- Line regulation: 0.01%/V (typ)
- Load regulation: 0.1% (typ)
- PSRR: 80dB at 120Hz (for CADJ = 10μF, new chip)
Features:
- Internal short-circuit current limiting
- Thermal overload protection
- Output safe-area compensation (new chip)
- Requires two external resistors to set output voltage
- Overload protection functional even if ADJUST pin is disconnected
- Can be used as a precision current regulator
- Electronic shutdown achievable by clamping adjustment terminal to ground
Applications:
- Multifunction printers
- AC drive power stage modules
- Electricity meters
- Servo drive control modules
- Merchant network and server PSU
Package:
- SOT-223 (DCY, 4-pin): 6.5mm × 7mm
- TO-263 (KTT, 3-pin): 10.16mm × 15.24mm
- TO-220 (KCS, KCT, 3-pin): 10.16mm × 4.55mm
Features
• Output voltage range:
– Adjustable: 1.25V to 37V
• Output current: 1.5A
• Line regulation: 0.01%/V (typ) • Load regulation: 0.1% (typ)
• Internal short-circuit current limiting
• Thermal overload protection
• Output safe-area compensation (new chip)
• PSRR: 80dB at 120Hz for CADJ = 10μF (new chip)
• Packages:
– 4-pin, SOT-223 (DCY)
– 3-pin, TO-263 (KTT)
– 3-pin, TO-220 (KCS, KCT), legacy chip
Applications
- Multifunction printers
- AC drive power stage modules
- Electricity meters
- Servo drive control modules
- Merchant network and server PSU
*Needed if the device is more than 6 inches from filter capacitors.
†Optional, improves transient response.
††See Equation 1.
$$V_{OUT} = 1.25V \times \left(1 + \frac{R_2}{R_1}\right) + I_{ADJ} \times (R_2)$$ (1)
Typical Application
Pin Configuration
Figure 5-2. KCS or KCT Package, 3-Pin TO-220 (Top View), Legacy Chip
Figure 5-1. DCY Package, 4-Pin SOT-223 (Top View)
Figure 5-3. KTT Package, 3-Pin TO-263 (Top View)
Pin Functions, Metal Can Packages
| | PIN |
|--------|-------------------------|--------|---------|-----|------------------------------------------------------------------------------|--|
| NAME | TO-220
(Legacy Chip) | TO-263 | SOT-223 | I/O | DESCRIPTION |
| ADJUST | 1 | 1 | 1 | — | Output voltage adjustment pin. Connect to a
resistor divider to set VOUT. |
| INPUT | 3 | 3 | 3 | I | Input voltage pin for the regulator. |
| OUTPUT | 2, TAB | 2, TAB | 2, TAB | O | Output voltage pin for the regulator. |
Electrical Characteristics
some specifications apply over the full operating temperature range as noted; unless otherwise specified, $T_J = 25$ °C, $V_{IN} - V_{OUT} = 5V$ , and $I_{OUT} = 10$ mA $^{(1)}$
| PARAMETER | TEST CONDITIO | NS (1) | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|---|
| T J = 25°C | 1.25 | ||||||
| Reference voltage | $3V \le (V_{IN} - V_{OUT})$ $10mA \le I_{OUT} \le 15$ | 1.2 | 1.25 | 1.3 | V | ||
| T J = 25°C | 0.01 | 0.04 | |||||
| Line regulation (2) | $3V \le (V_{IN} - V_{OUT})$ | ) ≤ 40V (4) | (over full operating temperature range) | 0.02 | 0.07 | %/V | |
| I O = 10mA to | V O ≤ 5V | 25 | mV | ||||
| Legacy chip | 1500mA, C ADJ = 10μF (3) , T J = 25°C | V O ≥ 5V | 0.1 | 0.5 | %V O | ||
| Load regulation | I O = 10mA to | V O ≤ 5V | 20 | 70 | mV | ||
| Load regulation | 1500mA, T J = 0°C to 125°C | V O ≥ 5V | 0.3 | 1.5 | |||
| 10mA ≤ I OUT ≤ | T J = 25°C | 0.1 | 0.5 | %Vo | |||
| New chip | I MAX (5) | (over full operating temperature range) | 0.3 | 1.5 | |||
| Thermal regulation | 20ms pulse | 0.04 | 0.07 | %/W | |||
| Adjustment pin current | Over full operatin | g temperature range | 50 | 100 | μA | ||
| Adjustment pin current change | $10\text{mA} \le I_{\text{OUT}} \le I_{\text{M}}$ $3\text{V} \le (\text{V}{\text{IN}} - \text{V}{\text{OUT}})$ | Over full operating temperature range | 0.2 | 5 | μA | ||
| Temperature stability | Legacy chip | T /T /T | Over full operating | 0.7 | %Vo | ||
| remperature stability | New chip | $T_{MIN} \le T_{J} \le T_{MAX}$ | temperature range | 1% | 70 V O | ||
| Minimum load current | $(V_{IN} - V_{OUT}) = 40$ | V | Over full operating temperature range | 3.5 | 10 | mA | |
| Current limit | (V IN − V OUT ) ≤ 15 | V | P D < P MAX (3) | 1.5 | 2.2 | _ | |
| Current limit | $(V_{IN} - V_{OUT}) = 40$ | V | $P_D < P_{MAX}$ (3), $T_J = 25$ °C | 0.15 | 0.4 | Α | |
| RMS output noise, % of V OUT | 10Hz ≤ f ≤ 10kHz | , | 0.003 | % | |||
| Lagacyahin | V OUT = 10V, f = 12 | 20Hz, C ADJ = 0µF (4) | 57 | ||||
| Legacy chip | V OUT = 10V, f = 12 | 20Hz, C ADJ = 10μF (4) | 62 | 64 | |||
| Ripple rejection ratio | Now ohio | V OUT = 10V, f = 12 operating tempera | 20Hz, C ADJ = 0µF (over full ature range) | 65 | dB | ||
| New chip | V OUT = 10V, f = 12 full operating temp | 20Hz, C ADJ = 10μF (over perature range) | 66 | 80 | |||
| Long-term stability | T J = 25°C | 0.3 | 1 | %/1k hr |
(1) For the legacy chip (unless otherwise noted), the following test conditions apply: $|V_I - V_O| = 5V$ , $I_{OMAX} = 1.5A$ , and $T_J = 0^{\circ}C$ to 125°C. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
Copyright © 2025 Texas Instruments Incorporated Product Folder Links: LM317
(2) For the legacy chip, line regulation is expressed as the percentage change in output voltage per 1V change at the input.
(3) For the legacy chip, maximum power dissipation is a function of $T_{J(max)}$ , $R_{\theta JA}$ , and $T_A$ . The maximum allowable power dissipation at any allowable ambient temperature is $P_D = (T_{J(max)} - T_A) / R_{\theta JA}$ . Operating at the absolute maximum $T_J$ of 150°C potentially affects reliability.
(4) For the legacy chip, CADJ is connected between the ADJUST pin and GND.
(5) For the new chip, regulation is measured at a constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage resulting from heating effects are covered under the specifications for thermal regulation.
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
| MIN | MAX | UNIT | |
|---|---|---|---|
| Power dissipation | Internally limited | ||
| Input-output voltage differential | −0.3 | 40 | V |
| Storage temperature, Tstg | −65 | 150 | °C |
| Operating virtual junction temperature, TJ (legacy chip) | −65 | 150 | °C |
- (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
- (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VO | Output voltage | 1.25 | 37 | V |
| VI – VO | Input-to-output differential voltage | 3 | 40 | V |
| IO | Output current | 0.01 | 1.5 | A |
| TJ | Operating virtual junction temperature | 0 | 125 | °C |
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6.4 Thermal Information (Legacy Chip)
| | | | LM | 317 |
|-----------------------|----------------------------------------------|------------------|-----------------|-----------------|-----------------|------|
| | THERMAL METRIC(1) | DCY
(SOT-223) | KCS
(TO-220) | KCT
(TO-220) | KTT
(TO-263) | UNIT |
| | | 4 PINS | 3 PINS | 3 PINS | 3 PINS |
| $R_{\theta(JA)}$ | Junction-to-ambient thermal resistance | 66.8 | 23.5 | 37.9 | 38.0 | °C/W |
| R 0JC(top) | Junction-to-case (top) thermal resistance | 43.2 | 15.9 | 51.1 | 36.5 | °C/W |
| R θJB | Junction-to-board thermal resistance | 16.9 | 7.9 | 23.2 | 18.9 | °C/W |
| ΨЈT | Junction-to-top characterization parameter | 3.6 | 3.0 | 13.0 | 6.9 | °C/W |
| ΨЈB | Junction-to-board characterization parameter | 16.8 | 7.8 | 22.8 | 17.9 | °C/W |
| R 0JC(bot) | Junction-to-case (bottom) thermal resistance | NA | 0.1 | 4.2 | 1.1 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application note.
6.5 Thermal Information (New Chip)
| | | LM | 317 |
|-----------------------|----------------------------------------------|------------------|-----------------|------|
| | THERMAL METRIC (1) (2) | DCY
(SOT-223) | KTT
(TO-263) | UNIT |
| | | 4 PINS | 3 PINS |
| $R_{\theta(JA)}$ | Junction-to-ambient thermal resistance | 59.6 | 41.0 | °C/W |
| R 0JC(top) | Junction-to-case (top) thermal resistance | 39.3 | 43.6 | °C/W |
| $R_{\theta JB}$ | Junction-to-board thermal resistance | 8.4 | 23.6 | °C/W |
| $\Psi_{JT}$ | Junction-to-top characterization parameter | 1.8 | 10.4 | °C/W |
| ΨЈB | Junction-to-board characterization parameter | 8.3 | 22.6 | °C/W |
| R 0JC(bot) | Junction-to-case (bottom) thermal resistance | _ | 0.9 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application note.
(2) When surface-mount packages are used (SOT-223), the junction to ambient thermal resistance is reduced by increasing the PCB copper area that is thermally connected to the package. See the Heat Sink Requirements section for heat sink techniques.
6.6 Electrical Characteristics
some specifications apply over the full operating temperature range as noted; unless otherwise specified, $T_J = 25$ °C, $V_{IN} - V_{OUT} = 5V$ , and $I_{OUT} = 10$ mA $^{(1)}$
| PARAMETER | TEST CONDITIO | NS (1) | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|---|
| T J = 25°C | 1.25 | ||||||
| Reference voltage | $3V \le (V_{IN} - V_{OUT})$ $10mA \le I_{OUT} \le 15$ | 1.2 | 1.25 | 1.3 | V | ||
| T J = 25°C | 0.01 | 0.04 | |||||
| Line regulation (2) | $3V \le (V_{IN} - V_{OUT})$ | ) ≤ 40V (4) | (over full operating temperature range) | 0.02 | 0.07 | %/V | |
| I O = 10mA to | V O ≤ 5V | 25 | mV | ||||
| Legacy chip | 1500mA, C ADJ = 10μF (3) , T J = 25°C | V O ≥ 5V | 0.1 | 0.5 | %V O | ||
| Load regulation | I O = 10mA to | V O ≤ 5V | 20 | 70 | mV | ||
| Load regulation | 1500mA, T J = 0°C to 125°C | V O ≥ 5V | 0.3 | 1.5 | |||
| 10mA ≤ I OUT ≤ | T J = 25°C | 0.1 | 0.5 | %Vo | |||
| New chip | I MAX (5) | (over full operating temperature range) | 0.3 | 1.5 | |||
| Thermal regulation | 20ms pulse | 0.04 | 0.07 | %/W | |||
| Adjustment pin current | Over full operatin | g temperature range | 50 | 100 | μA | ||
| Adjustment pin current change | $10\text{mA} \le I_{\text{OUT}} \le I_{\text{M}}$ $3\text{V} \le (\text{V}{\text{IN}} - \text{V}{\text{OUT}})$ | Over full operating temperature range | 0.2 | 5 | μA | ||
| Temperature stability | Legacy chip | T /T /T | Over full operating | 0.7 | %Vo | ||
| remperature stability | New chip | $T_{MIN} \le T_{J} \le T_{MAX}$ | temperature range | 1% | 70 V O | ||
| Minimum load current | $(V_{IN} - V_{OUT}) = 40$ | V | Over full operating temperature range | 3.5 | 10 | mA | |
| Current limit | (V IN − V OUT ) ≤ 15 | V | P D < P MAX (3) | 1.5 | 2.2 | _ | |
| Current limit | $(V_{IN} - V_{OUT}) = 40$ | V | $P_D < P_{MAX}$ (3), $T_J = 25$ °C | 0.15 | 0.4 | Α | |
| RMS output noise, % of V OUT | 10Hz ≤ f ≤ 10kHz | , | 0.003 | % | |||
| Lagacyahin | V OUT = 10V, f = 12 | 20Hz, C ADJ = 0µF (4) | 57 | ||||
| Legacy chip | V OUT = 10V, f = 12 | 20Hz, C ADJ = 10μF (4) | 62 | 64 | |||
| Ripple rejection ratio | Now ohio | V OUT = 10V, f = 12 operating tempera | 20Hz, C ADJ = 0µF (over full ature range) | 65 | dB | ||
| New chip | V OUT = 10V, f = 12 full operating temp | 20Hz, C ADJ = 10μF (over perature range) | 66 | 80 | |||
| Long-term stability | T J = 25°C | 0.3 | 1 | %/1k hr |
(1) For the legacy chip (unless otherwise noted), the following test conditions apply: $|V_I - V_O| = 5V$ , $I_{OMAX} = 1.5A$ , and $T_J = 0^{\circ}C$ to 125°C. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
Copyright © 2025 Texas Instruments Incorporated Product Folder Links: LM317
(2) For the legacy chip, line regulation is expressed as the percentage change in output voltage per 1V change at the input.
(3) For the legacy chip, maximum power dissipation is a function of $T_{J(max)}$ , $R_{\theta JA}$ , and $T_A$ . The maximum allowable power dissipation at any allowable ambient temperature is $P_D = (T_{J(max)} - T_A) / R_{\theta JA}$ . Operating at the absolute maximum $T_J$ of 150°C potentially affects reliability.
(4) For the legacy chip, CADJ is connected between the ADJUST pin and GND.
(5) For the new chip, regulation is measured at a constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage resulting from heating effects are covered under the specifications for thermal regulation.
6.7 Typical Characteristics
Figure 6-3. Load Regulation (New Chip)
-75 -50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 6-5. Load Transient Response (Legacy Chip)
Figure 6-2. Load Regulation (Legacy Chip)
Figure 6-4. Load Transient Response (Legacy Chip)
Figure 6-6. Load Transient Response (New Chip)
6.7 Typical Characteristics (continued)
Figure 6-7. Line Regulation (Legacy Chip)
Figure 6-8. Output Voltage vs Input Voltage, VOUT = VREF (New Chip)
Figure 6-9. Output Voltage vs Input Voltage, $V_{OUT}$ = 5V (New Chip)
Figure 6-10. Ripple Rejection vs Output Current (Legacy Chip)
Figure 6-11. Ripple Rejection vs Output Voltage (Legacy Chip)
Figure 6-12. Ripple Rejection vs Frequency (Legacy Chip)
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