LD39050

Low Dropout (LDO) Voltage Regulator

The LD39050 is a low dropout (ldo) voltage regulator from STMicroelectronics. View the full LD39050 datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Overview

Part: LD39050 — STMicroelectronics

Type: Low Dropout (LDO) Voltage Regulator

Description: 500 mA low quiescent current and low noise voltage regulator with an input voltage range from 1.5 V to 5.5 V, 200 mV typical dropout, and available in fixed or adjustable output versions.

Operating Conditions:

Supply voltage: 1.5 to 5.5 V
Operating junction temperature: -40 to 125 °C
Output current: up to 500 mA

Absolute Maximum Ratings:

Max supply voltage: 7 V
Max junction/storage temperature: 150 °C

Key Specs:

Dropout voltage: 200 mV typ. at 500 mA (V OUT fixed to 1.5 V)
Output noise voltage: 30 μV RMS typ. (10 Hz to 100 kHz, I OUT = 100 mA, V OUT = 0.8 V)
Quiescent current (no load): 20 μA typ.
Quiescent current (500 mA load): 100 μA typ.
Quiescent current (OFF mode): 0.001 μA typ., 1 μA max.
Supply voltage rejection: 65 dB typ. at 1 kHz (V OUT = 0.8 V, I OUT = 10 mA)
Short-circuit current: 800 mA typ.
Thermal shutdown: 160 °C typ.

Features:

Ultra low-dropout voltage
Very low quiescent current
Very low noise without bypass capacitor
Output voltage tolerance: ± 2.0% @ 25 °C
Logic-controlled electronic shutdown
Compatible with ceramic capacitor C OUT = 1 μF
Internal current and thermal limit
Power Good function

Applications:

Mobile phones
Hard disks
Battery-powered systems

Package:

DFN6 (3x3 mm)
DFN6 (2x2 mm)

Features

Input voltage from 1.5 to 5.5 V
Ultra low-dropout voltage (200 mV typ. at 500 mA load)
Very low quiescent current (20 μA typ. at no load, 100 μA typ. at 500 mA load, 1 μA max. in OFF mode)
Very low noise without bypass capacitor
Output voltage tolerance: ± 2.0% @ 25 °C
500 mA guaranteed output current
Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and adjustable from 0.8 V
Logic-controlled electronic shutdown
Compatible with ceramic capacitor C OUT = 1 μF
Internal current and thermal limit
Package DFN6 (3x3 mm) and DFN6 (2x2 mm)
Temperature range: from -40 °C to 125 °C

Pin Configuration

Figure 3. DFN6 (3x3 mm) pin connection (top view)

Figure 4. DFN6 (2x2 mm) pin connection (top view)

Table 1. Pin description

Symbol	Pin n° for DFN6 (3x3 mm)	Pin n° for DFN6 (3x3 mm)	Pin n° for DFN6 (2x2 mm)	Pin n° for DFN6 (2x2 mm)	Function
Symbol	LD39050 (adjustable)	LD39050 (fixed)	LD39050 (adjustable)	LD39050 (fixed)	Function
EN	1	1	2	2	Enable pin logic input: low = shutdown, high = active
GND	2	2	3	3	Common ground
PG	3	3	4	4	Power Good
VOUT	4	4	5	5	Output voltage
ADJ	5	-	6	-	Adjustable pin
VIN	6	6	1	1	Input voltage of the LDO
N.C.	-	5	-	6	Not connected
GND	Exposed pad	Exposed pad	Exposed pad	Exposed pad	Exposed pad must be connected to GND

Table 1. Pin description

Electrical Characteristics

T J = 25 °C, V IN = 1.8 V, C IN = C OUT = 1 μF, I OUT = 10 mA, V EN = V IN , unless otherwise specified.

Table 5. Electrical characteristics for the LD39050 (adjustable)

Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
V IN	Operating input voltage		1.5		5.5	V
V ADJ	V ADJ accuracy	I OUT = 10 mA, T J = 25 °C	784	800	816	mV
V ADJ	V ADJ accuracy	I OUT = 10 mA, -40 °C < T J < 125 °C	776	800	824
I ADJ	Adjustable pin current				1	μA
∆ V OUT	Static line regulation	V OUT +1 V ≤ V IN ≤ 5.5 V, I OUT = 1 mA		0.01		%/V
∆ V OUT	Transient line regulation (1)	∆ V IN = 500 mV, I OUT = 10 mA, t R = 5 μs		10		mVpp
∆ V OUT	Transient line regulation (1)	∆ V IN = 500 mV, I OUT = 10 mA, t F = 5 μs		10		mVpp
∆ V OUT	Static load regulation	I OUT = 10 mA to 500 mA		0.002		%/mA
∆ V OUT	Transient load regulation (1)	I OUT = 10 mA to 500 mA, t R = 5 μs I = 10 mA to 500 mA, t = 5 μs		40 40		mVpp
V DROP	Dropout voltage (2)	I O = 500 mA, V OUT fixed to 1.5 V 40 °C < T J < 125 °C		200	400	mV
e N	Output noise voltage	10 Hz to 100 kHz, I OUT = 100 mA, V OUT = 0.8 V		30		μV RMS
SVR	Supply voltage rejection V OUT = 0.8 V	V IN = 1.8 V+/-V RIPPLE V RIPPLE = 0.25 V, frequency = 1 kHz I OUT = 10 mA		65		dB
SVR	Supply voltage rejection V OUT = 0.8 V	V IN = 1.8 V+/-V RIPPLE V RIPPLE = 0.25 V, frequency =10 kHz I OUT = 100 mA		62		dB
I Q	Quiescent current	I OUT = 0 mA		20		μA
I Q	Quiescent current	I OUT = 0 mA, -40 °C < T J < 125 °C			50	μA
I Q	Quiescent current	I OUT = 0 to 500 mA		100		μA
I Q	Quiescent current	I OUT = 0 to 500 mA, -40 °C<T J <125 °C			200	μA
I Q	Quiescent current	V IN input current in OFF mode: V EN = GND (3)		0.001	1	μA

Table 5. Electrical characteristics for the LD39050 (adjustable)

Table 5. Electrical characteristics for the LD39050 (adjustable) (continued)

Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
PG	Power Good output threshold	Rising edge		0.92* V OUT		V
PG	Power Good output threshold	Falling edge		0.8* V OUT		V
PG	Power Good output voltage low	I sink = 6 mA open drain output			0.4	V
I SC	Short-circuit current	R L = 0	600	800		mA
V EN	Enable input logic low	V IN = 1.5 V to 5.5 V, 40 °C < T J < 125 °C			0.4	V
V EN	Enable input logic high	V IN = 1.5 V to 5.5 V, 40 °C < T J < 125 °C	0.9			V
I EN	Enable pin input current	V EN = V IN		0.1	100	nA
t ON	Turn-on time (4)			30		μs
T SHDN	Thermal shutdown			160		°C
T SHDN	Hysteresis			20		°C
C OUT	Output capacitor	Capacitance (see typical performance characteristics for stability)	1		22	μF

TJ = 25 °C, V IN = V OUT(NOM) + 1 V, C IN = C OUT = 1 μF, I OUT = 10 mA, V EN = V IN , unless otherwise specified.

Table 6. Electrical characteristics for the LD39050 (fixed output)

Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
V IN	Operating input voltage		1.5		5.5	V
V OUT	V OUT accuracy	V OUT >1.5 V, I OUT = 10 mA, T J = 25 °C	-2		2	%
V OUT	V OUT accuracy	V OUT >1.5 V, I OUT = 10 mA, -40 °C<T J <125 °C	-3		3	%
V OUT	V OUT accuracy	V OUT ≤ 1.5 V, I OUT = 10 mA		± 20		mV
V OUT	V OUT accuracy	V OUT ≤ 1.5 V, I OUT = 10 mA, -40 °C<T J <125 °C		± 30		mV
∆ V OUT	Static line regulation	V OUT +1 V ≤ V IN ≤ 5.5 V, I OUT = 1 mA		0.01		%/V
∆ V OUT	Transient line regulation (1)	∆ V IN = 500 mV, I OUT = 10 mA, t R = 5 μs		10		mVpp
∆ V OUT	Transient line regulation (1)	∆ V IN = 500 mV, I OUT = 10 mA, t F = 5 μs		10		mVpp
∆ V OUT	Static load regulation	I OUT = 10 mA to 500 mA		0.002		%/mA
∆ V OUT	Transient load regulation (1)	I OUT = 10 mA to 500 mA, t R = 5 μs		40 40		mVpp
V DROP	Dropout voltage (2)	I OUT = 10 mA to 500 mA, t F = 5 μs I OUT = 500 mA, V OUT > 1.5 V -40 °C < T J < 125 °C		200	400	mV
e N	Output noise voltage	10 Hz to 100 kHz, I O = 100 mA,		30		μV RMS
SVR	Supply voltage rejection V = 1.5 V	V IN = V OUT(NOM ) + 0.5 V+/-V RIPPLE V RIPPLE = 0.1 V, freq. = 1 kHz I OUT = 10 mA		65		dB
SVR	OUT	V IN = V OUT(NOM) + 0.5 V+/- V RIPPLE V RIPPLE = 0.1 V, frequency =10 kHz I OUT = 100 mA		62		dB
I Q	Quiescent current	I OUT = 0 mA		20		μA
I Q	Quiescent current	I OUT = 0 mA, -40 °C < T J < 125 °C			50	μA
I Q	Quiescent current	I OUT = 0 to 500 mA		100		μA
I Q	Quiescent current	I OUT = 0 to 500 mA -40 °C < T J < 125 °C			200	μA
I Q	Quiescent current	V IN input current in OFF mode: V EN = GND (3)		0.001	1	μA

Table 6. Electrical characteristics for the LD39050 (fixed output)

Table 6. Electrical characteristics for the LD39050 (fixed output) (continued)

Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
PG	Power Good output threshold	Rising edge		0.92* V OUT		V
PG		Falling edge		0.8* V OUT		V
PG	Power Good output voltage low	I sink = 6 mA open drain output			0.4	V
I SC	Short-circuit current	R L = 0	600	800		mA
V EN	Enable input logic low	V IN = 1.5 V to 5.5 V, - 40 °C < T J < 125 °C			0.4	V
V EN	Enable input logic high	V IN = 1.5 V to 5.5 V, -40 °C < T J < 125 °C	0.9			V
I EN	Enable pin input current	V EN = V IN		0.1	100	nA
t ON	Turn-on time (4)			30		μs
T SHDN	Thermal shutdown			160		°C
T SHDN	Hysteresis			20		°C
C OUT	Output capacitor	Capacitance (see typical performance characteristics for stability)	1		22	μF

Turn-on time is time measured between the enable input just exceeding V EN high value and the output voltage just reaching 95% of its nominal value

Absolute Maximum Ratings

Table 2. Absolute maximum ratings

Symbol	Parameter	Value	Unit
V IN	DC input voltage	-0.3 to 7	V
V OUT	DC output voltage	-0.3 to V I + 0.3 (7 V max.)	V
EN	Enable pin	-0.3 to V I + 0.3 (7 V max.)	V
PG	Power Good pin	-0.3 to 7	V
ADJ	Adjustable pin	4	V
I OUT	Output current	Internally limited
P D	Power dissipation	Internally limited
T STG	Storage temperature range	- 65 to 150	°C
T OP	Operating junction temperature range	- 40 to 125	°C

Note:

Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND.

Table 3. Thermal data

Symbol	Parameter	Value	Value	Unit
		DFN6 (2x2 mm)	DFN6 (3x3 mm)
R thJA	Thermal resistance junction-ambient	65	55	°C/W
R thJC	Thermal resistance junction-case	6.5	10	°C/W

Table 4. ESD performance

Symbol	Parameter	Test conditions	Value	Unit
ESD	ESD protection voltage	HBM	2	kV
ESD	ESD protection voltage	CDM	500	V
ESD	ESD protection voltage	MM	0.3	kV

Table 4. ESD performance

Typical Application

The LD39050 is an ultra low-dropout linear regulator. It provides up to 500 mA with a 200 mV dropout. The input voltage range is from 1.5 V to 5.5 V. The device is available in fixed and adjustable output versions.

The regulator is equipped with internal protection circuitry, such as short-circuit current limiting and thermal protection.

The regulator is designed to be stable with ceramic capacitors on the input and the output. The recommended values of the input and output ceramic capacitors are from 1 μF to 22 μF with 1 μF typical. The input capacitor must be connected within 0.5 inches of the V IN terminal. The output capacitor must also be connected within 0.5 inches of output pin. There is no upper limit to the value of the input capacitor.

Figure 35 and Figure 36 illustrate the typical application schematics:

Figure 35. Application schematic for fixed version

Figure 36. Application schematic for adjustable version

Regarding to the adjustable version, the output voltage can be adjusted from 0.8 V up to the input voltage minus the voltage drop across the PMOS (dropout voltage), by connecting a resistor divider between the ADJ pin and the output, thus allowing the remote voltage sensing.

The resistor divider should be selected using the following equation:

V_OUT= V_ADJ≤ft(1 + R₁/ R₂right)withV_ADJ= 0 . 8 vee(typ.)

Resistors should be used with values in the range from 10 k Ω to 50 k Ω . Lower values can also be suitable, but they increase current consumption.

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
LD39050PU33R	STMicroelectronics	6-VDFN Exposed Pad

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